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-- VHDL Test Bench Created from source file Processor.vhd -- 07-MAY-2008 01:09:40

---  25 October 2010 Ian Chapman

--   ******************************************************

---- Distributed under the GNU General Public License.    *

---- This can be obtained from “www.gnu.org”.             *

--   ******************************************************

--    This program is free software: you can redistribute it and/or modify

--    it under the terms of the GNU General Public License as published by

--    the Free Software Foundation, either version 3 of the License, or

--    (at your option) any later version.

--

--    This program is distributed in the hope that it will be useful,

--    but WITHOUT ANY WARRANTY; without even the implied warranty of

--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--    GNU General Public License for more details.

--

--    You should have received a copy of the GNU General Public License

--    along with this program.  If not, see <http://www.gnu.org/licenses/>

--

-- Notes: 

-- 1) This testbench template has been automatically generated using types

-- std_logic and std_logic_vector for the ports of the unit under test.

-- Lattice recommends that these types always be used for the top-level

-- I/O of a design in order to guarantee that the testbench will bind

-- correctly to the timing (post-route) simulation model.

-- 2) To use this template as your testbench, change the filename to any

-- name of your choice with the extension .vhd, and use the "source->import"

-- menu in the ispLEVER Project Navigator to import the testbench.

-- Then edit the user defined section below, adding code to generate the 

-- stimulus for your design.

-- 3) VHDL simulations will produce errors if there are Lattice FPGA library 

-- elements in your design that require the instantiation of GSR, PUR, and

-- TSALL and they are not present in the testbench. For more information see

-- the How To section of online help.  

--

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

ENTITY testbench IS

END testbench;

ARCHITECTURE behavior OF testbench IS

        COMPONENT Processor

        PORT(

                clk_pin : IN std_logic;

--              data_wr : inout unsigned(7 downto 0);

                Pwr_on_pin : out std_logic;

                rst_pin, irq_pin, nmi_pin : IN std_logic;

                RX_pin : in std_logic;

                Tx_pin : out std_logic

                );

        END COMPONENT;

        SIGNAL clk :  std_logic;

        signal RX_pin, TX_pin : std_logic;

        SIGNAL rst, nmi, irq :  std_logic;

--      signal data_wr : unsigned(7 downto 0);

BEGIN

-- Please check and add your generic clause manually

        uut: Processor PORT MAP(

                clk_pin => clk,

                irq_pin => irq,

                nmi_pin => nmi,

                RX_pin  => RX_pin,

                TX_pin  => TX_pin,

--              data_wr => data_wr,

                rst_pin => rst

        );

-- *** Test Bench - User Defined Section ***

clock : process

        begin

                clk <= '0';

        wait for 50 ns;

                clk <= '1';

        wait for 50 ns;

end process;

reset: process

        begin

        rst <= '0';

        wait for 175 ns;

        rst <= '1';

        wait; -- will wait forever

   END PROCESS;

--rx_232 : process

--      begin

--      RX_pin <= '1';

--      wait for 5 us;

--      RX_pin <= '0';

--      wait for 104 us;

--      RX_pin <= '1';

--      wait for 208 us;

--      RX_pin <= '0';

--      wait for 104 us;

--      RX_pin <= '1';

--      wait for 208 us;

--      RX_pin <= '0';

--      wait for 208 us;

--      RX_pin <= '1';

--      WAIT;

--END PROCESS;

interrupt: process

        begin

        irq <= '1';

        nmi <= '1';

        wait for 2 us;

        irq <= '1';

        nmi <= '1';

        wait for 100 ns;

        irq <= '1';

        nmi <= '1';

        wait;   --will wait forever

   END PROCESS;

-- *** End Test Bench - User Defined Section ***

END behavior;