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stanley82 |
------------------------------------------------------------------
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-- 6502 principal module.
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--
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-- Copyright Ian Chapman October 28 2010
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--
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-- This file is part of the Lattice 6502 project
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-- It is used to compile with Linux ghdl and ispLeaver.
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--
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--
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-- To do
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-- Detailed test of all instructions.
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--
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-- *************************************************************
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-- Distributed under the GNU Lesser General Public License. *
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-- This can be obtained from “www.gnu.org”. *
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-- *************************************************************
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>
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--
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-- 65C02.vhd
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--- Purpose to test and exercise my VHLD skills
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---- I've decided not to support 65C02 instructions
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---- nor BCD arithmetic.
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---- I will make it run as fast as I can. Timing not per a real 6502
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---- Lattice EBI has clocked address inputs, so as not to add a cycle
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---- 6502 address outputs are not latched. The data output of the EBI ROM and
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---- RAM is not clocked.
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---- To maintain speed the 6502 address to ROM/RAM is not clocked and the data
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---- returned is not clocked by ROM/RAM. Structures of form address <= address + "1";
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---- cause a race condition. I had to store the address from the mux for
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---- INC type instructions ie read then write.
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----
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---- One boob I've just noticed jsr and pha in the 6502 work opposite to
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---- what I expected ie jsr decrements the stack and I inc it. I guess
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---- that was the way my first computer the SDS sigma 2 did it. I'll keep
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---- like that for now in case a bigger stack is needed. Oh no a sigma 2
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---- did not have a stack only L link register.
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----
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-- I used this to set the hold timing default "-exp parHoldLimit=999"
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-- Also path based placement on
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-- When generating a Lattice ROM/RAM untick latche outputs and use
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-- the *.mem file generated with my asm2rom.pl script.
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------------------------------------------------------------------------------------
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-- TO Do
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-- 1 DONE Update all address modes of cmp, cpx and cpy per #mode
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-- 2 DONE Add rol, ror, asl, lsr, per inc and dec
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-- 3 DONE Correct flags in all modes of item 2
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-- 4 Update the stack instructions, I've it pushing up not down.
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-- 5 Continue testing
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-- 6 DONE Get a kernel up to test each and every instruction
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-- 7 Test all instructions
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-- 7 Add the 65C02 stuff. I think the most needed is phx, phy, plx
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-- and ply are the most useful.
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------------------------------------------------------------------------------------
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library IEEE; --Use standard IEEE libs as recommended by Tristan.
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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entity P65C02 is
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Port (
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clock: in std_logic;
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reset : in std_logic;
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data_wr: out unsigned(7 downto 0);
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data_rd: in unsigned(7 downto 0);
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proc_write: inout std_logic;
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irq: in std_logic; --Active 0
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nmi: in std_logic; --Neg transition.
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-- cycle_mark : out std_logic;
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-- add_hold : inout unsigned(15 downto 14);
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address: inout unsigned(15 downto 0)
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);
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end P65C02;
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architecture P65C02_architecture of P65C02 is
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------------------------------------------------------------------------
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-- Signal Declarations
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------------------------------------------------------------------------
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signal reg_pc : unsigned(15 downto 0);
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signal add_hold : unsigned(15 downto 0);
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signal reg_a : unsigned(8 downto 0);
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signal reg_x, reg_y, reg_s, reg_sp : unsigned(7 downto 0);
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signal Instruction_in, dat_in1, dat_in2, dat_out1, dat_out2 : unsigned(7 downto 0);
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signal n_fg, v_fg, b_fg, d_fg, i_fg, z_fg, v_ff : std_logic;
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signal cycle_ctr, add_fg : unsigned(3 downto 0);
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signal wr_ctr, flags_fg : unsigned(1 downto 0);
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signal reset_fg, irq_fg, nmi_fg, start_fg, pc_inc_fg, branch_fg: std_logic;
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signal pc_dec_fg, dat2pc_fg : std_logic;
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-- End of signal declarations
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begin --architecture
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-- =======================================================
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read_mem:process (clock, reset)
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begin
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if reset = '0' then
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dat_in1 <= (others => '0');
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dat_in2 <= (others => '0');
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instruction_in <= (others => '0');
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elsif rising_edge(clock) then
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dat_in2 <= dat_in1;
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dat_in1 <= data_rd;
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-- if cycle_ctr = x"0" and start_fg = '0' then
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if cycle_ctr = x"0" then
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if irq = '0' or nmi = '0' or (reset = '1' and reset_fg = '0') then
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Instruction_in <= x"00";
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else
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Instruction_in <= data_rd;
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end if;
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end if;
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end if;
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end process read_mem;
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-- =======================================================
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Prog_ptr:process (clock, reset, pc_dec_fg)
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begin
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if reset = '0' then
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reg_pc <= x"FFFC";
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elsif rising_edge(clock) then
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if dat2pc_fg = '1' then
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reg_pc(15 downto 8) <= data_rd;
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reg_pc(7 downto 0) <= dat_in1;
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elsif (cycle_ctr = X"0" and not(irq = '0' or nmi = '0' )) or pc_inc_fg = '1' then
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reg_pc <= reg_pc + x"0001";
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elsif pc_dec_fg = '1' then
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reg_pc <= reg_pc - x"0001";
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-- elsif cycle_ctr = x"0" and irq = '0' and i_fg = '0' then
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-- reg_pc <= reg_pc - x"0001";
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elsif branch_fg = '1' then
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reg_pc <= reg_pc + (dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1(7) & dat_in1);
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end if;
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end if;
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end process Prog_ptr;
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addressing:process (clock, reset, reg_PC, add_fg)
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begin
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if reset = '0' then
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address <= reg_pc;
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-- elsif rising_edge(clock) then
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else
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Case add_fg is
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when x"0" =>
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address <= reg_pc;
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when x"1" => --Zero page
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if proc_write = '0' then
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address(7 downto 0) <= data_rd;
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else
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address(7 downto 0) <= dat_in1;
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end if;
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address(15 downto 8) <= x"00";
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when x"2" => --Zero page, x
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if proc_write = '0' then
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address(7 downto 0) <= data_rd + reg_x;
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else
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address(7 downto 0) <= dat_in1 + reg_x;
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end if;
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address(15 downto 8) <= x"00";
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when x"3" => --Zero page, y
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if proc_write = '0' then
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address(7 downto 0) <= data_rd + reg_y;
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else
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address(7 downto 0) <= dat_in1 + reg_y;
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end if;
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address(15 downto 8) <= x"00";
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when x"4" => --Absolute Return sub etc
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if proc_write = '0' then
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address <= data_rd & dat_in1;
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else
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address <= dat_in1 & dat_in2;
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end if;
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when x"5" => --Absolute, x
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if proc_write = '0' then
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address <= data_rd & dat_in1 + reg_x;
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else
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address <= dat_in1 & dat_in2 + reg_x;
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end if;
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when x"6" => --Absolute, y
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address <= (data_rd & dat_in1) + reg_y;
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if proc_write = '0' then
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address <= data_rd & dat_in1 + reg_y;
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else
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address <= dat_in1 & dat_in2 + reg_y;
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end if;
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when x"7" => --Stack pointer
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address <= x"01" & reg_sp; --msb should be hex 01
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when x"8" => --Reset 1st byte
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address <= x"FFFC";
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when x"9" => --IRQ and Break 1st byte
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address <= x"FFFE";
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when x"A" => --NMI and Break 1st byte
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address <= x"FFFA";
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when x"B" => --address + 1
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address <= add_hold + "1";
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when x"C" => --(zero),y
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address(7 downto 0) <= dat_in1 + "1";
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address(15 downto 8) <= x"00";
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when x"D" => --(zero,x)
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address(7 downto 0) <= dat_in1 + reg_x + "1";
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address(15 downto 8) <= x"00";
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when x"F" => --Hold address steady for INC etc
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-- address <= address;
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address <= add_hold;
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when others =>
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address <= reg_pc;
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end case;
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end if;
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end process addressing;
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hold_address:process(clock, reset, address)
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begin --hold address bus for inc type instructions.
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if reset = '0' then
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add_hold <= (others => '0');
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elsif rising_edge(clock) then
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add_hold <= address;
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end if;
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end process hold_address;
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memory_proc_write:process(clock, reset, wr_ctr)
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begin
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if reset = '0' then
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data_wr <= (others => '0');
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proc_write <= '0';
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elsif rising_edge(clock) then
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proc_write <= wr_ctr(0) or wr_ctr(1);
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if wr_ctr = "01" then
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data_wr <= dat_out1;
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elsif wr_ctr = "10" then
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data_wr <= dat_out2;
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else
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data_wr <= x"22";
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end if;
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end if;
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end process memory_proc_write;
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instruction_decode:process (clock, reset, irq, nmi)
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begin
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if reset = '0' then
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cycle_ctr <= (others => '0');
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-- cycle_mark <= '0';
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pc_inc_fg <= '0';
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pc_dec_fg <= '0';
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dat2pc_fg <= '0';
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add_fg <= (others => '0');
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branch_fg <= '0';
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flags_fg <= (others => '0');
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wr_ctr <= "00";
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reg_a <= (others => '0');
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reg_x <= (others => '0');
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reg_y <= (others => '0');
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reg_s <= (others => '0');
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reg_sp <= (others => '0');
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n_fg <= '0';
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v_fg <= '0';
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b_fg <= '0';
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d_fg <= '0';
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i_fg <= '0';
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z_fg <= '0';
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reset_fg <= '0';
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start_fg <= '0';
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v_ff <= '0';
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nmi_fg <= '0';
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irq_fg <= '0';
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dat_out1 <= (others => '0');
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dat_out2<= (others => '0');
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--elsif rising_edge(clock) and run_fg = '1' then
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elsif rising_edge(clock) then
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-- v_ff <= dat_out2(7); --Used to track the v_fg
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reset_fg <= reset;
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-- This section is to get started
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if reset = '1' and reset_fg = '0' then
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start_fg <= '1';
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wr_ctr <= "00";
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add_fg <= x"8"; --get start up vectors FFFC FFFD
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cycle_ctr <= x"5"; --Jump into cycle 5 add_fg <= x'8'
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-- end if;
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else
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case cycle_ctr is --cycle counter case
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when x"0" =>
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-- cycle_mark <= '1';
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if reset_fg = '1' and reset = '1' then
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if flags_fg /= "00" then
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n_fg <= dat_out2(7);
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if dat_out2 = x"00" then
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z_fg <= '1';
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else
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z_fg <= '0';
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end if;
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end if;
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if flags_fg = "10" then
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start_fg <= '0';
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v_fg <= reg_a(7) xnor v_ff; --Add V_ff true overflow possible
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-- --Sub V_ff false underflow possible
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end if;
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flags_fg <= "00";
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end if;
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| 326 |
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| 327 |
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if irq = '0' and i_fg = '0' then
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| 328 |
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irq_fg <= '1';
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b_fg <= '0';
|
| 330 |
|
|
pc_dec_fg <= '1';
|
| 331 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 332 |
|
|
elsif nmi = '0' and i_fg = '0' then
|
| 333 |
|
|
nmi_fg <= '1';
|
| 334 |
|
|
b_fg <= '0';
|
| 335 |
|
|
pc_dec_fg <= '1';
|
| 336 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 337 |
|
|
else
|
| 338 |
|
|
|
| 339 |
|
|
case data_rd is
|
| 340 |
|
|
|
| 341 |
|
|
-- ===========================================================================================
|
| 342 |
|
|
when x"48" => --PHA 1st part accumulator onto stack
|
| 343 |
|
|
wr_ctr <= "01";
|
| 344 |
|
|
dat_out1 <= reg_a(7 downto 0);
|
| 345 |
|
|
pc_dec_fg <= '1';
|
| 346 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 347 |
|
|
|
| 348 |
|
|
when x"08" => --PHP 1st part status onto stack
|
| 349 |
|
|
wr_ctr <= "01";
|
| 350 |
|
|
dat_out1 <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8);
|
| 351 |
|
|
pc_dec_fg <= '1';
|
| 352 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 353 |
|
|
|
| 354 |
|
|
when x"68" => --PLA 1st part Pull Accumulator from Stack
|
| 355 |
|
|
reg_sp <= reg_sp - "1";
|
| 356 |
|
|
pc_dec_fg <= '1';
|
| 357 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 358 |
|
|
|
| 359 |
|
|
when x"28" => --PLP 1st part pull old status from stack
|
| 360 |
|
|
reg_sp <= reg_sp - "1";
|
| 361 |
|
|
pc_dec_fg <= '1';
|
| 362 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 363 |
|
|
|
| 364 |
|
|
when x"18" => --CLC clear carry
|
| 365 |
|
|
reg_a(8) <= '0';
|
| 366 |
|
|
-- pc_dec_fg <= '1';
|
| 367 |
|
|
cycle_ctr <= x"0";
|
| 368 |
|
|
|
| 369 |
|
|
when x"38" => --SEC set carry
|
| 370 |
|
|
reg_a(8) <= '1';
|
| 371 |
|
|
cycle_ctr <= x"0";
|
| 372 |
|
|
when x"58" => --CLI Clear interrupt Disable Bit
|
| 373 |
|
|
i_fg <= '0';
|
| 374 |
|
|
cycle_ctr <= x"0";
|
| 375 |
|
|
|
| 376 |
|
|
when x"78" => --SEI Set interrupt Disable Status
|
| 377 |
|
|
i_fg <= '1';
|
| 378 |
|
|
cycle_ctr <= x"0";
|
| 379 |
|
|
when x"88" => --DEY Decrement y reg
|
| 380 |
|
|
reg_y <= reg_y - "1";
|
| 381 |
|
|
flags_fg <= "01";
|
| 382 |
|
|
dat_out2 <= reg_y - "1";
|
| 383 |
|
|
cycle_ctr <= x"0";
|
| 384 |
|
|
when x"98" => --TYA transfer Y to A
|
| 385 |
|
|
reg_a(7 downto 0) <= reg_y;
|
| 386 |
|
|
flags_fg <= "01";
|
| 387 |
|
|
dat_out2 <= reg_y;
|
| 388 |
|
|
cycle_ctr <= x"0";
|
| 389 |
|
|
when x"A8" => --TAY transfer A to Y
|
| 390 |
|
|
reg_y <= reg_a(7 downto 0);
|
| 391 |
|
|
flags_fg <= "01";
|
| 392 |
|
|
dat_out2 <= reg_a(7 downto 0);
|
| 393 |
|
|
cycle_ctr <= x"0";
|
| 394 |
|
|
when x"B8" => --CLV clear overflow flag
|
| 395 |
|
|
v_fg <= '0';
|
| 396 |
|
|
pc_dec_fg <= '1';
|
| 397 |
|
|
cycle_ctr <= x"0";
|
| 398 |
|
|
when x"C8" => --INY increment Y reg
|
| 399 |
|
|
reg_y <= reg_y + x"1";
|
| 400 |
|
|
flags_fg <= "01";
|
| 401 |
|
|
dat_out2 <= reg_y + x"1";
|
| 402 |
|
|
cycle_ctr <= x"0";
|
| 403 |
|
|
when x"D8" => --CLD Clear decimnal flag
|
| 404 |
|
|
d_fg <= '0';
|
| 405 |
|
|
cycle_ctr <= x"0";
|
| 406 |
|
|
when x"E8" => --INX increment X reg
|
| 407 |
|
|
reg_x <= reg_x + x"1";
|
| 408 |
|
|
flags_fg <= "01";
|
| 409 |
|
|
dat_out2 <= reg_x + x"1";
|
| 410 |
|
|
cycle_ctr <= x"0";
|
| 411 |
|
|
when x"F8" => --SLD Set decimnal flag
|
| 412 |
|
|
d_fg <= '1';
|
| 413 |
|
|
cycle_ctr <= x"0";
|
| 414 |
|
|
when x"2A" => --ROL A Rotate Left one bit 1st part.
|
| 415 |
|
|
reg_a(8 downto 1) <= reg_a(7 downto 0);
|
| 416 |
|
|
reg_a(0) <= reg_a(8);
|
| 417 |
|
|
dat_out2(7 downto 1) <= reg_a(6 downto 0);
|
| 418 |
|
|
dat_out2(0) <= reg_a(8);
|
| 419 |
|
|
flags_fg <= "01";
|
| 420 |
|
|
cycle_ctr <= x"0";
|
| 421 |
|
|
when x"6A" => --ROR A Rotateft right one bit 1st part.
|
| 422 |
|
|
reg_a(7 downto 0) <= reg_a(8 downto 1);
|
| 423 |
|
|
reg_a(8) <= reg_a(0);
|
| 424 |
|
|
dat_out2 <= reg_a(8 downto 1);
|
| 425 |
|
|
flags_fg <= "01";
|
| 426 |
|
|
cycle_ctr <= x"0";
|
| 427 |
|
|
when x"0A" => --ASL A Shift Left one bit 1st part.
|
| 428 |
|
|
reg_a <= reg_a(7 downto 0) & '0';
|
| 429 |
|
|
dat_out2 <= reg_a(6 downto 0) & '0';
|
| 430 |
|
|
flags_fg <= "01";
|
| 431 |
|
|
cycle_ctr <= x"0";
|
| 432 |
|
|
when x"4A" => --LSR A Logical Shift Right one bit 1st part.
|
| 433 |
|
|
reg_a(7 downto 0) <= '0' & reg_a(7 downto 1);
|
| 434 |
|
|
reg_a(8) <= reg_a(0);
|
| 435 |
|
|
dat_out2 <= '0' & reg_a(7 downto 1);
|
| 436 |
|
|
flags_fg <= "01";
|
| 437 |
|
|
cycle_ctr <= x"0";
|
| 438 |
|
|
when x"9A" => --TXS
|
| 439 |
|
|
reg_sp <= reg_x;
|
| 440 |
|
|
cycle_ctr <= x"0";
|
| 441 |
|
|
when x"AA" => --TAX
|
| 442 |
|
|
reg_x <= reg_a(7 downto 0);
|
| 443 |
|
|
flags_fg <= "01";
|
| 444 |
|
|
dat_out2 <= reg_a(7 downto 0);
|
| 445 |
|
|
cycle_ctr <= x"0";
|
| 446 |
|
|
when x"8A" => --TXA
|
| 447 |
|
|
reg_a(7 downto 0) <= reg_x;
|
| 448 |
|
|
flags_fg <= "01";
|
| 449 |
|
|
dat_out2 <= reg_a(7 downto 0);
|
| 450 |
|
|
cycle_ctr <= x"0";
|
| 451 |
|
|
when x"BA" => --TSX
|
| 452 |
|
|
reg_x <= reg_sp;
|
| 453 |
|
|
flags_fg <= "01";
|
| 454 |
|
|
dat_out2 <= reg_sp;
|
| 455 |
|
|
cycle_ctr <= x"0";
|
| 456 |
|
|
when x"CA" => --DEX
|
| 457 |
|
|
reg_x <= reg_X - X"01";
|
| 458 |
|
|
flags_fg <= "01";
|
| 459 |
|
|
dat_out2 <= reg_x - X"01";
|
| 460 |
|
|
cycle_ctr <= x"0";
|
| 461 |
|
|
-- =============================================================================================
|
| 462 |
|
|
when x"F0" => --BEQ branch true 1st part.
|
| 463 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 464 |
|
|
when x"D0" => --BNE branch true 1st part.
|
| 465 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 466 |
|
|
when x"10" => --BPL plus true 1st part.
|
| 467 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 468 |
|
|
when x"30" => --BM1 negative true 1st part.
|
| 469 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 470 |
|
|
when x"50" => --BVC overflow false 1st part.
|
| 471 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 472 |
|
|
when x"70" => --BVS overflow true 1st part.
|
| 473 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 474 |
|
|
when x"90" => --BCC carry false 1st part.
|
| 475 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 476 |
|
|
when x"B0" => --BCS carry true 1st part.
|
| 477 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 478 |
|
|
|
| 479 |
|
|
-- =============================================================================================
|
| 480 |
|
|
when x"A2" => --LDX #. 1st partProto imediate instruction
|
| 481 |
|
|
pc_inc_fg <= '1';
|
| 482 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 483 |
|
|
when x"A9" => --LDA #. 1st part Proto imediate instruction
|
| 484 |
|
|
pc_inc_fg <= '1';
|
| 485 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 486 |
|
|
when x"09" => --ORA #. 1st part Proto imediate instruction
|
| 487 |
|
|
pc_inc_fg <= '1';
|
| 488 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 489 |
|
|
when x"29" => --AND #. 1st part Proto imediate instruction
|
| 490 |
|
|
pc_inc_fg <= '1';
|
| 491 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 492 |
|
|
when x"49" => --EOR #. 1st part Proto imediate instruction
|
| 493 |
|
|
pc_inc_fg <= '1';
|
| 494 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 495 |
|
|
when x"69" => --ADC #. 1st part Proto imediate instruction
|
| 496 |
|
|
pc_inc_fg <= '1';
|
| 497 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 498 |
|
|
when x"A0" => --LDY #. 1st part Proto imediate instruction
|
| 499 |
|
|
pc_inc_fg <= '1';
|
| 500 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 501 |
|
|
when x"C0" => --CPY #. 1st part Proto imediate instruction
|
| 502 |
|
|
pc_inc_fg <= '1';
|
| 503 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 504 |
|
|
when x"C9" => --CMP #. 1st part Proto imediate instruction
|
| 505 |
|
|
pc_inc_fg <= '1';
|
| 506 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 507 |
|
|
when x"E0" => --CPX #. 1st part Proto imediate instruction
|
| 508 |
|
|
pc_inc_fg <= '1';
|
| 509 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 510 |
|
|
when x"E9" => --SBC #. 1st part Proto imediate instruction
|
| 511 |
|
|
pc_inc_fg <= '1';
|
| 512 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 513 |
|
|
|
| 514 |
|
|
-- =============================================================================================
|
| 515 |
|
|
when x"84" => --STY zero 1st part proto
|
| 516 |
|
|
dat_out1 <= reg_y;
|
| 517 |
|
|
wr_ctr <= "01";
|
| 518 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 519 |
|
|
when x"85" => --STA zero 1st part proto
|
| 520 |
|
|
dat_out1 <= reg_a(7 downto 0);
|
| 521 |
|
|
wr_ctr <= "01";
|
| 522 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 523 |
|
|
when x"86" => --STX zero 1st part proto
|
| 524 |
|
|
dat_out1 <= reg_x;
|
| 525 |
|
|
wr_ctr <= "01";
|
| 526 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 527 |
|
|
when x"94" => --STY zero, X 1st part proto
|
| 528 |
|
|
dat_out1 <= reg_y;
|
| 529 |
|
|
add_fg <= x"2";
|
| 530 |
|
|
wr_ctr <= "01";
|
| 531 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 532 |
|
|
when x"95" => --STA zero, X 1st part proto
|
| 533 |
|
|
dat_out1 <= reg_a(7 downto 0);
|
| 534 |
|
|
wr_ctr <= "01";
|
| 535 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 536 |
|
|
when x"96" => --STX zero, Y 1st part proto
|
| 537 |
|
|
dat_out1 <= reg_x;
|
| 538 |
|
|
wr_ctr <= "01";
|
| 539 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 540 |
|
|
|
| 541 |
|
|
-- ===============================================================================================
|
| 542 |
|
|
|
| 543 |
|
|
when x"A1" => --LDA (zero,x) 1st part proto
|
| 544 |
|
|
add_fg <= x"2";
|
| 545 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 546 |
|
|
when x"B1" => --LDA (zero),y 1st part proto
|
| 547 |
|
|
add_fg <= x"1";
|
| 548 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 549 |
|
|
|
| 550 |
|
|
when x"21" => --AND (zero,x) 1st part proto
|
| 551 |
|
|
add_fg <= x"2";
|
| 552 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 553 |
|
|
when x"31" => --AND (zero),y 1st part proto
|
| 554 |
|
|
add_fg <= x"1";
|
| 555 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 556 |
|
|
|
| 557 |
|
|
when x"41" => --EOR (zero,x) 1st part proto
|
| 558 |
|
|
add_fg <= x"2";
|
| 559 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 560 |
|
|
when x"51" => --EOR (zero),y 1st part proto
|
| 561 |
|
|
add_fg <= x"1";
|
| 562 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 563 |
|
|
|
| 564 |
|
|
when x"01" => --OR (zero,x) 1st part proto
|
| 565 |
|
|
add_fg <= x"2";
|
| 566 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 567 |
|
|
when x"11" => --OR (zero),y 1st part proto
|
| 568 |
|
|
add_fg <= x"1";
|
| 569 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 570 |
|
|
|
| 571 |
|
|
when x"61" => --ADC (zero,x) 1st part proto
|
| 572 |
|
|
add_fg <= x"2";
|
| 573 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 574 |
|
|
when x"71" => --ADC (zero),y 1st part proto
|
| 575 |
|
|
add_fg <= x"1";
|
| 576 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 577 |
|
|
|
| 578 |
|
|
when x"E1" => --SBC (zero,x) 1st part proto
|
| 579 |
|
|
add_fg <= x"2";
|
| 580 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 581 |
|
|
when x"F1" => --SBC (zero),y 1st part proto
|
| 582 |
|
|
add_fg <= x"1";
|
| 583 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 584 |
|
|
|
| 585 |
|
|
when x"C1" => --CMP (zero,x) 1st part proto
|
| 586 |
|
|
add_fg <= x"2";
|
| 587 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 588 |
|
|
when x"D1" => --CMP (zero),y 1st part proto
|
| 589 |
|
|
add_fg <= x"1";
|
| 590 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 591 |
|
|
|
| 592 |
|
|
when x"81" => --STA (zero,x) 1st part proto
|
| 593 |
|
|
add_fg <= x"2";
|
| 594 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 595 |
|
|
when x"91" => --STA (zero),y 1st part proto
|
| 596 |
|
|
add_fg <= x"1";
|
| 597 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 598 |
|
|
|
| 599 |
|
|
|
| 600 |
|
|
-- ==============================================================================================
|
| 601 |
|
|
when x"A5" => --LDA zero 1st part proto
|
| 602 |
|
|
add_fg <= x"1";
|
| 603 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 604 |
|
|
when x"A4" => --LDY zero 1st part
|
| 605 |
|
|
add_fg <= x"1";
|
| 606 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 607 |
|
|
when x"A6" => --LDX zero 1st part
|
| 608 |
|
|
add_fg <= x"1";
|
| 609 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 610 |
|
|
when x"B5" => --LDA zero,x 1st part
|
| 611 |
|
|
add_fg <= x"2";
|
| 612 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 613 |
|
|
when x"B4" => --LDY zero,x 1st part
|
| 614 |
|
|
add_fg <= x"2";
|
| 615 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 616 |
|
|
when x"B6" => --LDX zero,y 1st part
|
| 617 |
|
|
add_fg <= x"3";
|
| 618 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 619 |
|
|
when x"05" => --ORA zero 1st part
|
| 620 |
|
|
add_fg <= x"1";
|
| 621 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 622 |
|
|
when x"15" => --ORA zero,X 1st part
|
| 623 |
|
|
add_fg <= x"2";
|
| 624 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 625 |
|
|
when x"24" => --BIT zero 1st part
|
| 626 |
|
|
add_fg <= x"1";
|
| 627 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 628 |
|
|
when x"25" => --AND zero 1st part
|
| 629 |
|
|
add_fg <= x"1";
|
| 630 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 631 |
|
|
when x"26" => --ROL zero 1st part
|
| 632 |
|
|
add_fg <= x"1";
|
| 633 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 634 |
|
|
when x"35" => --AND zero,X 1st part
|
| 635 |
|
|
add_fg <= x"2";
|
| 636 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 637 |
|
|
when x"36" => --ROL zero,X 1st part
|
| 638 |
|
|
add_fg <= x"1";
|
| 639 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 640 |
|
|
when x"45" => --EOR zero 1st part
|
| 641 |
|
|
add_fg <= x"1";
|
| 642 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 643 |
|
|
when x"46" => --LSR zero 1st part
|
| 644 |
|
|
add_fg <= x"1";
|
| 645 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 646 |
|
|
when x"55" => --EOR zero,X 1st part
|
| 647 |
|
|
add_fg <= x"2";
|
| 648 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 649 |
|
|
-- =========================================================================================
|
| 650 |
|
|
when x"E6" => --INC zero 1st part
|
| 651 |
|
|
add_fg <= x"1";
|
| 652 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 653 |
|
|
when x"56" => --LSR zero,X 1st part
|
| 654 |
|
|
add_fg <= x"2";
|
| 655 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 656 |
|
|
when x"65" => --ADC zero 1st part
|
| 657 |
|
|
add_fg <= x"1";
|
| 658 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 659 |
|
|
when x"66" => --ROR zero 1st part
|
| 660 |
|
|
add_fg <= x"1";
|
| 661 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 662 |
|
|
when x"75" => --ADC zero,X 1st part
|
| 663 |
|
|
add_fg <= x"2";
|
| 664 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 665 |
|
|
when x"76" => --ROR zero,X 1st part
|
| 666 |
|
|
add_fg <= x"2";
|
| 667 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 668 |
|
|
when x"C4" => --CPY zero 1st part
|
| 669 |
|
|
add_fg <= x"1";
|
| 670 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 671 |
|
|
when x"C5" => --CMP zero 1st part
|
| 672 |
|
|
add_fg <= x"1";
|
| 673 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 674 |
|
|
when x"C6" => --DEC zero 1st part
|
| 675 |
|
|
add_fg <= x"1";
|
| 676 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 677 |
|
|
when x"D5" => --CMP zero,X 1st part
|
| 678 |
|
|
add_fg <= x"2";
|
| 679 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 680 |
|
|
when x"D6" => --DEC zero,X 1st part
|
| 681 |
|
|
add_fg <= x"2";
|
| 682 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 683 |
|
|
when x"E4" => --CPX zero 1st part
|
| 684 |
|
|
add_fg <= x"1";
|
| 685 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 686 |
|
|
when x"E5" => --SBC zero 1st part
|
| 687 |
|
|
add_fg <= x"1";
|
| 688 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 689 |
|
|
when x"F5" => --SBC zero,X 1st part
|
| 690 |
|
|
add_fg <= x"2";
|
| 691 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 692 |
|
|
when x"F6" => --INC zero,X 1st part
|
| 693 |
|
|
add_fg <= x"2";
|
| 694 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 695 |
|
|
when x"06" => --ASL zero, 1st part
|
| 696 |
|
|
add_fg <= x"1";
|
| 697 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 698 |
|
|
when x"16" => --ASL zero, x 1st part
|
| 699 |
|
|
add_fg <= x"2";
|
| 700 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 701 |
|
|
-- ==============================================================================
|
| 702 |
|
|
when x"AD" => --LDA abs 1st part.
|
| 703 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 704 |
|
|
when x"BD" => --LDA, x abs 1st part.
|
| 705 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 706 |
|
|
when x"B9" => --LDA, Y abs 1st part
|
| 707 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 708 |
|
|
|
| 709 |
|
|
when x"2D" => --AND abs 1st part.
|
| 710 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 711 |
|
|
when x"3D" => --AND, x abs 1st part.
|
| 712 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 713 |
|
|
when x"39" => --AND, Y abs 1st part.
|
| 714 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 715 |
|
|
|
| 716 |
|
|
when x"0D" => --ORA abs 1st part.
|
| 717 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 718 |
|
|
when x"1D" => --ORA, x abs 1st part.
|
| 719 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 720 |
|
|
|
| 721 |
|
|
when x"19" => --ORA, Y abs 1st part.
|
| 722 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 723 |
|
|
|
| 724 |
|
|
when x"4D" => --EOR abs 1st part.
|
| 725 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 726 |
|
|
when x"5D" => --EOR, x abs 1st part.
|
| 727 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 728 |
|
|
when x"59" => --EOR, Y abs 1st part.
|
| 729 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 730 |
|
|
|
| 731 |
|
|
when x"6D" => --ADC abs 1st part.
|
| 732 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 733 |
|
|
when x"7D" => --ADC, x abs 1st part.
|
| 734 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 735 |
|
|
when x"79" => --ADC, Y abs 1st part.
|
| 736 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 737 |
|
|
|
| 738 |
|
|
when x"ED" => --SBC abs 1st part.
|
| 739 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 740 |
|
|
when x"FD" => --SBC, x abs 1st part.
|
| 741 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 742 |
|
|
when x"F9" => --SBC, Y abs 1st part.
|
| 743 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 744 |
|
|
|
| 745 |
|
|
when x"AE" => --LDX abs 1st part.
|
| 746 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 747 |
|
|
when x"BE" => --LDX, y abs 1st part.
|
| 748 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 749 |
|
|
when x"AC" => --LDY abs 1st part.
|
| 750 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 751 |
|
|
when x"BC" => --LDY, x abs 1st part.
|
| 752 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 753 |
|
|
when x"2C" => --BIT abs 1st part.
|
| 754 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 755 |
|
|
|
| 756 |
|
|
when x"CD" => --CMP abs 1st part.
|
| 757 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 758 |
|
|
when x"DD" => --CMP, x abs 1st part.
|
| 759 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 760 |
|
|
when x"D9" => --CMP, Y abs 1st part.
|
| 761 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 762 |
|
|
when x"EC" => --CPX abs 1st part.
|
| 763 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 764 |
|
|
when x"CC" => --CPY abs 1st part.
|
| 765 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 766 |
|
|
--.........................................................................................
|
| 767 |
|
|
when x"8D" => --STA abs 1st part.
|
| 768 |
|
|
dat_out1 <= reg_a(7 downto 0);
|
| 769 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 770 |
|
|
when x"9D" => --STA,x abs 1st part.
|
| 771 |
|
|
dat_out1 <= reg_a(7 downto 0);
|
| 772 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 773 |
|
|
when x"99" => --STA, y abs 1st part.
|
| 774 |
|
|
dat_out1 <= reg_a(7 downto 0);
|
| 775 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 776 |
|
|
when x"8E" => --STX abs 1st part.
|
| 777 |
|
|
dat_out1 <= reg_x;
|
| 778 |
|
|
cycle_ctr <= cycle_ctr + x"1";--
|
| 779 |
|
|
when x"8C" => --STY abs 1st part.
|
| 780 |
|
|
dat_out1 <= reg_y;
|
| 781 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 782 |
|
|
--.........................................................................................
|
| 783 |
|
|
|
| 784 |
|
|
when x"EE" => --INC abs 1st part.
|
| 785 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 786 |
|
|
when x"FE" => --INC, x abs 1st part.
|
| 787 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 788 |
|
|
when x"CE" => --DEC abs 1st part.
|
| 789 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 790 |
|
|
when x"DE" => --DEC, x abs 1st part.
|
| 791 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 792 |
|
|
when x"2E" => --ROL abs 1st part.
|
| 793 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 794 |
|
|
when x"3E" => --ROL, x abs 1st part.
|
| 795 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 796 |
|
|
when x"6E" => --ROR abs 1st part.
|
| 797 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 798 |
|
|
when x"7E" => --ROR, x abs 1st part.
|
| 799 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 800 |
|
|
when x"4E" => --LSR abs 1st part.
|
| 801 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 802 |
|
|
when x"5E" => --LSR, x abs 1st part.
|
| 803 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 804 |
|
|
when x"0E" => --ASL abs 1st part.
|
| 805 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 806 |
|
|
when x"1E" => --ASL, x abs 1st part.
|
| 807 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 808 |
|
|
-- ............................................................................
|
| 809 |
|
|
-- ==============================================================================
|
| 810 |
|
|
|
| 811 |
|
|
|
| 812 |
|
|
when x"4C" => --JMP abs first part
|
| 813 |
|
|
pc_inc_fg <= '1';
|
| 814 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 815 |
|
|
when x"6C" => --JMP indirect first part
|
| 816 |
|
|
pc_inc_fg <= '1';
|
| 817 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 818 |
|
|
when x"20" => --JSR abs first part
|
| 819 |
|
|
pc_inc_fg <= '1';
|
| 820 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 821 |
|
|
when x"60" => --RTS first part
|
| 822 |
|
|
reg_sp <= reg_sp - "1";
|
| 823 |
|
|
add_fg <= x"7";
|
| 824 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 825 |
|
|
when x"40" => --RTI 1st part pull old status from stack
|
| 826 |
|
|
reg_sp <= reg_sp - "1";
|
| 827 |
|
|
add_fg <= x"7";
|
| 828 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 829 |
|
|
|
| 830 |
|
|
when x"00" => --Break first part cyc 0
|
| 831 |
|
|
if irq_fg = '0' then --Start up, irq and nmi also use
|
| 832 |
|
|
b_fg <= '1'; --this set of logic.
|
| 833 |
|
|
else
|
| 834 |
|
|
b_fg <= '0';
|
| 835 |
|
|
end if;
|
| 836 |
|
|
pc_dec_fg <= '1';
|
| 837 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 838 |
|
|
|
| 839 |
|
|
when others =>
|
| 840 |
|
|
cycle_ctr <= x"0";
|
| 841 |
|
|
|
| 842 |
|
|
end case; --Cycle 0
|
| 843 |
|
|
end if; --Initiated by nmi irq detection.
|
| 844 |
|
|
|
| 845 |
|
|
|
| 846 |
|
|
-- End cycle 0 =========================================================
|
| 847 |
|
|
|
| 848 |
|
|
|
| 849 |
|
|
when x"1" =>
|
| 850 |
|
|
-- cycle_mark <= '0';
|
| 851 |
|
|
|
| 852 |
|
|
case Instruction_in is
|
| 853 |
|
|
-- ================================================================================================
|
| 854 |
|
|
|
| 855 |
|
|
when x"48" => --PHA 2nd part accumulator onto stack
|
| 856 |
|
|
pc_dec_fg <= '0';
|
| 857 |
|
|
add_fg <= x"7";
|
| 858 |
|
|
wr_ctr <= "00";
|
| 859 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 860 |
|
|
when x"08" => --PHP 2nd part Status reg onto stack
|
| 861 |
|
|
pc_dec_fg <= '0';
|
| 862 |
|
|
add_fg <= x"7";
|
| 863 |
|
|
wr_ctr <= "00";
|
| 864 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 865 |
|
|
|
| 866 |
|
|
when x"68" => --PLA 2nd part Pull Accumulator from Stack
|
| 867 |
|
|
add_fg <= x"7";
|
| 868 |
|
|
pc_dec_fg <= '0';
|
| 869 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 870 |
|
|
when x"28" => --PLP 2nd part Pull Status from Stack
|
| 871 |
|
|
add_fg <= x"7";
|
| 872 |
|
|
pc_dec_fg <= '0';
|
| 873 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 874 |
|
|
|
| 875 |
|
|
when x"F0" => --BEQ branch true 2nd part.
|
| 876 |
|
|
if z_fg = '1' then --Should work like a nop
|
| 877 |
|
|
branch_fg <= '1'; --branch true 1st part.
|
| 878 |
|
|
else
|
| 879 |
|
|
pc_inc_fg <= '1';
|
| 880 |
|
|
end if;
|
| 881 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 882 |
|
|
when x"D0" => --BNE branch true 2nd part.
|
| 883 |
|
|
if z_fg = '0' then --Should work like a nop
|
| 884 |
|
|
branch_fg <= '1'; --branch true 1st part.
|
| 885 |
|
|
else
|
| 886 |
|
|
pc_inc_fg <= '1';
|
| 887 |
|
|
end if;
|
| 888 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 889 |
|
|
when x"10" => --BPL plus true 2nd part.
|
| 890 |
|
|
if n_fg = '0' then --Should work like a nop
|
| 891 |
|
|
branch_fg <= '1'; --branch true 1st part.
|
| 892 |
|
|
else
|
| 893 |
|
|
pc_inc_fg <= '1';
|
| 894 |
|
|
end if;
|
| 895 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 896 |
|
|
when x"30" => --BM1 negative true 2nd part.
|
| 897 |
|
|
if n_fg = '1' then --Should work like a nop
|
| 898 |
|
|
branch_fg <= '1'; --branch true 1st part.
|
| 899 |
|
|
else
|
| 900 |
|
|
pc_inc_fg <= '1';
|
| 901 |
|
|
end if;
|
| 902 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 903 |
|
|
when x"50" => --BVC overflow false 2nd part.
|
| 904 |
|
|
if v_fg = '0' then --Should work like a nop
|
| 905 |
|
|
branch_fg <= '1'; --branch true 1st part.
|
| 906 |
|
|
else
|
| 907 |
|
|
pc_inc_fg <= '1';
|
| 908 |
|
|
end if;
|
| 909 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 910 |
|
|
when x"70" => --BVS overflow true 2nd part.
|
| 911 |
|
|
if v_fg = '1' then --Should work like a nop
|
| 912 |
|
|
branch_fg <= '1'; --branch true 1st part.
|
| 913 |
|
|
else
|
| 914 |
|
|
pc_inc_fg <= '1';
|
| 915 |
|
|
end if;
|
| 916 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 917 |
|
|
when x"90" => --BCC carry false 2nd part.
|
| 918 |
|
|
if reg_a(8) = '0' then --Should work like a nop
|
| 919 |
|
|
branch_fg <= '1'; --branch true 1st part.
|
| 920 |
|
|
else
|
| 921 |
|
|
pc_inc_fg <= '1';
|
| 922 |
|
|
end if;
|
| 923 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 924 |
|
|
when x"B0" => --BCS carry true 2nd part.
|
| 925 |
|
|
if reg_a(8) = '1' then --Should work like a nop
|
| 926 |
|
|
branch_fg <= '1'; --branch true 1st part.
|
| 927 |
|
|
else
|
| 928 |
|
|
pc_inc_fg <= '1';
|
| 929 |
|
|
end if;
|
| 930 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 931 |
|
|
-- ================================================================================================
|
| 932 |
|
|
|
| 933 |
|
|
when x"A2" => --LDX #. 2nd part Proto imediate instruction
|
| 934 |
|
|
pc_inc_fg <= '0';
|
| 935 |
|
|
reg_x <= data_rd;
|
| 936 |
|
|
-- flags_fg <= "01";
|
| 937 |
|
|
dat_out2 <= data_rd;
|
| 938 |
|
|
cycle_ctr <= x"0";
|
| 939 |
|
|
when x"A9" => --LDA #. 2nd part Proto imediate instruction
|
| 940 |
|
|
pc_inc_fg <= '0';
|
| 941 |
|
|
-- add_fg <= x"0";
|
| 942 |
|
|
flags_fg <= "01";
|
| 943 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 944 |
|
|
dat_out2 <= data_rd;
|
| 945 |
|
|
cycle_ctr <= x"0";
|
| 946 |
|
|
when x"A0" => --LDY #
|
| 947 |
|
|
pc_inc_fg <= '0';
|
| 948 |
|
|
-- add_fg <= x"0";
|
| 949 |
|
|
flags_fg <= "01";
|
| 950 |
|
|
reg_y <= data_rd;
|
| 951 |
|
|
dat_out2 <= data_rd;
|
| 952 |
|
|
cycle_ctr <= x"0";
|
| 953 |
|
|
when x"09" => --ORA #
|
| 954 |
|
|
pc_inc_fg <= '0';
|
| 955 |
|
|
add_fg <= x"0";
|
| 956 |
|
|
-- flags_fg <= "01";
|
| 957 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd;
|
| 958 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 959 |
|
|
cycle_ctr <= x"0";
|
| 960 |
|
|
when x"29" => --AND # 2nd part
|
| 961 |
|
|
pc_inc_fg <= '0';
|
| 962 |
|
|
-- add_fg <= x"0";
|
| 963 |
|
|
flags_fg <= "01";
|
| 964 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd;
|
| 965 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 966 |
|
|
cycle_ctr <= x"0";
|
| 967 |
|
|
when x"49" => --EOR #
|
| 968 |
|
|
pc_inc_fg <= '0';
|
| 969 |
|
|
-- add_fg <= x"0";
|
| 970 |
|
|
flags_fg <= "01";
|
| 971 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd;
|
| 972 |
|
|
dat_out2 <= reg_a(7 downto 0) xor data_rd;
|
| 973 |
|
|
cycle_ctr <= x"0";
|
| 974 |
|
|
when x"69" => --ADC #
|
| 975 |
|
|
pc_inc_fg <= '0';
|
| 976 |
|
|
v_ff <= not reg_a(7) and not data_rd(7); --Pos+Pos=Overflow possible
|
| 977 |
|
|
flags_fg <= "10";
|
| 978 |
|
|
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8));
|
| 979 |
|
|
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8));
|
| 980 |
|
|
cycle_ctr <= x"0";
|
| 981 |
|
|
when x"E9" => --SBC # 2nd part
|
| 982 |
|
|
pc_inc_fg <= '0';
|
| 983 |
|
|
v_ff <= reg_a(7) and data_rd(7); --Neg-Neg=Underflow possible
|
| 984 |
|
|
flags_fg <= "10";
|
| 985 |
|
|
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8));
|
| 986 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8));
|
| 987 |
|
|
cycle_ctr <= x"0";
|
| 988 |
|
|
|
| 989 |
|
|
when x"C9" => --CMP # 2nd part.
|
| 990 |
|
|
pc_inc_fg <= '0';
|
| 991 |
|
|
flags_fg <= "01";
|
| 992 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd;
|
| 993 |
|
|
if reg_a(7 downto 0) > data_rd then
|
| 994 |
|
|
reg_a(8) <= '1';
|
| 995 |
|
|
else
|
| 996 |
|
|
reg_a(8) <= '0';
|
| 997 |
|
|
end if;
|
| 998 |
|
|
cycle_ctr <= x"0";
|
| 999 |
|
|
when x"E0" => --CPX #.
|
| 1000 |
|
|
pc_inc_fg <= '0';
|
| 1001 |
|
|
flags_fg <= "01";
|
| 1002 |
|
|
dat_out2 <= reg_x - data_rd;
|
| 1003 |
|
|
if reg_x > data_rd then
|
| 1004 |
|
|
reg_a(8) <= '1';
|
| 1005 |
|
|
else
|
| 1006 |
|
|
reg_a(8) <= '0';
|
| 1007 |
|
|
end if;
|
| 1008 |
|
|
cycle_ctr <= x"0";
|
| 1009 |
|
|
when x"C0" => --CPY #.
|
| 1010 |
|
|
pc_inc_fg <= '0';
|
| 1011 |
|
|
flags_fg <= "01";
|
| 1012 |
|
|
dat_out2 <= reg_y - data_rd;
|
| 1013 |
|
|
if reg_y > data_rd then
|
| 1014 |
|
|
reg_a(8) <= '1';
|
| 1015 |
|
|
else
|
| 1016 |
|
|
reg_a(8) <= '0';
|
| 1017 |
|
|
end if;
|
| 1018 |
|
|
cycle_ctr <= x"0";
|
| 1019 |
|
|
|
| 1020 |
|
|
-- ===================================================================================================
|
| 1021 |
|
|
when x"84" => --STY zero 2nd part proto
|
| 1022 |
|
|
add_fg <= x"1";
|
| 1023 |
|
|
wr_ctr <= "00";
|
| 1024 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1025 |
|
|
when x"85" => --STA zero 2nd part proto
|
| 1026 |
|
|
add_fg <= x"1";
|
| 1027 |
|
|
wr_ctr <= "00";
|
| 1028 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1029 |
|
|
when x"86" => --STX zero 2nd part proto
|
| 1030 |
|
|
add_fg <= x"1";
|
| 1031 |
|
|
wr_ctr <= "00";
|
| 1032 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1033 |
|
|
when x"94" => --STY zero, X 2nd part proto
|
| 1034 |
|
|
add_fg <= x"2";
|
| 1035 |
|
|
wr_ctr <= "00";
|
| 1036 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1037 |
|
|
when x"95" => --STA zero, X 2nd part proto
|
| 1038 |
|
|
add_fg <= x"2";
|
| 1039 |
|
|
wr_ctr <= "00";
|
| 1040 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1041 |
|
|
when x"96" => --STX zero, Y 2nd part proto
|
| 1042 |
|
|
add_fg <= x"3";
|
| 1043 |
|
|
wr_ctr <= "00";
|
| 1044 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1045 |
|
|
|
| 1046 |
|
|
-- =================================================================================
|
| 1047 |
|
|
when x"A5" => --LDA zero 2nd part proto
|
| 1048 |
|
|
pc_inc_fg <= '1';
|
| 1049 |
|
|
add_fg <= x"0";
|
| 1050 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1051 |
|
|
when x"A4" => --LDY zero 2nd part
|
| 1052 |
|
|
pc_inc_fg <= '1';
|
| 1053 |
|
|
add_fg <= x"0";
|
| 1054 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1055 |
|
|
when x"A6" => --LDX zero 2nd part
|
| 1056 |
|
|
pc_inc_fg <= '1';
|
| 1057 |
|
|
add_fg <= x"0";
|
| 1058 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1059 |
|
|
when x"B5" => --LDA zero,X 2nd part
|
| 1060 |
|
|
pc_inc_fg <= '1';
|
| 1061 |
|
|
add_fg <= x"0";
|
| 1062 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1063 |
|
|
when x"B4" => --LDY zero,X 2nd part
|
| 1064 |
|
|
pc_inc_fg <= '1';
|
| 1065 |
|
|
add_fg <= x"0";
|
| 1066 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1067 |
|
|
|
| 1068 |
|
|
when x"B6" => --LDX zero,Y 2nd part
|
| 1069 |
|
|
pc_inc_fg <= '1';
|
| 1070 |
|
|
add_fg <= x"0";
|
| 1071 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1072 |
|
|
when x"05" => --ORA zero 2nd part
|
| 1073 |
|
|
pc_inc_fg <= '1';
|
| 1074 |
|
|
add_fg <= x"0";
|
| 1075 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1076 |
|
|
|
| 1077 |
|
|
when x"15" => --ORA zero,X 2nd part
|
| 1078 |
|
|
pc_inc_fg <= '1';
|
| 1079 |
|
|
add_fg <= x"0";
|
| 1080 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1081 |
|
|
when x"24" => --BIT zero 2nd part
|
| 1082 |
|
|
pc_inc_fg <= '1';
|
| 1083 |
|
|
add_fg <= x"0";
|
| 1084 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1085 |
|
|
|
| 1086 |
|
|
when x"25" => --AND zero 2nd part
|
| 1087 |
|
|
pc_inc_fg <= '1';
|
| 1088 |
|
|
add_fg <= x"0";
|
| 1089 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1090 |
|
|
|
| 1091 |
|
|
when x"35" => --AND zero,X 2nd part
|
| 1092 |
|
|
pc_inc_fg <= '1';
|
| 1093 |
|
|
add_fg <= x"0";
|
| 1094 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1095 |
|
|
|
| 1096 |
|
|
when x"45" => --EOR zero,Y 2nd part
|
| 1097 |
|
|
pc_inc_fg <= '1';
|
| 1098 |
|
|
add_fg <= x"0";
|
| 1099 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1100 |
|
|
|
| 1101 |
|
|
when x"55" => --EOR zero,X 2nd part
|
| 1102 |
|
|
pc_inc_fg <= '1';
|
| 1103 |
|
|
add_fg <= x"0";
|
| 1104 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1105 |
|
|
|
| 1106 |
|
|
when x"65" => --ADC zero 2nd part
|
| 1107 |
|
|
pc_inc_fg <= '1';
|
| 1108 |
|
|
add_fg <= x"0";
|
| 1109 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1110 |
|
|
|
| 1111 |
|
|
when x"75" => --ADC zero,X 2nd part
|
| 1112 |
|
|
pc_inc_fg <= '1';
|
| 1113 |
|
|
add_fg <= x"0";
|
| 1114 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1115 |
|
|
|
| 1116 |
|
|
when x"C4" => --CPY zero 2nd part
|
| 1117 |
|
|
pc_inc_fg <= '1';
|
| 1118 |
|
|
add_fg <= x"0";
|
| 1119 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1120 |
|
|
|
| 1121 |
|
|
when x"C5" => --CMP zero 2nd part
|
| 1122 |
|
|
pc_inc_fg <= '1';
|
| 1123 |
|
|
add_fg <= x"f";
|
| 1124 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1125 |
|
|
when x"C6" => --DEC zero 2nd part
|
| 1126 |
|
|
add_fg <= x"f";
|
| 1127 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1128 |
|
|
when x"D5" => --CMP zero,X 2nd part
|
| 1129 |
|
|
pc_inc_fg <= '1';
|
| 1130 |
|
|
add_fg <= x"0";
|
| 1131 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1132 |
|
|
when x"D6" => --DEC zero,X 2nd part
|
| 1133 |
|
|
pc_inc_fg <= '1';
|
| 1134 |
|
|
add_fg <= x"0";
|
| 1135 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1136 |
|
|
|
| 1137 |
|
|
when x"E4" => --CPX zero 2nd part
|
| 1138 |
|
|
pc_inc_fg <= '1';
|
| 1139 |
|
|
add_fg <= x"0";
|
| 1140 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1141 |
|
|
when x"E5" => --SBC zero 2nd part
|
| 1142 |
|
|
pc_inc_fg <= '1';
|
| 1143 |
|
|
add_fg <= x"0";
|
| 1144 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1145 |
|
|
when x"F5" => --SBC zero,X 2nd part
|
| 1146 |
|
|
pc_inc_fg <= '1';
|
| 1147 |
|
|
add_fg <= x"0";
|
| 1148 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1149 |
|
|
-- ===================================================================================
|
| 1150 |
|
|
when x"E6" => --INC zero 2nd part
|
| 1151 |
|
|
add_fg <= x"f";
|
| 1152 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1153 |
|
|
when x"F6" => --INC zero,X 2nd part
|
| 1154 |
|
|
add_fg <= x"f";
|
| 1155 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1156 |
|
|
when x"46" => --LSR zero 2nd part
|
| 1157 |
|
|
add_fg <= x"f";
|
| 1158 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1159 |
|
|
when x"56" => --LSR zero,X 2nd part
|
| 1160 |
|
|
add_fg <= x"f";
|
| 1161 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1162 |
|
|
|
| 1163 |
|
|
when x"66" => --ROR zero 2nd part
|
| 1164 |
|
|
add_fg <= x"f";
|
| 1165 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1166 |
|
|
when x"76" => --ROR zero,X 2nd part
|
| 1167 |
|
|
add_fg <= x"f";
|
| 1168 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1169 |
|
|
when x"26" => --ROL zero 2nd part
|
| 1170 |
|
|
add_fg <= x"f";
|
| 1171 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1172 |
|
|
when x"36" => --ROL zero,X 2nd part
|
| 1173 |
|
|
add_fg <= x"f";
|
| 1174 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1175 |
|
|
when x"06" => --ASL zero 2nd part
|
| 1176 |
|
|
add_fg <= x"f";
|
| 1177 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1178 |
|
|
when x"16" => --ASL zero,X 2nd part
|
| 1179 |
|
|
add_fg <= x"f";
|
| 1180 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1181 |
|
|
|
| 1182 |
|
|
|
| 1183 |
|
|
-- ==============================================================================
|
| 1184 |
|
|
when x"A1" => --LDA (zero,x) 2nd part proto
|
| 1185 |
|
|
add_fg <= x"D";
|
| 1186 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1187 |
|
|
when x"B1" => --LDA (zero),y 2nd part proto
|
| 1188 |
|
|
add_fg <= x"C";
|
| 1189 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1190 |
|
|
|
| 1191 |
|
|
when x"21" => --AND (zero,x) 2nd part proto
|
| 1192 |
|
|
add_fg <= x"D";
|
| 1193 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1194 |
|
|
when x"31" => --AND (zero),y 2nd part proto
|
| 1195 |
|
|
add_fg <= x"C";
|
| 1196 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1197 |
|
|
|
| 1198 |
|
|
when x"41" => --EOR (zero,x) 2nd part proto
|
| 1199 |
|
|
add_fg <= x"D";
|
| 1200 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1201 |
|
|
when x"51" => --EOR (zero),y 2nd part proto
|
| 1202 |
|
|
add_fg <= x"C";
|
| 1203 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1204 |
|
|
|
| 1205 |
|
|
when x"01" => --OR (zero,x) 2nd part proto
|
| 1206 |
|
|
add_fg <= x"D";
|
| 1207 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1208 |
|
|
when x"11" => --OR (zero),y 2nd part proto
|
| 1209 |
|
|
add_fg <= x"C";
|
| 1210 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1211 |
|
|
|
| 1212 |
|
|
when x"61" => --ADC (zero,x) 2nd part proto
|
| 1213 |
|
|
add_fg <= x"D";
|
| 1214 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1215 |
|
|
when x"71" => --ADC (zero),y 2nd part proto
|
| 1216 |
|
|
add_fg <= x"C";
|
| 1217 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1218 |
|
|
|
| 1219 |
|
|
when x"E1" => --SBC (zero,x) 2nd part proto
|
| 1220 |
|
|
add_fg <= x"D";
|
| 1221 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1222 |
|
|
when x"F1" => --SBC (zero),y 2nd part proto
|
| 1223 |
|
|
add_fg <= x"C";
|
| 1224 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1225 |
|
|
|
| 1226 |
|
|
when x"C1" => --CMP (zero,x) 2nd part proto
|
| 1227 |
|
|
add_fg <= x"D";
|
| 1228 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1229 |
|
|
when x"D1" => --CMP (zero),y 2nd part proto
|
| 1230 |
|
|
add_fg <= x"C";
|
| 1231 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1232 |
|
|
|
| 1233 |
|
|
when x"81" => --STA (zero,x) 2nd part proto
|
| 1234 |
|
|
add_fg <= x"D";
|
| 1235 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1236 |
|
|
when x"91" => --STA (zero),y 2nd part proto
|
| 1237 |
|
|
add_fg <= x"C";
|
| 1238 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1239 |
|
|
-- ==============================================================================
|
| 1240 |
|
|
when x"AD" => --LDA abs 2nd part.
|
| 1241 |
|
|
add_fg <= x"4";
|
| 1242 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1243 |
|
|
when x"BD" => --LDA, x abs 2nd part.
|
| 1244 |
|
|
add_fg <= x"5";
|
| 1245 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1246 |
|
|
when x"B9" => --LDA, Y abs 2nd part.
|
| 1247 |
|
|
add_fg <= x"6";
|
| 1248 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1249 |
|
|
|
| 1250 |
|
|
when x"2D" => --AND abs 2nd part.
|
| 1251 |
|
|
add_fg <= x"4";
|
| 1252 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1253 |
|
|
|
| 1254 |
|
|
when x"3D" => --AND, x abs 2nd part.
|
| 1255 |
|
|
add_fg <= x"5";
|
| 1256 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1257 |
|
|
when x"39" => --AND, Y abs 2nd part.
|
| 1258 |
|
|
add_fg <= x"6";
|
| 1259 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1260 |
|
|
|
| 1261 |
|
|
when x"0D" => --ORA abs 2nd part.
|
| 1262 |
|
|
add_fg <= x"4";
|
| 1263 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1264 |
|
|
when x"1D" => --ORA, x abs 2nd part.
|
| 1265 |
|
|
add_fg <= x"5";
|
| 1266 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1267 |
|
|
when x"19" => --ORA, Y abs 2nd part.
|
| 1268 |
|
|
add_fg <= x"6";
|
| 1269 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1270 |
|
|
|
| 1271 |
|
|
when x"4D" => --EOR abs 2nd part.
|
| 1272 |
|
|
add_fg <= x"4";
|
| 1273 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1274 |
|
|
when x"5D" => --EOR, x abs 2nd part.
|
| 1275 |
|
|
add_fg <= x"5";
|
| 1276 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1277 |
|
|
when x"59" => --EOR, Y abs 2nd part.
|
| 1278 |
|
|
add_fg <= x"6";
|
| 1279 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1280 |
|
|
|
| 1281 |
|
|
when x"6D" => --ADC abs 2nd part.
|
| 1282 |
|
|
add_fg <= x"4";
|
| 1283 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1284 |
|
|
when x"7D" => --ADC, x abs 2nd part.
|
| 1285 |
|
|
add_fg <= x"5";
|
| 1286 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1287 |
|
|
when x"79" => --ADC, Y abs 2nd part.
|
| 1288 |
|
|
add_fg <= x"6";
|
| 1289 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1290 |
|
|
|
| 1291 |
|
|
when x"ED" => --SBC abs 2nd part.
|
| 1292 |
|
|
add_fg <= x"4";
|
| 1293 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1294 |
|
|
when x"FD" => --SBC, x abs 2nd part.
|
| 1295 |
|
|
add_fg <= x"5";
|
| 1296 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1297 |
|
|
when x"F9" => --SBC, Y abs 2nd part.
|
| 1298 |
|
|
add_fg <= x"6";
|
| 1299 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1300 |
|
|
|
| 1301 |
|
|
when x"AE" => --LDX abs 2nd part.
|
| 1302 |
|
|
add_fg <= x"4";
|
| 1303 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1304 |
|
|
when x"BE" => --LDX, y abs 2nd part.
|
| 1305 |
|
|
add_fg <= x"6";
|
| 1306 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1307 |
|
|
when x"AC" => --LDY abs 2nd part.
|
| 1308 |
|
|
add_fg <= x"4";
|
| 1309 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1310 |
|
|
when x"BC" => --LDY, x abs 2nd part.
|
| 1311 |
|
|
add_fg <= x"5";
|
| 1312 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1313 |
|
|
|
| 1314 |
|
|
when x"2C" => --BIT abs 2nd part.
|
| 1315 |
|
|
add_fg <= x"4";
|
| 1316 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1317 |
|
|
|
| 1318 |
|
|
when x"CD" => --CMP abs 2nd part.
|
| 1319 |
|
|
add_fg <= x"4";
|
| 1320 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1321 |
|
|
when x"DD" => --CMP, x abs 2nd part.
|
| 1322 |
|
|
add_fg <= x"5";
|
| 1323 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1324 |
|
|
when x"D9" => --CMP, Y abs 2nd part.
|
| 1325 |
|
|
add_fg <= x"6";
|
| 1326 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1327 |
|
|
when x"EC" => --CPX abs 2nd part.
|
| 1328 |
|
|
add_fg <= x"4";
|
| 1329 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1330 |
|
|
when x"CC" => --CPY abs 2nd part.
|
| 1331 |
|
|
add_fg <= x"4";
|
| 1332 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1333 |
|
|
-- ...............................................................................
|
| 1334 |
|
|
when x"8D" => --STA abs 2nd part.
|
| 1335 |
|
|
wr_ctr <= "01";
|
| 1336 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1337 |
|
|
when x"9D" => --STA,x abs 2nd part.
|
| 1338 |
|
|
wr_ctr <= "01";
|
| 1339 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1340 |
|
|
when x"99" => --STA, y abs 2nd part.
|
| 1341 |
|
|
wr_ctr <= "01";
|
| 1342 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1343 |
|
|
when x"8E" => --STX abs 2nd part.
|
| 1344 |
|
|
wr_ctr <= "01";
|
| 1345 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1346 |
|
|
when x"8C" => --STY abs 2nd part.
|
| 1347 |
|
|
wr_ctr <= "01";
|
| 1348 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1349 |
|
|
-- ........................................................................
|
| 1350 |
|
|
|
| 1351 |
|
|
when x"EE" => --INC abs 2nd part.
|
| 1352 |
|
|
add_fg <= x"4";
|
| 1353 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1354 |
|
|
when x"FE" => --INC, x abs 2nd part.
|
| 1355 |
|
|
add_fg <= x"5";
|
| 1356 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1357 |
|
|
when x"CE" => --DEC abs 2nd part.
|
| 1358 |
|
|
add_fg <= x"4";
|
| 1359 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1360 |
|
|
when x"DE" => --DEC, x abs 2nd part.
|
| 1361 |
|
|
add_fg <= x"4";
|
| 1362 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1363 |
|
|
when x"2E" => --ROL abs 2nd part.
|
| 1364 |
|
|
add_fg <= x"4";
|
| 1365 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1366 |
|
|
when x"3E" => --ROL, x abs 2nd part.
|
| 1367 |
|
|
add_fg <= x"5";
|
| 1368 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1369 |
|
|
when x"6E" => --ROR abs 2nd part.
|
| 1370 |
|
|
add_fg <= x"4";
|
| 1371 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1372 |
|
|
when x"7E" => --ROR, x abs 2nd part.
|
| 1373 |
|
|
add_fg <= x"5";
|
| 1374 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1375 |
|
|
when x"4E" => --LSR abs 2nd part.
|
| 1376 |
|
|
add_fg <= x"4";
|
| 1377 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1378 |
|
|
when x"5E" => --LSR, x abs 2nd part.
|
| 1379 |
|
|
add_fg <= x"5";
|
| 1380 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1381 |
|
|
when x"0E" => --ASL abs 2nd part.
|
| 1382 |
|
|
add_fg <= x"4";
|
| 1383 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1384 |
|
|
when x"1E" => --ASL, x abs 2nd part.
|
| 1385 |
|
|
add_fg <= x"5";
|
| 1386 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1387 |
|
|
-- ............................................................................
|
| 1388 |
|
|
-- ==============================================================================
|
| 1389 |
|
|
when x"4C" => --JMP abs 2nd part
|
| 1390 |
|
|
pc_inc_fg <= '0';
|
| 1391 |
|
|
dat2pc_fg <= '1';
|
| 1392 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1393 |
|
|
when x"6C" => --JMP indirect 2nd part
|
| 1394 |
|
|
add_fg <= x"4";
|
| 1395 |
|
|
pc_inc_fg <= '0';
|
| 1396 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1397 |
|
|
when x"20" => --JSR abs 2nd part
|
| 1398 |
|
|
dat2pc_fg <= '1';
|
| 1399 |
|
|
pc_inc_fg <= '0';
|
| 1400 |
|
|
wr_ctr <= "10";
|
| 1401 |
|
|
-- add_fg <= x"7";
|
| 1402 |
|
|
dat_out1 <= reg_pc(7 downto 0);
|
| 1403 |
|
|
dat_out2 <= reg_pc(15 downto 8);
|
| 1404 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1405 |
|
|
|
| 1406 |
|
|
when x"60" => --RTS second part
|
| 1407 |
|
|
reg_sp <= reg_sp - "1";
|
| 1408 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1409 |
|
|
when x"40" => --RTI second part pull old status from stack
|
| 1410 |
|
|
reg_sp <= reg_sp - "1";
|
| 1411 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1412 |
|
|
|
| 1413 |
|
|
when x"00" => --Break second part cyc 1
|
| 1414 |
|
|
wr_ctr <= "01"; --put dat_out2 onto stack
|
| 1415 |
|
|
dat_out1 <= reg_pc(15 downto 8);
|
| 1416 |
|
|
add_fg <= x"7";
|
| 1417 |
|
|
dat2pc_fg <= '0';
|
| 1418 |
|
|
pc_dec_fg <= '0';
|
| 1419 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1420 |
|
|
|
| 1421 |
|
|
when others =>
|
| 1422 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1423 |
|
|
end case; --Cycle 1
|
| 1424 |
|
|
|
| 1425 |
|
|
|
| 1426 |
|
|
-- End cycle 1 =========================================================
|
| 1427 |
|
|
|
| 1428 |
|
|
when x"2" =>
|
| 1429 |
|
|
|
| 1430 |
|
|
case instruction_in(7 downto 0) is
|
| 1431 |
|
|
-- ====================================================================================
|
| 1432 |
|
|
|
| 1433 |
|
|
when x"48" => --PHA 3rd part accumulator onto stack
|
| 1434 |
|
|
pc_inc_fg <= '1';
|
| 1435 |
|
|
add_fg <= x"0";
|
| 1436 |
|
|
reg_sp <= reg_sp + "1";
|
| 1437 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1438 |
|
|
when x"08" => --PHP 3rd part Status reg onto stack
|
| 1439 |
|
|
pc_inc_fg <= '1';
|
| 1440 |
|
|
add_fg <= x"0";
|
| 1441 |
|
|
reg_sp <= reg_sp + "1";
|
| 1442 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1443 |
|
|
|
| 1444 |
|
|
when x"68" => --PLA 3rd part Pull Accumulator from Stack
|
| 1445 |
|
|
pc_dec_fg <= '0';
|
| 1446 |
|
|
add_fg <= x"0";
|
| 1447 |
|
|
pc_inc_fg <= '1';
|
| 1448 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1449 |
|
|
when x"28" => --PLP 3rd part Pull Status from Stack
|
| 1450 |
|
|
pc_dec_fg <= '0';
|
| 1451 |
|
|
add_fg <= x"0";
|
| 1452 |
|
|
pc_inc_fg <= '1';
|
| 1453 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1454 |
|
|
|
| 1455 |
|
|
when x"F0" => --BEQ branch true 3rd part.
|
| 1456 |
|
|
if branch_fg = '1' then
|
| 1457 |
|
|
branch_fg <= '0';
|
| 1458 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1459 |
|
|
else
|
| 1460 |
|
|
pc_inc_fg <= '0';
|
| 1461 |
|
|
cycle_ctr <= x"0";
|
| 1462 |
|
|
end if;
|
| 1463 |
|
|
when x"D0" => --BNE branch true 3rd part.
|
| 1464 |
|
|
if branch_fg = '1' then
|
| 1465 |
|
|
branch_fg <= '0';
|
| 1466 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1467 |
|
|
else
|
| 1468 |
|
|
pc_inc_fg <= '0';
|
| 1469 |
|
|
cycle_ctr <= x"0";
|
| 1470 |
|
|
end if;
|
| 1471 |
|
|
when x"10" => --BPL plus true 3rd part.
|
| 1472 |
|
|
if branch_fg = '1' then
|
| 1473 |
|
|
branch_fg <= '0';
|
| 1474 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1475 |
|
|
else
|
| 1476 |
|
|
pc_inc_fg <= '0';
|
| 1477 |
|
|
cycle_ctr <= x"0";
|
| 1478 |
|
|
end if;
|
| 1479 |
|
|
when x"30" => --BM1 negative true 3rd part.
|
| 1480 |
|
|
if branch_fg = '1' then
|
| 1481 |
|
|
branch_fg <= '0';
|
| 1482 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1483 |
|
|
else
|
| 1484 |
|
|
pc_inc_fg <= '0';
|
| 1485 |
|
|
cycle_ctr <= x"0";
|
| 1486 |
|
|
end if;
|
| 1487 |
|
|
when x"50" => --BVC overflow false 3rd part.
|
| 1488 |
|
|
if branch_fg = '1' then
|
| 1489 |
|
|
branch_fg <= '0';
|
| 1490 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1491 |
|
|
else
|
| 1492 |
|
|
pc_inc_fg <= '0';
|
| 1493 |
|
|
cycle_ctr <= x"0";
|
| 1494 |
|
|
end if;
|
| 1495 |
|
|
when x"70" => --BVS overflow true 3rd part.
|
| 1496 |
|
|
if branch_fg = '1' then
|
| 1497 |
|
|
branch_fg <= '0';
|
| 1498 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1499 |
|
|
else
|
| 1500 |
|
|
pc_inc_fg <= '0';
|
| 1501 |
|
|
cycle_ctr <= x"0";
|
| 1502 |
|
|
end if;
|
| 1503 |
|
|
when x"90" => --BCC carry false 3rd part.
|
| 1504 |
|
|
if branch_fg = '1' then
|
| 1505 |
|
|
branch_fg <= '0';
|
| 1506 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1507 |
|
|
else
|
| 1508 |
|
|
pc_inc_fg <= '0';
|
| 1509 |
|
|
cycle_ctr <= x"0";
|
| 1510 |
|
|
end if;
|
| 1511 |
|
|
when x"B0" => --BCS carry true 3rd part.
|
| 1512 |
|
|
if branch_fg = '1' then
|
| 1513 |
|
|
branch_fg <= '0';
|
| 1514 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1515 |
|
|
else
|
| 1516 |
|
|
pc_inc_fg <= '0';
|
| 1517 |
|
|
cycle_ctr <= x"0";
|
| 1518 |
|
|
end if;
|
| 1519 |
|
|
-- ====================================================================================
|
| 1520 |
|
|
when x"84" => --STY zero 3rd part proto
|
| 1521 |
|
|
pc_inc_fg <= '1';
|
| 1522 |
|
|
add_fg <= x"0";
|
| 1523 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1524 |
|
|
when x"85" => --STA zero 3rd part proto
|
| 1525 |
|
|
pc_inc_fg <= '1';
|
| 1526 |
|
|
add_fg <= x"0";
|
| 1527 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1528 |
|
|
when x"86" => --STX zero 3rd part proto
|
| 1529 |
|
|
pc_inc_fg <= '1';
|
| 1530 |
|
|
add_fg <= x"0";
|
| 1531 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1532 |
|
|
when x"94" => --STY zero, X 3rd part proto
|
| 1533 |
|
|
pc_inc_fg <= '1';
|
| 1534 |
|
|
add_fg <= x"0";
|
| 1535 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1536 |
|
|
when x"95" => --STA zero, X 3rd part proto
|
| 1537 |
|
|
pc_inc_fg <= '1';
|
| 1538 |
|
|
add_fg <= x"0";
|
| 1539 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1540 |
|
|
when x"96" => --STX zero, Y 3rd part proto
|
| 1541 |
|
|
pc_inc_fg <= '1';
|
| 1542 |
|
|
add_fg <= x"0";
|
| 1543 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 1544 |
|
|
|
| 1545 |
|
|
-- ========================================================================================
|
| 1546 |
|
|
when x"A5" => --LDA zero 3rd part proto
|
| 1547 |
|
|
pc_inc_fg <= '0';
|
| 1548 |
|
|
-- add_fg <= x"0";
|
| 1549 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 1550 |
|
|
flags_fg <= "01";
|
| 1551 |
|
|
dat_out2 <= data_rd;
|
| 1552 |
|
|
cycle_ctr <= x"0";
|
| 1553 |
|
|
when x"A4" => --LDY zero 3rd part
|
| 1554 |
|
|
pc_inc_fg <= '0';
|
| 1555 |
|
|
-- add_fg <= x"0";
|
| 1556 |
|
|
reg_y <= data_rd;
|
| 1557 |
|
|
flags_fg <= "01";
|
| 1558 |
|
|
dat_out2 <= data_rd;
|
| 1559 |
|
|
cycle_ctr <= x"0";
|
| 1560 |
|
|
when x"A6" => --LDX zero 3rd part
|
| 1561 |
|
|
pc_inc_fg <= '0';
|
| 1562 |
|
|
-- add_fg <= x"0";
|
| 1563 |
|
|
reg_x <= data_rd;
|
| 1564 |
|
|
flags_fg <= "01";
|
| 1565 |
|
|
dat_out2 <= data_rd;
|
| 1566 |
|
|
cycle_ctr <= x"0";
|
| 1567 |
|
|
when x"B5" => --LDA zero,X 3rd part
|
| 1568 |
|
|
pc_inc_fg <= '0';
|
| 1569 |
|
|
-- add_fg <= x"0";
|
| 1570 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 1571 |
|
|
flags_fg <= "01";
|
| 1572 |
|
|
dat_out2 <= data_rd;
|
| 1573 |
|
|
cycle_ctr <= x"0";
|
| 1574 |
|
|
when x"B4" => --LDY zero,X 3rd part
|
| 1575 |
|
|
pc_inc_fg <= '0';
|
| 1576 |
|
|
-- add_fg <= x"0";
|
| 1577 |
|
|
reg_y <= data_rd;
|
| 1578 |
|
|
flags_fg <= "01";
|
| 1579 |
|
|
dat_out2 <= data_rd;
|
| 1580 |
|
|
cycle_ctr <= x"0";
|
| 1581 |
|
|
when x"B6" => --LDX zero,Y 3rd part
|
| 1582 |
|
|
wr_ctr <= "00";
|
| 1583 |
|
|
pc_inc_fg <= '0';
|
| 1584 |
|
|
-- add_fg <= x"0";
|
| 1585 |
|
|
reg_x <= data_rd;
|
| 1586 |
|
|
flags_fg <= "01";
|
| 1587 |
|
|
dat_out2 <= data_rd;
|
| 1588 |
|
|
cycle_ctr <= x"0";
|
| 1589 |
|
|
when x"05" => --ORA zero 3rd part
|
| 1590 |
|
|
pc_inc_fg <= '0';
|
| 1591 |
|
|
-- add_fg <= x"0";
|
| 1592 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd;
|
| 1593 |
|
|
flags_fg <= "01";
|
| 1594 |
|
|
dat_out2 <= reg_a(7 downto 0) or data_rd;
|
| 1595 |
|
|
cycle_ctr <= x"0";
|
| 1596 |
|
|
when x"15" => --ORA zero,X 3rd part
|
| 1597 |
|
|
pc_inc_fg <= '0';
|
| 1598 |
|
|
-- add_fg <= x"0";
|
| 1599 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd;
|
| 1600 |
|
|
flags_fg <= "01";
|
| 1601 |
|
|
dat_out2 <= reg_a(7 downto 0) or data_rd;
|
| 1602 |
|
|
cycle_ctr <= x"0";
|
| 1603 |
|
|
when x"24" => --BIT zero 3rd part
|
| 1604 |
|
|
pc_inc_fg <= '0';
|
| 1605 |
|
|
-- add_fg <= x"0";
|
| 1606 |
|
|
n_fg <= data_rd(7);
|
| 1607 |
|
|
v_fg <= data_rd(6);
|
| 1608 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 1609 |
|
|
flags_fg <= "01";
|
| 1610 |
|
|
cycle_ctr <= x"0";
|
| 1611 |
|
|
when x"25" => --AND zero 3rd part
|
| 1612 |
|
|
pc_inc_fg <= '0';
|
| 1613 |
|
|
-- add_fg <= x"0";
|
| 1614 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd;
|
| 1615 |
|
|
flags_fg <= "01";
|
| 1616 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 1617 |
|
|
cycle_ctr <= x"0";
|
| 1618 |
|
|
|
| 1619 |
|
|
when x"35" => --AND zero,X 3rd part
|
| 1620 |
|
|
pc_inc_fg <= '0';
|
| 1621 |
|
|
-- add_fg <= x"0";
|
| 1622 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd;
|
| 1623 |
|
|
flags_fg <= "01";
|
| 1624 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 1625 |
|
|
cycle_ctr <= x"0";
|
| 1626 |
|
|
|
| 1627 |
|
|
when x"45" => --EOR zero 3rd part
|
| 1628 |
|
|
pc_inc_fg <= '0';
|
| 1629 |
|
|
-- add_fg <= x"0";
|
| 1630 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd;
|
| 1631 |
|
|
flags_fg <= "01";
|
| 1632 |
|
|
dat_out2 <= reg_a(7 downto 0) xor data_rd;
|
| 1633 |
|
|
cycle_ctr <= x"0";
|
| 1634 |
|
|
|
| 1635 |
|
|
when x"55" => --EOR zero,X 3rd part
|
| 1636 |
|
|
pc_inc_fg <= '0';
|
| 1637 |
|
|
-- add_fg <= x"0";
|
| 1638 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd;
|
| 1639 |
|
|
flags_fg <= "01";
|
| 1640 |
|
|
dat_out2 <= reg_a(7 downto 0) xor data_rd;
|
| 1641 |
|
|
cycle_ctr <= x"0";
|
| 1642 |
|
|
|
| 1643 |
|
|
when x"65" => --ADC zero 3rd part
|
| 1644 |
|
|
pc_inc_fg <= '0';
|
| 1645 |
|
|
-- add_fg <= x"0";
|
| 1646 |
|
|
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8));
|
| 1647 |
|
|
flags_fg <= "01";
|
| 1648 |
|
|
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8));
|
| 1649 |
|
|
cycle_ctr <= x"0";
|
| 1650 |
|
|
|
| 1651 |
|
|
when x"75" => --ADC zero,X 3rd part
|
| 1652 |
|
|
pc_inc_fg <= '0';
|
| 1653 |
|
|
-- add_fg <= x"0";
|
| 1654 |
|
|
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8));
|
| 1655 |
|
|
flags_fg <= "01";
|
| 1656 |
|
|
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8));
|
| 1657 |
|
|
cycle_ctr <= x"0";
|
| 1658 |
|
|
|
| 1659 |
|
|
when x"C4" => --CPY zero 3rd part
|
| 1660 |
|
|
pc_inc_fg <= '0';
|
| 1661 |
|
|
-- add_fg <= x"0";
|
| 1662 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 1663 |
|
|
flags_fg <= "01";
|
| 1664 |
|
|
dat_out2 <= data_rd;
|
| 1665 |
|
|
cycle_ctr <= x"0";
|
| 1666 |
|
|
when x"C5" => --CMP zero 3rd part
|
| 1667 |
|
|
flags_fg <= "01";
|
| 1668 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd;
|
| 1669 |
|
|
if reg_a(7 downto 0) > data_rd then
|
| 1670 |
|
|
reg_a(8) <= '1';
|
| 1671 |
|
|
else
|
| 1672 |
|
|
reg_a(8) <= '0';
|
| 1673 |
|
|
end if;
|
| 1674 |
|
|
pc_inc_fg <= '0';
|
| 1675 |
|
|
cycle_ctr <= x"0";
|
| 1676 |
|
|
when x"C6" => --DEC zero 3rd part
|
| 1677 |
|
|
dat_out1 <= data_rd - x"01";
|
| 1678 |
|
|
dat_out2 <= data_rd - x"01";
|
| 1679 |
|
|
wr_ctr <= "01";
|
| 1680 |
|
|
flags_fg <= "01";
|
| 1681 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1682 |
|
|
when x"D5" => --CMP zero,X 3rd part
|
| 1683 |
|
|
flags_fg <= "01";
|
| 1684 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd;
|
| 1685 |
|
|
if reg_a(7 downto 0) > data_rd then
|
| 1686 |
|
|
reg_a(8) <= '1';
|
| 1687 |
|
|
else
|
| 1688 |
|
|
reg_a(8) <= '0';
|
| 1689 |
|
|
end if;
|
| 1690 |
|
|
pc_inc_fg <= '0';
|
| 1691 |
|
|
cycle_ctr <= x"0";
|
| 1692 |
|
|
when x"D6" => --DEC zero,X 3rd part
|
| 1693 |
|
|
pc_inc_fg <= '0';
|
| 1694 |
|
|
add_fg <= x"0";
|
| 1695 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 1696 |
|
|
flags_fg <= "01";
|
| 1697 |
|
|
dat_out2 <= data_rd;
|
| 1698 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1699 |
|
|
when x"E4" => --CPX zero 3rd part
|
| 1700 |
|
|
pc_inc_fg <= '0';
|
| 1701 |
|
|
add_fg <= x"0";
|
| 1702 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 1703 |
|
|
flags_fg <= "01";
|
| 1704 |
|
|
dat_out2 <= data_rd;
|
| 1705 |
|
|
cycle_ctr <= x"0";
|
| 1706 |
|
|
when x"E5" => --SBC zero 3rd part
|
| 1707 |
|
|
pc_inc_fg <= '0';
|
| 1708 |
|
|
-- add_fg <= x"0";
|
| 1709 |
|
|
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8));
|
| 1710 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8));
|
| 1711 |
|
|
flags_fg <= "01";
|
| 1712 |
|
|
cycle_ctr <= x"0";
|
| 1713 |
|
|
|
| 1714 |
|
|
|
| 1715 |
|
|
when x"F5" => --SBC zero,X 3rd part
|
| 1716 |
|
|
pc_inc_fg <= '0';
|
| 1717 |
|
|
-- add_fg <= x"0";
|
| 1718 |
|
|
reg_a <= reg_a - ('0' & data_rd) - ("00000000" & reg_a(8));
|
| 1719 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8));
|
| 1720 |
|
|
flags_fg <= "01";
|
| 1721 |
|
|
cycle_ctr <= x"0";
|
| 1722 |
|
|
|
| 1723 |
|
|
when x"E6" => --INC zero 3rd part
|
| 1724 |
|
|
dat_out1 <= data_rd + x"01";
|
| 1725 |
|
|
dat_out2 <= data_rd + x"01";
|
| 1726 |
|
|
wr_ctr <= "01";
|
| 1727 |
|
|
flags_fg <= "01";
|
| 1728 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1729 |
|
|
when x"F6" => --INC zero,X 3rd part
|
| 1730 |
|
|
dat_out1 <= data_rd + x"01";
|
| 1731 |
|
|
dat_out2 <= data_rd + x"01";
|
| 1732 |
|
|
wr_ctr <= "01";
|
| 1733 |
|
|
flags_fg <= "01";
|
| 1734 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1735 |
|
|
|
| 1736 |
|
|
when x"66" => --ROR zero 3rd part
|
| 1737 |
|
|
reg_a(8) <= data_rd(0);
|
| 1738 |
|
|
dat_out1 <= reg_a(8) & data_rd(7 downto 1);
|
| 1739 |
|
|
dat_out2 <= reg_a(8) & data_rd(7 downto 1);
|
| 1740 |
|
|
wr_ctr <= "01";
|
| 1741 |
|
|
flags_fg <= "01";
|
| 1742 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1743 |
|
|
|
| 1744 |
|
|
when x"76" => --ROR zero,X 3rd part
|
| 1745 |
|
|
reg_a(8) <= data_rd(0);
|
| 1746 |
|
|
dat_out1 <= reg_a(8) & data_rd(7 downto 1);
|
| 1747 |
|
|
dat_out2 <= reg_a(8) & data_rd(7 downto 1);
|
| 1748 |
|
|
wr_ctr <= "01";
|
| 1749 |
|
|
flags_fg <= "01";
|
| 1750 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1751 |
|
|
|
| 1752 |
|
|
when x"26" => --ROL zero 3rd part
|
| 1753 |
|
|
dat_out1(7 downto 1) <= data_rd(6 downto 0);
|
| 1754 |
|
|
dat_out1(0) <= reg_a(8);
|
| 1755 |
|
|
dat_out2(7 downto 1) <= data_rd(6 downto 0);
|
| 1756 |
|
|
dat_out2(0) <= reg_a(8);
|
| 1757 |
|
|
flags_fg <= "01";
|
| 1758 |
|
|
wr_ctr <= "01";
|
| 1759 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1760 |
|
|
when x"36" => --ROL zero,X 3rd part
|
| 1761 |
|
|
dat_out1(7 downto 1) <= data_rd(6 downto 0);
|
| 1762 |
|
|
dat_out1(0) <= reg_a(8);
|
| 1763 |
|
|
dat_out2(7 downto 1) <= data_rd(6 downto 0);
|
| 1764 |
|
|
dat_out2(0) <= reg_a(8);
|
| 1765 |
|
|
flags_fg <= "01";
|
| 1766 |
|
|
wr_ctr <= "01";
|
| 1767 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1768 |
|
|
when x"46" => --LSR zero 3rd part
|
| 1769 |
|
|
dat_out1 <= '0' & reg_a(7 downto 1);
|
| 1770 |
|
|
dat_out2 <= '0' & reg_a(7 downto 1);
|
| 1771 |
|
|
reg_a(8) <= data_rd(0);
|
| 1772 |
|
|
wr_ctr <= "01";
|
| 1773 |
|
|
flags_fg <= "01";
|
| 1774 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1775 |
|
|
when x"56" => --LSR zero,X 3rd part
|
| 1776 |
|
|
dat_out1 <= '0' & reg_a(7 downto 1);
|
| 1777 |
|
|
dat_out2 <= '0' & reg_a(7 downto 1);
|
| 1778 |
|
|
reg_a(8) <= data_rd(0);
|
| 1779 |
|
|
wr_ctr <= "01";
|
| 1780 |
|
|
flags_fg <= "01";
|
| 1781 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1782 |
|
|
when x"06" => --ASL zero 3rd part
|
| 1783 |
|
|
reg_a(8) <= data_rd(7);
|
| 1784 |
|
|
dat_out1 <= data_rd(6 downto 0) & '0';
|
| 1785 |
|
|
dat_out2 <= data_rd(6 downto 0) & '0';
|
| 1786 |
|
|
wr_ctr <= "01";
|
| 1787 |
|
|
flags_fg <= "01";
|
| 1788 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1789 |
|
|
when x"16" => --ASL zero,X 3rd part
|
| 1790 |
|
|
reg_a(8) <= data_rd(7);
|
| 1791 |
|
|
dat_out1 <= data_rd(6 downto 0) & data_rd(0);
|
| 1792 |
|
|
dat_out2 <= data_rd(6 downto 0) & data_rd(0);
|
| 1793 |
|
|
wr_ctr <= "01";
|
| 1794 |
|
|
flags_fg <= "01";
|
| 1795 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1796 |
|
|
|
| 1797 |
|
|
-- =============================================================================================
|
| 1798 |
|
|
when x"A1" => --LDA (zero,x) 3rd part proto
|
| 1799 |
|
|
add_fg <= x"6";
|
| 1800 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1801 |
|
|
when x"B1" => --LDA (zero),y 3rd part proto
|
| 1802 |
|
|
add_fg <= x"6";
|
| 1803 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1804 |
|
|
|
| 1805 |
|
|
when x"21" => --AMD (zero,x) 3rd part proto
|
| 1806 |
|
|
add_fg <= x"6";
|
| 1807 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1808 |
|
|
when x"31" => --AND (zero),y 3rd part proto
|
| 1809 |
|
|
add_fg <= x"6";
|
| 1810 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1811 |
|
|
|
| 1812 |
|
|
when x"41" => --EOR (zero,x) 3rd part proto
|
| 1813 |
|
|
add_fg <= x"6";
|
| 1814 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1815 |
|
|
when x"51" => --EOR (zero),y 3rd part proto
|
| 1816 |
|
|
add_fg <= x"6";
|
| 1817 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1818 |
|
|
|
| 1819 |
|
|
when x"01" => --OR (zero,x) 3rd part proto
|
| 1820 |
|
|
add_fg <= x"6";
|
| 1821 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1822 |
|
|
when x"11" => --OR (zero),y 3rd part proto
|
| 1823 |
|
|
add_fg <= x"6";
|
| 1824 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1825 |
|
|
|
| 1826 |
|
|
when x"61" => --ADC (zero,x) 3rd part proto
|
| 1827 |
|
|
add_fg <= x"6";
|
| 1828 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1829 |
|
|
when x"71" => --ADC (zero),y 3rd part proto
|
| 1830 |
|
|
add_fg <= x"6";
|
| 1831 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1832 |
|
|
|
| 1833 |
|
|
when x"E1" => --SBC (zero,x) 3rd part proto
|
| 1834 |
|
|
add_fg <= x"6";
|
| 1835 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1836 |
|
|
when x"F1" => --SBC (zero),y 3rd part proto
|
| 1837 |
|
|
add_fg <= x"6";
|
| 1838 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1839 |
|
|
|
| 1840 |
|
|
when x"C1" => --CMP (zero,x) 3rd part proto
|
| 1841 |
|
|
add_fg <= x"6";
|
| 1842 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1843 |
|
|
when x"D1" => --CMP (zero),y 3rd part proto
|
| 1844 |
|
|
add_fg <= x"6";
|
| 1845 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1846 |
|
|
|
| 1847 |
|
|
when x"81" => --STA (zero,x) 3rd part proto
|
| 1848 |
|
|
add_fg <= x"4";
|
| 1849 |
|
|
wr_ctr <= "01";
|
| 1850 |
|
|
dat_out1 <= reg_a(7 downto 0);
|
| 1851 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1852 |
|
|
when x"91" => --STA (zero),y 3rd part proto
|
| 1853 |
|
|
add_fg <= x"6";
|
| 1854 |
|
|
wr_ctr <= "01";
|
| 1855 |
|
|
dat_out1 <= reg_a(7 downto 0);
|
| 1856 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1857 |
|
|
-- ==============================================================================
|
| 1858 |
|
|
when x"AD" => --LDA abs 3rd part.
|
| 1859 |
|
|
add_fg <= x"0";
|
| 1860 |
|
|
pc_inc_fg <= '1';
|
| 1861 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1862 |
|
|
|
| 1863 |
|
|
when x"BD" => --LDA, x abs 3rd part.
|
| 1864 |
|
|
add_fg <= x"0";
|
| 1865 |
|
|
pc_inc_fg <= '1';
|
| 1866 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1867 |
|
|
|
| 1868 |
|
|
when x"B9" => --LDA, Y abs 3rd part
|
| 1869 |
|
|
add_fg <= x"0";
|
| 1870 |
|
|
pc_inc_fg <= '1';
|
| 1871 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1872 |
|
|
|
| 1873 |
|
|
|
| 1874 |
|
|
when x"2D" => --AND abs 3rd part.
|
| 1875 |
|
|
add_fg <= x"0";
|
| 1876 |
|
|
pc_inc_fg <= '1';
|
| 1877 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1878 |
|
|
|
| 1879 |
|
|
when x"3D" => --AND, x abs 3rd part.
|
| 1880 |
|
|
add_fg <= x"0";
|
| 1881 |
|
|
pc_inc_fg <= '1';
|
| 1882 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1883 |
|
|
when x"39" => --AND, Y abs 3rd part.
|
| 1884 |
|
|
add_fg <= x"0";
|
| 1885 |
|
|
pc_inc_fg <= '1';
|
| 1886 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1887 |
|
|
|
| 1888 |
|
|
when x"0D" => --ORA abs 3rd part.
|
| 1889 |
|
|
add_fg <= x"0";
|
| 1890 |
|
|
pc_inc_fg <= '1';
|
| 1891 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1892 |
|
|
when x"1D" => --ORA, x abs 3rd part.
|
| 1893 |
|
|
add_fg <= x"0";
|
| 1894 |
|
|
pc_inc_fg <= '1';
|
| 1895 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1896 |
|
|
when x"19" => --ORA, Y abs 3rd part.
|
| 1897 |
|
|
add_fg <= x"0";
|
| 1898 |
|
|
pc_inc_fg <= '1';
|
| 1899 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1900 |
|
|
|
| 1901 |
|
|
when x"4D" => --EOR abs 3rd part.
|
| 1902 |
|
|
add_fg <= x"0";
|
| 1903 |
|
|
pc_inc_fg <= '1';
|
| 1904 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1905 |
|
|
when x"5D" => --EOR, x abs 3rd part.
|
| 1906 |
|
|
add_fg <= x"0";
|
| 1907 |
|
|
pc_inc_fg <= '1';
|
| 1908 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1909 |
|
|
when x"59" => --EOR, Y abs 3rd part.
|
| 1910 |
|
|
add_fg <= x"0";
|
| 1911 |
|
|
pc_inc_fg <= '1';
|
| 1912 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1913 |
|
|
|
| 1914 |
|
|
when x"6D" => --ADC abs 3rd part.
|
| 1915 |
|
|
add_fg <= x"0";
|
| 1916 |
|
|
pc_inc_fg <= '1';
|
| 1917 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1918 |
|
|
when x"7D" => --ADC, x abs 3rd part.
|
| 1919 |
|
|
add_fg <= x"0";
|
| 1920 |
|
|
pc_inc_fg <= '1';
|
| 1921 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1922 |
|
|
when x"79" => --ADC, Y abs 3rd part.
|
| 1923 |
|
|
add_fg <= x"0";
|
| 1924 |
|
|
pc_inc_fg <= '1';
|
| 1925 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1926 |
|
|
|
| 1927 |
|
|
when x"ED" => --SBC abs 3rd part.
|
| 1928 |
|
|
add_fg <= x"0";
|
| 1929 |
|
|
pc_inc_fg <= '1';
|
| 1930 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1931 |
|
|
when x"FD" => --SBC, x abs 3rd part.
|
| 1932 |
|
|
add_fg <= x"0";
|
| 1933 |
|
|
pc_inc_fg <= '1';
|
| 1934 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1935 |
|
|
when x"F9" => --SBC, Y abs 3rd part.
|
| 1936 |
|
|
add_fg <= x"0";
|
| 1937 |
|
|
pc_inc_fg <= '1';
|
| 1938 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1939 |
|
|
|
| 1940 |
|
|
when x"AE" => --LDX abs 3rd part.
|
| 1941 |
|
|
add_fg <= x"0";
|
| 1942 |
|
|
pc_inc_fg <= '1';
|
| 1943 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1944 |
|
|
when x"BE" => --LDX, y abs 3rd part.
|
| 1945 |
|
|
add_fg <= x"0";
|
| 1946 |
|
|
pc_inc_fg <= '1';
|
| 1947 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1948 |
|
|
when x"AC" => --LDY abs 3rd part.
|
| 1949 |
|
|
add_fg <= x"0";
|
| 1950 |
|
|
pc_inc_fg <= '1';
|
| 1951 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1952 |
|
|
when x"BC" => --LDY, x abs 3rd part.
|
| 1953 |
|
|
add_fg <= x"0";
|
| 1954 |
|
|
pc_inc_fg <= '1';
|
| 1955 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1956 |
|
|
|
| 1957 |
|
|
when x"2C" => --BIT abs 3rd part.
|
| 1958 |
|
|
add_fg <= x"0";
|
| 1959 |
|
|
pc_inc_fg <= '1';
|
| 1960 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1961 |
|
|
|
| 1962 |
|
|
when x"CD" => --CMP abs 3rd part.
|
| 1963 |
|
|
add_fg <= x"0";
|
| 1964 |
|
|
pc_inc_fg <= '1';
|
| 1965 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1966 |
|
|
when x"DD" => --CMP, x abs 3rd part.
|
| 1967 |
|
|
add_fg <= x"0";
|
| 1968 |
|
|
pc_inc_fg <= '1';
|
| 1969 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1970 |
|
|
when x"D9" => --CMP, Y abs 3rd part.
|
| 1971 |
|
|
add_fg <= x"0";
|
| 1972 |
|
|
pc_inc_fg <= '1';
|
| 1973 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1974 |
|
|
when x"EC" => --CPX abs 3rd part.
|
| 1975 |
|
|
add_fg <= x"0";
|
| 1976 |
|
|
pc_inc_fg <= '1';
|
| 1977 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1978 |
|
|
when x"CC" => --CPY abs 3rd part.
|
| 1979 |
|
|
add_fg <= x"0";
|
| 1980 |
|
|
pc_inc_fg <= '1';
|
| 1981 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1982 |
|
|
|
| 1983 |
|
|
-- ................................................................................
|
| 1984 |
|
|
when x"8D" => --STA abs 3rd part.
|
| 1985 |
|
|
wr_ctr <= "00";
|
| 1986 |
|
|
add_fg <= x"4";
|
| 1987 |
|
|
pc_inc_fg <= '1';
|
| 1988 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1989 |
|
|
when x"9D" => --STA,x abs 3rd part.
|
| 1990 |
|
|
wr_ctr <= "00";
|
| 1991 |
|
|
add_fg <= x"5";
|
| 1992 |
|
|
pc_inc_fg <= '1';
|
| 1993 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1994 |
|
|
when x"99" => --STA, y abs 3rd part.
|
| 1995 |
|
|
wr_ctr <= "00";
|
| 1996 |
|
|
add_fg <= x"6";
|
| 1997 |
|
|
pc_inc_fg <= '1';
|
| 1998 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 1999 |
|
|
when x"8E" => --STX abs 3rd part.
|
| 2000 |
|
|
wr_ctr <= "00";
|
| 2001 |
|
|
add_fg <= x"4";
|
| 2002 |
|
|
pc_inc_fg <= '1';
|
| 2003 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2004 |
|
|
when x"8C" => --STY abs 3rd part.
|
| 2005 |
|
|
wr_ctr <= "00";
|
| 2006 |
|
|
add_fg <= x"4";
|
| 2007 |
|
|
pc_inc_fg <= '1';
|
| 2008 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2009 |
|
|
-- ................................................................................
|
| 2010 |
|
|
|
| 2011 |
|
|
when x"EE" => --INC abs 3rd part.
|
| 2012 |
|
|
add_fg <= x"f";
|
| 2013 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2014 |
|
|
when x"FE" => --INC, x abs 3rd part.
|
| 2015 |
|
|
add_fg <= x"f";
|
| 2016 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2017 |
|
|
when x"CE" => --DEC abs 3rd part.
|
| 2018 |
|
|
add_fg <= x"f";
|
| 2019 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2020 |
|
|
when x"DE" => --DEC, x abs 3rd part.
|
| 2021 |
|
|
add_fg <= x"f";
|
| 2022 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2023 |
|
|
when x"2E" => --ROL abs 3rd part.
|
| 2024 |
|
|
add_fg <= x"f";
|
| 2025 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2026 |
|
|
when x"3E" => --ROL, x abs 3rd part.
|
| 2027 |
|
|
add_fg <= x"f";
|
| 2028 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2029 |
|
|
when x"6E" => --ROR abs 3rd part.
|
| 2030 |
|
|
add_fg <= x"f";
|
| 2031 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2032 |
|
|
when x"7E" => --ROR, x abs 3rd part.
|
| 2033 |
|
|
add_fg <= x"f";
|
| 2034 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2035 |
|
|
when x"4E" => --LSR abs 3rd part.
|
| 2036 |
|
|
add_fg <= x"f";
|
| 2037 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2038 |
|
|
when x"5E" => --LSR, x abs 3rd part.
|
| 2039 |
|
|
add_fg <= x"f";
|
| 2040 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2041 |
|
|
when x"0E" => --ASL abs 3rd part.
|
| 2042 |
|
|
add_fg <= x"f";
|
| 2043 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2044 |
|
|
when x"1E" => --ASL, x abs 3rd part.
|
| 2045 |
|
|
add_fg <= x"f";
|
| 2046 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2047 |
|
|
-- ............................................................................
|
| 2048 |
|
|
-- ==============================================================================
|
| 2049 |
|
|
when x"4C" => --JMP abs 3rd part
|
| 2050 |
|
|
dat2pc_fg <= '0';
|
| 2051 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2052 |
|
|
when x"6C" => --JMP indirect 3rd part
|
| 2053 |
|
|
add_fg <= x"B";
|
| 2054 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2055 |
|
|
when x"20" => --JSR abs 3rd part
|
| 2056 |
|
|
dat2pc_fg <= '0';
|
| 2057 |
|
|
add_fg <= x"7";
|
| 2058 |
|
|
wr_ctr <= "01";
|
| 2059 |
|
|
-- reg_sp <= reg_sp + "1";
|
| 2060 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2061 |
|
|
when x"60" => --RTS third part
|
| 2062 |
|
|
dat2pc_fg <= '1';
|
| 2063 |
|
|
add_fg <= x"0";
|
| 2064 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2065 |
|
|
when x"40" => --RTI 3rd part pull old status from stack
|
| 2066 |
|
|
pc_dec_fg <= '0'; --Get 1st PC byte
|
| 2067 |
|
|
n_fg <= data_rd(7); --cyc 6
|
| 2068 |
|
|
v_fg <= data_rd(6);
|
| 2069 |
|
|
b_fg <= data_rd(4);
|
| 2070 |
|
|
d_fg <= data_rd(3);
|
| 2071 |
|
|
i_fg <= data_rd(2);
|
| 2072 |
|
|
z_fg <= data_rd(1);
|
| 2073 |
|
|
reg_a(8) <= data_rd(0);
|
| 2074 |
|
|
reg_sp <= reg_sp - "1";
|
| 2075 |
|
|
dat2pc_fg <= '1';
|
| 2076 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2077 |
|
|
|
| 2078 |
|
|
when x"00" => --Break third part cyc 2
|
| 2079 |
|
|
dat_out1 <= reg_pc(7 downto 0); --put dat_out1 onto stack set up dat_out2
|
| 2080 |
|
|
reg_sp <= reg_sp + "1";
|
| 2081 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2082 |
|
|
|
| 2083 |
|
|
when others =>
|
| 2084 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2085 |
|
|
end case; --Cycle 2
|
| 2086 |
|
|
|
| 2087 |
|
|
------------------------------------------------------------------------
|
| 2088 |
|
|
-- Cycle 3 is for single byte instructions ie TAY
|
| 2089 |
|
|
when x"3" =>
|
| 2090 |
|
|
|
| 2091 |
|
|
|
| 2092 |
|
|
|
| 2093 |
|
|
if instruction_in(7 downto 0) /= x"A2" and
|
| 2094 |
|
|
(
|
| 2095 |
|
|
instruction_in(3 downto 0) = x"3" or
|
| 2096 |
|
|
instruction_in(3 downto 0) = x"7" or
|
| 2097 |
|
|
instruction_in(3 downto 0) = x"B" or
|
| 2098 |
|
|
instruction_in(3 downto 0) = x"F"
|
| 2099 |
|
|
) then --NOPs
|
| 2100 |
|
|
cycle_ctr <= x"0";
|
| 2101 |
|
|
pc_dec_fg <= '1';
|
| 2102 |
|
|
else
|
| 2103 |
|
|
|
| 2104 |
|
|
case instruction_in(7 downto 0) is
|
| 2105 |
|
|
-- ======================================================================================
|
| 2106 |
|
|
when x"84" => --STY zero 4th part proto
|
| 2107 |
|
|
pc_inc_fg <= '0';
|
| 2108 |
|
|
cycle_ctr <= x"0";
|
| 2109 |
|
|
when x"85" => --STA zero 4th part proto
|
| 2110 |
|
|
pc_inc_fg <= '0';
|
| 2111 |
|
|
cycle_ctr <= x"0";
|
| 2112 |
|
|
when x"86" => --STX zero 4th part proto
|
| 2113 |
|
|
pc_inc_fg <= '0';
|
| 2114 |
|
|
cycle_ctr <= x"0";
|
| 2115 |
|
|
when x"94" => --STY zero, X 4th part proto
|
| 2116 |
|
|
pc_inc_fg <= '0';
|
| 2117 |
|
|
cycle_ctr <= x"0";
|
| 2118 |
|
|
when x"95" => --STA zero, X 4th part proto
|
| 2119 |
|
|
pc_inc_fg <= '0';
|
| 2120 |
|
|
cycle_ctr <= x"0";
|
| 2121 |
|
|
when x"96" => --STX zero, Y 4th part proto
|
| 2122 |
|
|
pc_inc_fg <= '0';
|
| 2123 |
|
|
cycle_ctr <= x"0";
|
| 2124 |
|
|
-- =======================================================================================
|
| 2125 |
|
|
|
| 2126 |
|
|
|
| 2127 |
|
|
when x"08" => --PHP 4th part accumulator onto stack
|
| 2128 |
|
|
pc_inc_fg <= '0';
|
| 2129 |
|
|
cycle_ctr <= x"0";
|
| 2130 |
|
|
|
| 2131 |
|
|
when x"48" => --PHA 4th part accumulator onto stack
|
| 2132 |
|
|
pc_inc_fg <= '0';
|
| 2133 |
|
|
cycle_ctr <= x"0";
|
| 2134 |
|
|
|
| 2135 |
|
|
|
| 2136 |
|
|
when x"68" => --PLA 4th part Pull Accumulator from Stack
|
| 2137 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 2138 |
|
|
pc_inc_fg <= '0';
|
| 2139 |
|
|
cycle_ctr <= x"0";
|
| 2140 |
|
|
when x"28" => --PLP 4th part Pull Status from Stack
|
| 2141 |
|
|
n_fg <= data_rd(7);
|
| 2142 |
|
|
v_fg <= data_rd(6);
|
| 2143 |
|
|
-- b_fg <= data_rd(4);
|
| 2144 |
|
|
d_fg <= data_rd(3);
|
| 2145 |
|
|
i_fg <= data_rd(2);
|
| 2146 |
|
|
z_fg <= data_rd(1);
|
| 2147 |
|
|
reg_a(8) <= data_rd(0);
|
| 2148 |
|
|
pc_inc_fg <= '0';
|
| 2149 |
|
|
cycle_ctr <= x"0";
|
| 2150 |
|
|
|
| 2151 |
|
|
when x"F0" => --BEQ branch true 4th part.
|
| 2152 |
|
|
branch_fg <= '0';
|
| 2153 |
|
|
pc_inc_fg <= '1';
|
| 2154 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2155 |
|
|
when x"D0" => --BNE branch true 4th part.
|
| 2156 |
|
|
branch_fg <= '0';
|
| 2157 |
|
|
pc_inc_fg <= '1';
|
| 2158 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2159 |
|
|
when x"10" => --BPL plus true 4th part.
|
| 2160 |
|
|
branch_fg <= '0';
|
| 2161 |
|
|
pc_inc_fg <= '1';
|
| 2162 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2163 |
|
|
when x"30" => --BM1 negative true 4th part.
|
| 2164 |
|
|
branch_fg <= '0';
|
| 2165 |
|
|
pc_inc_fg <= '1';
|
| 2166 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2167 |
|
|
when x"50" => --BVC overflow false 4th part.
|
| 2168 |
|
|
branch_fg <= '0';
|
| 2169 |
|
|
pc_inc_fg <= '1';
|
| 2170 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2171 |
|
|
when x"70" => --BVS overflow true 4th part.
|
| 2172 |
|
|
branch_fg <= '0';
|
| 2173 |
|
|
pc_inc_fg <= '1';
|
| 2174 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2175 |
|
|
when x"90" => --BCC carry false 4th part.
|
| 2176 |
|
|
branch_fg <= '0';
|
| 2177 |
|
|
pc_inc_fg <= '1';
|
| 2178 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2179 |
|
|
when x"B0" => --BCS carry true 4th part.
|
| 2180 |
|
|
branch_fg <= '0';
|
| 2181 |
|
|
pc_inc_fg <= '1';
|
| 2182 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2183 |
|
|
|
| 2184 |
|
|
-- ======================================================================================
|
| 2185 |
|
|
|
| 2186 |
|
|
when x"E6" => --INC zero fourth part
|
| 2187 |
|
|
wr_ctr <= "00";
|
| 2188 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2189 |
|
|
|
| 2190 |
|
|
when x"F6" => --INC zero,X fourth part
|
| 2191 |
|
|
wr_ctr <= "00";
|
| 2192 |
|
|
cycle_ctr <= x"0";
|
| 2193 |
|
|
when x"C6" => --DEC zero fourth part
|
| 2194 |
|
|
wr_ctr <= "00";
|
| 2195 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2196 |
|
|
when x"D6" => --DEC zero,X fourth part
|
| 2197 |
|
|
wr_ctr <= "00";
|
| 2198 |
|
|
cycle_ctr <= x"0";
|
| 2199 |
|
|
|
| 2200 |
|
|
when x"26" => --ROL zero fourth part
|
| 2201 |
|
|
wr_ctr <= "00";
|
| 2202 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2203 |
|
|
when x"36" => --ROL zero,X fourth part
|
| 2204 |
|
|
wr_ctr <= "00";
|
| 2205 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2206 |
|
|
when x"66" => --ROR zero fourth part
|
| 2207 |
|
|
wr_ctr <= "00";
|
| 2208 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2209 |
|
|
when x"76" => --ROR zero,X fourth part
|
| 2210 |
|
|
wr_ctr <= "00";
|
| 2211 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2212 |
|
|
when x"06" => --ASL zero fourth part
|
| 2213 |
|
|
wr_ctr <= "00";
|
| 2214 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2215 |
|
|
when x"16" => --ASL zero,X fourth part
|
| 2216 |
|
|
wr_ctr <= "00";
|
| 2217 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2218 |
|
|
when x"46" => --LSR zero fourth part
|
| 2219 |
|
|
wr_ctr <= "00";
|
| 2220 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2221 |
|
|
when x"56" => --LSR zero,X fourth part
|
| 2222 |
|
|
wr_ctr <= "00";
|
| 2223 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2224 |
|
|
--
|
| 2225 |
|
|
-- ==============================================================================
|
| 2226 |
|
|
when x"AD" => --LDA abs 4th part.
|
| 2227 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 2228 |
|
|
flags_fg <= "01";
|
| 2229 |
|
|
dat_out2 <= data_rd;
|
| 2230 |
|
|
pc_inc_fg <= '1';
|
| 2231 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2232 |
|
|
when x"BD" => --LDA, x abs 4th part.
|
| 2233 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 2234 |
|
|
flags_fg <= "01";
|
| 2235 |
|
|
dat_out2 <= data_rd;
|
| 2236 |
|
|
pc_inc_fg <= '1';
|
| 2237 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2238 |
|
|
|
| 2239 |
|
|
when x"B9" => --LDA, Y abs 4th part
|
| 2240 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 2241 |
|
|
flags_fg <= "01";
|
| 2242 |
|
|
dat_out2 <= data_rd;
|
| 2243 |
|
|
pc_inc_fg <= '1';
|
| 2244 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2245 |
|
|
|
| 2246 |
|
|
|
| 2247 |
|
|
when x"2D" => --AND abs 4th part.
|
| 2248 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd;
|
| 2249 |
|
|
flags_fg <= "01";
|
| 2250 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 2251 |
|
|
pc_inc_fg <= '1';
|
| 2252 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2253 |
|
|
|
| 2254 |
|
|
when x"3D" => --AND, x abs 4th part.
|
| 2255 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd;
|
| 2256 |
|
|
flags_fg <= "01";
|
| 2257 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 2258 |
|
|
pc_inc_fg <= '1';
|
| 2259 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2260 |
|
|
when x"39" => --AND, Y abs 4th part.
|
| 2261 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd;
|
| 2262 |
|
|
flags_fg <= "01";
|
| 2263 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 2264 |
|
|
pc_inc_fg <= '1';
|
| 2265 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2266 |
|
|
|
| 2267 |
|
|
when x"0D" => --ORA abs 4th part.
|
| 2268 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd;
|
| 2269 |
|
|
flags_fg <= "01";
|
| 2270 |
|
|
dat_out2 <= reg_a(7 downto 0) or data_rd;
|
| 2271 |
|
|
pc_inc_fg <= '1';
|
| 2272 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2273 |
|
|
when x"1D" => --ORA, x abs 4th part.
|
| 2274 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd;
|
| 2275 |
|
|
flags_fg <= "01";
|
| 2276 |
|
|
dat_out2 <= reg_a(7 downto 0) or data_rd;
|
| 2277 |
|
|
pc_inc_fg <= '1';
|
| 2278 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2279 |
|
|
when x"19" => --ORA, Y abs 4th part.
|
| 2280 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd;
|
| 2281 |
|
|
flags_fg <= "01";
|
| 2282 |
|
|
dat_out2 <= reg_a(7 downto 0) or data_rd;
|
| 2283 |
|
|
pc_inc_fg <= '1';
|
| 2284 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2285 |
|
|
|
| 2286 |
|
|
when x"4D" => --EOR abs 4th part.
|
| 2287 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd;
|
| 2288 |
|
|
flags_fg <= "01";
|
| 2289 |
|
|
dat_out2 <= reg_a(7 downto 0) xor data_rd;
|
| 2290 |
|
|
pc_inc_fg <= '1';
|
| 2291 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2292 |
|
|
when x"5D" => --EOR, x abs 4th part.
|
| 2293 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd;
|
| 2294 |
|
|
flags_fg <= "01";
|
| 2295 |
|
|
dat_out2 <= reg_a(7 downto 0) xor data_rd;
|
| 2296 |
|
|
pc_inc_fg <= '1';
|
| 2297 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2298 |
|
|
when x"59" => --EOR, Y abs 4th part.
|
| 2299 |
|
|
|
| 2300 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd;
|
| 2301 |
|
|
flags_fg <= "01";
|
| 2302 |
|
|
dat_out2 <= reg_a(7 downto 0) xor data_rd;
|
| 2303 |
|
|
pc_inc_fg <= '1';
|
| 2304 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2305 |
|
|
|
| 2306 |
|
|
when x"6D" => --ADC abs 4th part.
|
| 2307 |
|
|
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8));
|
| 2308 |
|
|
flags_fg <= "01";
|
| 2309 |
|
|
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8));
|
| 2310 |
|
|
pc_inc_fg <= '1';
|
| 2311 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2312 |
|
|
when x"7D" => --ADC, x abs 4th part.
|
| 2313 |
|
|
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8));
|
| 2314 |
|
|
flags_fg <= "01";
|
| 2315 |
|
|
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8));
|
| 2316 |
|
|
pc_inc_fg <= '1';
|
| 2317 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2318 |
|
|
when x"79" => --ADC, Y abs 4th part.
|
| 2319 |
|
|
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8));
|
| 2320 |
|
|
flags_fg <= "01";
|
| 2321 |
|
|
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8));
|
| 2322 |
|
|
pc_inc_fg <= '1';
|
| 2323 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2324 |
|
|
|
| 2325 |
|
|
when x"ED" => --SBC abs 4th part.
|
| 2326 |
|
|
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8));
|
| 2327 |
|
|
flags_fg <= "01";
|
| 2328 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8));
|
| 2329 |
|
|
pc_inc_fg <= '1';
|
| 2330 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2331 |
|
|
when x"FD" => --SBC, x abs 4th part.
|
| 2332 |
|
|
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8));
|
| 2333 |
|
|
flags_fg <= "01";
|
| 2334 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8));
|
| 2335 |
|
|
pc_inc_fg <= '1';
|
| 2336 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2337 |
|
|
when x"F9" => --SBC, Y abs 4th part.
|
| 2338 |
|
|
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8));
|
| 2339 |
|
|
flags_fg <= "01";
|
| 2340 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8));
|
| 2341 |
|
|
pc_inc_fg <= '1';
|
| 2342 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2343 |
|
|
|
| 2344 |
|
|
when x"AE" => --LDX abs 4th part.
|
| 2345 |
|
|
reg_x <= data_rd;
|
| 2346 |
|
|
flags_fg <= "01";
|
| 2347 |
|
|
dat_out2 <= data_rd;
|
| 2348 |
|
|
-- pc_inc_fg <= '1';
|
| 2349 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2350 |
|
|
when x"BE" => --LDX, y abs 4th part.
|
| 2351 |
|
|
reg_x <= data_rd;
|
| 2352 |
|
|
flags_fg <= "01";
|
| 2353 |
|
|
dat_out2 <= data_rd;
|
| 2354 |
|
|
-- pc_inc_fg <= '1';
|
| 2355 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2356 |
|
|
when x"AC" => --LDY abs 4th part.
|
| 2357 |
|
|
reg_y <= data_rd;
|
| 2358 |
|
|
flags_fg <= "01";
|
| 2359 |
|
|
dat_out2 <= data_rd;
|
| 2360 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2361 |
|
|
when x"BC" => --LDY, x abs 4th part.
|
| 2362 |
|
|
reg_y <= data_rd;
|
| 2363 |
|
|
flags_fg <= "01";
|
| 2364 |
|
|
dat_out2 <= data_rd;
|
| 2365 |
|
|
-- pc_inc_fg <= '1';
|
| 2366 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2367 |
|
|
|
| 2368 |
|
|
when x"2C" => --BIT abs 4th part.
|
| 2369 |
|
|
flags_fg <= "01";
|
| 2370 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 2371 |
|
|
pc_inc_fg <= '1';
|
| 2372 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2373 |
|
|
|
| 2374 |
|
|
when x"CD" => --CMP abs 4th part.
|
| 2375 |
|
|
flags_fg <= "01";
|
| 2376 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd;
|
| 2377 |
|
|
if reg_a(7 downto 0) > data_rd then
|
| 2378 |
|
|
reg_a(8) <= '1';
|
| 2379 |
|
|
else
|
| 2380 |
|
|
reg_a(8) <= '0';
|
| 2381 |
|
|
end if;
|
| 2382 |
|
|
pc_inc_fg <= '1';
|
| 2383 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2384 |
|
|
when x"DD" => --CMP, x abs 4th part.
|
| 2385 |
|
|
flags_fg <= "01";
|
| 2386 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd;
|
| 2387 |
|
|
if reg_a(7 downto 0) > data_rd then
|
| 2388 |
|
|
reg_a(8) <= '1';
|
| 2389 |
|
|
else
|
| 2390 |
|
|
reg_a(8) <= '0';
|
| 2391 |
|
|
end if;
|
| 2392 |
|
|
pc_inc_fg <= '1';
|
| 2393 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2394 |
|
|
when x"D9" => --CMP, Y abs 4th part.
|
| 2395 |
|
|
flags_fg <= "01";
|
| 2396 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd;
|
| 2397 |
|
|
if reg_a(7 downto 0) > data_rd then
|
| 2398 |
|
|
reg_a(8) <= '1';
|
| 2399 |
|
|
else
|
| 2400 |
|
|
reg_a(8) <= '0';
|
| 2401 |
|
|
end if;
|
| 2402 |
|
|
pc_inc_fg <= '1';
|
| 2403 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2404 |
|
|
when x"EC" => --CPX abs 4th part.
|
| 2405 |
|
|
if reg_x = data_rd then
|
| 2406 |
|
|
z_fg <= '1';
|
| 2407 |
|
|
else
|
| 2408 |
|
|
z_fg <= '0';
|
| 2409 |
|
|
end if;
|
| 2410 |
|
|
if reg_x >= data_rd then
|
| 2411 |
|
|
reg_a(8) <= '1';
|
| 2412 |
|
|
else
|
| 2413 |
|
|
reg_a(8) <= '0';
|
| 2414 |
|
|
end if;
|
| 2415 |
|
|
if reg_x < data_rd then
|
| 2416 |
|
|
n_fg <= '1';
|
| 2417 |
|
|
else
|
| 2418 |
|
|
n_fg <= '0';
|
| 2419 |
|
|
end if;
|
| 2420 |
|
|
pc_inc_fg <= '1';
|
| 2421 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2422 |
|
|
when x"CC" => --CPY abs 4th part.
|
| 2423 |
|
|
if reg_y = data_rd then
|
| 2424 |
|
|
z_fg <= '1';
|
| 2425 |
|
|
else
|
| 2426 |
|
|
z_fg <= '0';
|
| 2427 |
|
|
end if;
|
| 2428 |
|
|
if reg_y >= data_rd then
|
| 2429 |
|
|
reg_a(8) <= '1';
|
| 2430 |
|
|
else
|
| 2431 |
|
|
reg_a(8) <= '0';
|
| 2432 |
|
|
end if;
|
| 2433 |
|
|
if reg_y < data_rd then
|
| 2434 |
|
|
n_fg <= '1';
|
| 2435 |
|
|
else
|
| 2436 |
|
|
n_fg <= '0';
|
| 2437 |
|
|
end if;
|
| 2438 |
|
|
pc_inc_fg <= '1';
|
| 2439 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2440 |
|
|
-- .................................................................................
|
| 2441 |
|
|
when x"8D" => --STA abs 4th part.
|
| 2442 |
|
|
add_fg <= x"0";
|
| 2443 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2444 |
|
|
when x"9D" => --STA,x abs 4th part.
|
| 2445 |
|
|
add_fg <= x"0";
|
| 2446 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2447 |
|
|
when x"99" => --STA, y abs 4th part.
|
| 2448 |
|
|
add_fg <= x"0";
|
| 2449 |
|
|
pc_inc_fg <= '1';
|
| 2450 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2451 |
|
|
when x"8E" => --STX abs 4th part.
|
| 2452 |
|
|
add_fg <= x"0";
|
| 2453 |
|
|
pc_inc_fg <= '1';
|
| 2454 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2455 |
|
|
when x"8C" => --STY abs 4th part.
|
| 2456 |
|
|
add_fg <= x"0";
|
| 2457 |
|
|
pc_inc_fg <= '1';
|
| 2458 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2459 |
|
|
-- ........................................................................
|
| 2460 |
|
|
|
| 2461 |
|
|
when x"EE" => --INC abs 4th part.
|
| 2462 |
|
|
dat_out1 <= data_rd + x"01";
|
| 2463 |
|
|
dat_out2 <= data_rd + x"01";
|
| 2464 |
|
|
wr_ctr <= "01";
|
| 2465 |
|
|
flags_fg <= "01";
|
| 2466 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2467 |
|
|
when x"FE" => --INC, x abs 4th part.
|
| 2468 |
|
|
dat_out1 <= data_rd + x"01";
|
| 2469 |
|
|
dat_out2 <= data_rd + x"01";
|
| 2470 |
|
|
wr_ctr <= "01";
|
| 2471 |
|
|
flags_fg <= "01";
|
| 2472 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2473 |
|
|
when x"CE" => --DEC abs 4th part.
|
| 2474 |
|
|
dat_out1 <= data_rd - x"01";
|
| 2475 |
|
|
dat_out2 <= data_rd - x"01";
|
| 2476 |
|
|
wr_ctr <= "01";
|
| 2477 |
|
|
flags_fg <= "01";
|
| 2478 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2479 |
|
|
when x"DE" => --DEC, x abs 4th part.
|
| 2480 |
|
|
dat_out1 <= data_rd - x"01";
|
| 2481 |
|
|
dat_out2 <= data_rd - x"01";
|
| 2482 |
|
|
wr_ctr <= "01";
|
| 2483 |
|
|
flags_fg <= "01";
|
| 2484 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2485 |
|
|
|
| 2486 |
|
|
when x"2E" => --ROL abs 4th part.
|
| 2487 |
|
|
dat_out1(7 downto 1) <= data_rd(6 downto 0);
|
| 2488 |
|
|
dat_out1(0) <= reg_a(8);
|
| 2489 |
|
|
dat_out2(7 downto 1) <= data_rd(6 downto 0);
|
| 2490 |
|
|
dat_out2(0) <= reg_a(8);
|
| 2491 |
|
|
flags_fg <= "01";
|
| 2492 |
|
|
wr_ctr <= "01";
|
| 2493 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2494 |
|
|
when x"3E" => --ROL, x abs 4th part.
|
| 2495 |
|
|
dat_out1(7 downto 1) <= data_rd(6 downto 0);
|
| 2496 |
|
|
dat_out1(0) <= reg_a(8);
|
| 2497 |
|
|
dat_out2(7 downto 1) <= data_rd(6 downto 0);
|
| 2498 |
|
|
dat_out2(0) <= reg_a(8);
|
| 2499 |
|
|
flags_fg <= "01";
|
| 2500 |
|
|
wr_ctr <= "01";
|
| 2501 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2502 |
|
|
when x"6E" => --ROR abs 4th part.
|
| 2503 |
|
|
reg_a(8) <= data_rd(0);
|
| 2504 |
|
|
dat_out1 <= reg_a(8) & data_rd(7 downto 1);
|
| 2505 |
|
|
dat_out2 <= reg_a(8) & data_rd(7 downto 1);
|
| 2506 |
|
|
wr_ctr <= "01";
|
| 2507 |
|
|
flags_fg <= "01";
|
| 2508 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2509 |
|
|
when x"7E" => --ROR, x abs 4th part.
|
| 2510 |
|
|
reg_a(8) <= data_rd(0);
|
| 2511 |
|
|
dat_out1 <= reg_a(8) & data_rd(7 downto 1);
|
| 2512 |
|
|
dat_out2 <= reg_a(8) & data_rd(7 downto 1);
|
| 2513 |
|
|
wr_ctr <= "01";
|
| 2514 |
|
|
flags_fg <= "01";
|
| 2515 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2516 |
|
|
when x"4E" => --LSR abs 4th part.
|
| 2517 |
|
|
dat_out1 <= '0' & reg_a(7 downto 1);
|
| 2518 |
|
|
dat_out2 <= '0' & reg_a(7 downto 1);
|
| 2519 |
|
|
reg_a(8) <= data_rd(0);
|
| 2520 |
|
|
wr_ctr <= "01";
|
| 2521 |
|
|
flags_fg <= "01";
|
| 2522 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2523 |
|
|
when x"5E" => --LSR, x abs 4th part.
|
| 2524 |
|
|
dat_out1 <= '0' & reg_a(7 downto 1);
|
| 2525 |
|
|
dat_out2 <= '0' & reg_a(7 downto 1);
|
| 2526 |
|
|
reg_a(8) <= data_rd(0);
|
| 2527 |
|
|
wr_ctr <= "01";
|
| 2528 |
|
|
flags_fg <= "01";
|
| 2529 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2530 |
|
|
when x"0E" => --ASL abs 4th part.
|
| 2531 |
|
|
reg_a(8) <= data_rd(7);
|
| 2532 |
|
|
dat_out1 <= data_rd(6 downto 0) & data_rd(0);
|
| 2533 |
|
|
dat_out2 <= data_rd(6 downto 0) & data_rd(0);
|
| 2534 |
|
|
wr_ctr <= "01";
|
| 2535 |
|
|
flags_fg <= "01";
|
| 2536 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2537 |
|
|
when x"1E" => --ASL, x abs 4th part.
|
| 2538 |
|
|
reg_a(8) <= data_rd(7);
|
| 2539 |
|
|
dat_out1 <= data_rd(6 downto 0) & data_rd(0);
|
| 2540 |
|
|
dat_out2 <= data_rd(6 downto 0) & data_rd(0);
|
| 2541 |
|
|
wr_ctr <= "01";
|
| 2542 |
|
|
flags_fg <= "01";
|
| 2543 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2544 |
|
|
-- ............................................................................
|
| 2545 |
|
|
-- ==============================================================================
|
| 2546 |
|
|
when x"A1" => --LDA (zero,x) 4th part proto
|
| 2547 |
|
|
add_fg <= x"0";
|
| 2548 |
|
|
pc_inc_fg <= '1';
|
| 2549 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2550 |
|
|
|
| 2551 |
|
|
when x"B1" => --LDA (zero),y 4th part proto
|
| 2552 |
|
|
add_fg <= x"0";
|
| 2553 |
|
|
pc_inc_fg <= '1';
|
| 2554 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2555 |
|
|
|
| 2556 |
|
|
when x"21" => --AND (zero,x) 4th part proto
|
| 2557 |
|
|
add_fg <= x"0";
|
| 2558 |
|
|
pc_inc_fg <= '1';
|
| 2559 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2560 |
|
|
|
| 2561 |
|
|
when x"31" => --AND (zero),y 4th part proto
|
| 2562 |
|
|
add_fg <= x"0";
|
| 2563 |
|
|
pc_inc_fg <= '1';
|
| 2564 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2565 |
|
|
|
| 2566 |
|
|
when x"41" => --EOR (zero,x) 4th part proto
|
| 2567 |
|
|
add_fg <= x"0";
|
| 2568 |
|
|
pc_inc_fg <= '1';
|
| 2569 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2570 |
|
|
|
| 2571 |
|
|
when x"51" => --EOR (zero),y 4th part proto
|
| 2572 |
|
|
add_fg <= x"0";
|
| 2573 |
|
|
pc_inc_fg <= '1';
|
| 2574 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2575 |
|
|
|
| 2576 |
|
|
when x"01" => --OR (zero,x) 4th part proto
|
| 2577 |
|
|
add_fg <= x"0";
|
| 2578 |
|
|
pc_inc_fg <= '1';
|
| 2579 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2580 |
|
|
|
| 2581 |
|
|
when x"11" => --OR (zero),y 4th part proto
|
| 2582 |
|
|
add_fg <= x"0";
|
| 2583 |
|
|
pc_inc_fg <= '1';
|
| 2584 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2585 |
|
|
|
| 2586 |
|
|
|
| 2587 |
|
|
when x"61" => --ADC (zero,x) 4th part proto
|
| 2588 |
|
|
add_fg <= x"0";
|
| 2589 |
|
|
pc_inc_fg <= '1';
|
| 2590 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2591 |
|
|
|
| 2592 |
|
|
when x"71" => --ADC (zero),y 4th part proto
|
| 2593 |
|
|
add_fg <= x"0";
|
| 2594 |
|
|
pc_inc_fg <= '1';
|
| 2595 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2596 |
|
|
|
| 2597 |
|
|
when x"E1" => --SBC (zero,x) 4th part proto
|
| 2598 |
|
|
add_fg <= x"0";
|
| 2599 |
|
|
pc_inc_fg <= '1';
|
| 2600 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2601 |
|
|
|
| 2602 |
|
|
when x"F1" => --SBC (zero),y 4th part proto
|
| 2603 |
|
|
add_fg <= x"0";
|
| 2604 |
|
|
pc_inc_fg <= '1';
|
| 2605 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2606 |
|
|
|
| 2607 |
|
|
when x"C1" => --CMP (zero,x) 4th part proto
|
| 2608 |
|
|
add_fg <= x"0";
|
| 2609 |
|
|
pc_inc_fg <= '1';
|
| 2610 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2611 |
|
|
|
| 2612 |
|
|
when x"D1" => --CMP (zero),y 4th part proto
|
| 2613 |
|
|
add_fg <= x"0";
|
| 2614 |
|
|
pc_inc_fg <= '1';
|
| 2615 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2616 |
|
|
|
| 2617 |
|
|
|
| 2618 |
|
|
when x"81" => --STA (zero,x) 4th part proto
|
| 2619 |
|
|
-- add_fg <= x"0";
|
| 2620 |
|
|
-- pc_inc_fg <= '1';
|
| 2621 |
|
|
wr_ctr <= "00";
|
| 2622 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2623 |
|
|
when x"91" => --STA (zero),y 4th part proto
|
| 2624 |
|
|
-- add_fg <= x"0";
|
| 2625 |
|
|
-- pc_inc_fg <= '1';
|
| 2626 |
|
|
wr_ctr <= "00";
|
| 2627 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 2628 |
|
|
-- ==================================================================================
|
| 2629 |
|
|
|
| 2630 |
|
|
when x"4C" => --JMP abs 4th part
|
| 2631 |
|
|
pc_inc_fg <= '1';
|
| 2632 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2633 |
|
|
when x"6C" => --JMP abs 4th part
|
| 2634 |
|
|
add_fg <= x"0";
|
| 2635 |
|
|
dat2pc_fg <= '1';
|
| 2636 |
|
|
pc_inc_fg <= '0';
|
| 2637 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2638 |
|
|
when x"20" => --JSR indirect 4th part
|
| 2639 |
|
|
-- add_fg <= x"0";
|
| 2640 |
|
|
wr_ctr <= "00";
|
| 2641 |
|
|
reg_sp <= reg_sp + "1";
|
| 2642 |
|
|
-- pc_inc_fg <= '1';
|
| 2643 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2644 |
|
|
when x"60" => --RTS fourth part
|
| 2645 |
|
|
dat2pc_fg <= '0';
|
| 2646 |
|
|
pc_inc_fg <= '1';
|
| 2647 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2648 |
|
|
|
| 2649 |
|
|
when x"40" => --RTI forth part
|
| 2650 |
|
|
-- reg_sp <= reg_sp - "1";
|
| 2651 |
|
|
add_fg <= x"7"; --Get 2nd PC byte
|
| 2652 |
|
|
dat2pc_fg <= '0';
|
| 2653 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2654 |
|
|
|
| 2655 |
|
|
when x"00" => --Break forth extra part cyc 3
|
| 2656 |
|
|
dat_out1 <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8);
|
| 2657 |
|
|
reg_sp <= reg_sp + "1";
|
| 2658 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2659 |
|
|
|
| 2660 |
|
|
--------------------------------------------------------------------------------------
|
| 2661 |
|
|
when others =>
|
| 2662 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2663 |
|
|
|
| 2664 |
|
|
end case; --Cycle 3
|
| 2665 |
|
|
end if; --End single byte stuff
|
| 2666 |
|
|
|
| 2667 |
|
|
-- End of cycle 3
|
| 2668 |
|
|
-- Cycle 4 is for 2 byte/cycle instructions ie LDA #
|
| 2669 |
|
|
--
|
| 2670 |
|
|
when x"4" =>
|
| 2671 |
|
|
case Instruction_in is
|
| 2672 |
|
|
-- ======================================================================================
|
| 2673 |
|
|
when x"F0" => --BEQ branch true 5th part.
|
| 2674 |
|
|
pc_inc_fg <= '0';
|
| 2675 |
|
|
cycle_ctr <= x"0";
|
| 2676 |
|
|
when x"D0" => --BNE branch true 5th part.
|
| 2677 |
|
|
pc_inc_fg <= '0';
|
| 2678 |
|
|
cycle_ctr <= x"0";
|
| 2679 |
|
|
when x"10" => --BPL plus true 5th part.
|
| 2680 |
|
|
pc_inc_fg <= '0';
|
| 2681 |
|
|
cycle_ctr <= x"0";
|
| 2682 |
|
|
when x"30" => --BM1 negative true 5th part.
|
| 2683 |
|
|
pc_inc_fg <= '0';
|
| 2684 |
|
|
cycle_ctr <= x"0";
|
| 2685 |
|
|
when x"50" => --BVC overflow false 5th part.
|
| 2686 |
|
|
pc_inc_fg <= '0';
|
| 2687 |
|
|
cycle_ctr <= x"0";
|
| 2688 |
|
|
when x"70" => --BVS overflow true 5th part.
|
| 2689 |
|
|
pc_inc_fg <= '0';
|
| 2690 |
|
|
cycle_ctr <= x"0";
|
| 2691 |
|
|
when x"90" => --BCC carry false 5th part.
|
| 2692 |
|
|
pc_inc_fg <= '0';
|
| 2693 |
|
|
cycle_ctr <= x"0";
|
| 2694 |
|
|
when x"B0" => --BCS carry true 5th part.
|
| 2695 |
|
|
pc_inc_fg <= '0';
|
| 2696 |
|
|
cycle_ctr <= x"0";
|
| 2697 |
|
|
-- ======================================================================================
|
| 2698 |
|
|
|
| 2699 |
|
|
when x"E6" => --INC zero 5th part
|
| 2700 |
|
|
pc_inc_fg <= '1';
|
| 2701 |
|
|
add_fg <= x"0";
|
| 2702 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2703 |
|
|
|
| 2704 |
|
|
when x"F6" => --INC zero,X 5th part
|
| 2705 |
|
|
wr_ctr <= "00";
|
| 2706 |
|
|
pc_inc_fg <= '0';
|
| 2707 |
|
|
add_fg <= x"0";
|
| 2708 |
|
|
cycle_ctr <= x"0";
|
| 2709 |
|
|
when x"c6" => --DEC zero 5th part
|
| 2710 |
|
|
pc_inc_fg <= '1';
|
| 2711 |
|
|
add_fg <= x"0";
|
| 2712 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2713 |
|
|
|
| 2714 |
|
|
when x"46" => --LSR zero 5th part
|
| 2715 |
|
|
pc_inc_fg <= '1';
|
| 2716 |
|
|
add_fg <= x"0";
|
| 2717 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2718 |
|
|
when x"56" => --LSR zero,X 5th part
|
| 2719 |
|
|
pc_inc_fg <= '1';
|
| 2720 |
|
|
add_fg <= x"0";
|
| 2721 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2722 |
|
|
|
| 2723 |
|
|
when x"66" => --ROR zero 5th part
|
| 2724 |
|
|
pc_inc_fg <= '1';
|
| 2725 |
|
|
add_fg <= x"0";
|
| 2726 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2727 |
|
|
when x"76" => --ROR zero,X 5th part
|
| 2728 |
|
|
pc_inc_fg <= '1';
|
| 2729 |
|
|
add_fg <= x"0";
|
| 2730 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2731 |
|
|
when x"26" => --ROL zero 5th part
|
| 2732 |
|
|
pc_inc_fg <= '1';
|
| 2733 |
|
|
add_fg <= x"0";
|
| 2734 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2735 |
|
|
when x"36" => --ROL zero,X 5th part
|
| 2736 |
|
|
pc_inc_fg <= '1';
|
| 2737 |
|
|
add_fg <= x"0";
|
| 2738 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2739 |
|
|
when x"06" => --ASL zero 5th part
|
| 2740 |
|
|
pc_inc_fg <= '1';
|
| 2741 |
|
|
add_fg <= x"0";
|
| 2742 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2743 |
|
|
when x"16" => --ASL zero,X 5th part
|
| 2744 |
|
|
pc_inc_fg <= '1';
|
| 2745 |
|
|
add_fg <= x"0";
|
| 2746 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2747 |
|
|
|
| 2748 |
|
|
|
| 2749 |
|
|
--
|
| 2750 |
|
|
-- ======================================================================================
|
| 2751 |
|
|
when x"AD" => --LDA 5th part.
|
| 2752 |
|
|
pc_inc_fg <= '0';
|
| 2753 |
|
|
cycle_ctr <= x"0";
|
| 2754 |
|
|
when x"BD" => --LDA, x 5th part.
|
| 2755 |
|
|
pc_inc_fg <= '0';
|
| 2756 |
|
|
cycle_ctr <= x"0";
|
| 2757 |
|
|
when x"B9" => --LDA, Y 5th part
|
| 2758 |
|
|
pc_inc_fg <= '0';
|
| 2759 |
|
|
cycle_ctr <= x"0";
|
| 2760 |
|
|
|
| 2761 |
|
|
when x"2D" => --AND 5th part.
|
| 2762 |
|
|
pc_inc_fg <= '0';
|
| 2763 |
|
|
cycle_ctr <= x"0";
|
| 2764 |
|
|
when x"3D" => --AND, x 5th part.
|
| 2765 |
|
|
pc_inc_fg <= '0';
|
| 2766 |
|
|
cycle_ctr <= x"0";
|
| 2767 |
|
|
when x"39" => --AND, Y 5th part.
|
| 2768 |
|
|
pc_inc_fg <= '0';
|
| 2769 |
|
|
cycle_ctr <= x"0";
|
| 2770 |
|
|
|
| 2771 |
|
|
when x"0D" => --ORA 5th part.
|
| 2772 |
|
|
pc_inc_fg <= '0';
|
| 2773 |
|
|
cycle_ctr <= x"0";
|
| 2774 |
|
|
when x"1D" => --ORA, x 5th part.
|
| 2775 |
|
|
pc_inc_fg <= '0';
|
| 2776 |
|
|
cycle_ctr <= x"0";
|
| 2777 |
|
|
when x"19" => --ORA, Y 5th part.
|
| 2778 |
|
|
pc_inc_fg <= '0';
|
| 2779 |
|
|
cycle_ctr <= x"0";
|
| 2780 |
|
|
|
| 2781 |
|
|
when x"4D" => --EOR 5th part.
|
| 2782 |
|
|
pc_inc_fg <= '0';
|
| 2783 |
|
|
cycle_ctr <= x"0";
|
| 2784 |
|
|
when x"5D" => --EOR, x 5th part.
|
| 2785 |
|
|
pc_inc_fg <= '0';
|
| 2786 |
|
|
cycle_ctr <= x"0";
|
| 2787 |
|
|
when x"59" => --EOR, Y 5th part.
|
| 2788 |
|
|
pc_inc_fg <= '0';
|
| 2789 |
|
|
cycle_ctr <= x"0";
|
| 2790 |
|
|
|
| 2791 |
|
|
when x"6D" => --ADC 5th part.
|
| 2792 |
|
|
pc_inc_fg <= '0';
|
| 2793 |
|
|
cycle_ctr <= x"0";
|
| 2794 |
|
|
when x"7D" => --ADC, x 5th part.
|
| 2795 |
|
|
pc_inc_fg <= '0';
|
| 2796 |
|
|
cycle_ctr <= x"0";
|
| 2797 |
|
|
when x"79" => --ADC, Y 5th part.
|
| 2798 |
|
|
pc_inc_fg <= '0';
|
| 2799 |
|
|
cycle_ctr <= x"0";
|
| 2800 |
|
|
|
| 2801 |
|
|
when x"ED" => --SBC 5th part.
|
| 2802 |
|
|
pc_inc_fg <= '0';
|
| 2803 |
|
|
cycle_ctr <= x"0";
|
| 2804 |
|
|
when x"FD" => --SBC, x 5th part.
|
| 2805 |
|
|
pc_inc_fg <= '0';
|
| 2806 |
|
|
cycle_ctr <= x"0";
|
| 2807 |
|
|
when x"F9" => --SBC, Y 5th part.
|
| 2808 |
|
|
pc_inc_fg <= '0';
|
| 2809 |
|
|
cycle_ctr <= x"0";
|
| 2810 |
|
|
|
| 2811 |
|
|
when x"AE" => --LDX 5th part.
|
| 2812 |
|
|
pc_inc_fg <= '0';
|
| 2813 |
|
|
cycle_ctr <= x"0";
|
| 2814 |
|
|
when x"BE" => --LDX, y 5th part.
|
| 2815 |
|
|
pc_inc_fg <= '0';
|
| 2816 |
|
|
cycle_ctr <= x"0";
|
| 2817 |
|
|
when x"AC" => --LDY 5th part.
|
| 2818 |
|
|
pc_inc_fg <= '0';
|
| 2819 |
|
|
cycle_ctr <= x"0";
|
| 2820 |
|
|
when x"BC" => --LDY, x 5th part.
|
| 2821 |
|
|
pc_inc_fg <= '0';
|
| 2822 |
|
|
cycle_ctr <= x"0";
|
| 2823 |
|
|
|
| 2824 |
|
|
when x"2C" => --BIT 5th part.
|
| 2825 |
|
|
pc_inc_fg <= '0';
|
| 2826 |
|
|
cycle_ctr <= x"0";
|
| 2827 |
|
|
|
| 2828 |
|
|
when x"CD" => --CMP 5th part.
|
| 2829 |
|
|
wr_ctr <= "10"; pc_inc_fg <= '0';
|
| 2830 |
|
|
cycle_ctr <= x"0";
|
| 2831 |
|
|
when x"DD" => --CMP, x 5th part.
|
| 2832 |
|
|
pc_inc_fg <= '0';
|
| 2833 |
|
|
cycle_ctr <= x"0";
|
| 2834 |
|
|
when x"D9" => --CMP, Y 5th part.
|
| 2835 |
|
|
pc_inc_fg <= '0';
|
| 2836 |
|
|
cycle_ctr <= x"0";
|
| 2837 |
|
|
when x"EC" => --CPX 5th part.
|
| 2838 |
|
|
pc_inc_fg <= '0';
|
| 2839 |
|
|
cycle_ctr <= x"0";
|
| 2840 |
|
|
when x"CC" => --CPY 5th part.
|
| 2841 |
|
|
pc_inc_fg <= '0';
|
| 2842 |
|
|
cycle_ctr <= x"0";
|
| 2843 |
|
|
-- ............................................................................
|
| 2844 |
|
|
when x"8D" => --STA 5th part.
|
| 2845 |
|
|
pc_inc_fg <= '0';
|
| 2846 |
|
|
cycle_ctr <= x"0";
|
| 2847 |
|
|
when x"9D" => --STA,x 5th part.
|
| 2848 |
|
|
pc_inc_fg <= '0';
|
| 2849 |
|
|
cycle_ctr <= x"0";
|
| 2850 |
|
|
when x"99" => --STA, y 5th part.
|
| 2851 |
|
|
pc_inc_fg <= '0';
|
| 2852 |
|
|
cycle_ctr <= x"0";
|
| 2853 |
|
|
when x"8E" => --STX 5th part.
|
| 2854 |
|
|
pc_inc_fg <= '0';
|
| 2855 |
|
|
cycle_ctr <= x"0";
|
| 2856 |
|
|
when x"8C" => --STY 5th part.
|
| 2857 |
|
|
pc_inc_fg <= '0';
|
| 2858 |
|
|
cycle_ctr <= x"0";
|
| 2859 |
|
|
-- ............................................................................
|
| 2860 |
|
|
|
| 2861 |
|
|
when x"EE" => --INC abs 5th part.
|
| 2862 |
|
|
wr_ctr <= "00";
|
| 2863 |
|
|
pc_inc_fg <= '1';
|
| 2864 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2865 |
|
|
|
| 2866 |
|
|
when x"FE" => --INC, x 5th part.
|
| 2867 |
|
|
wr_ctr <= "00";
|
| 2868 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2869 |
|
|
when x"CE" => --DEC 5th part.
|
| 2870 |
|
|
wr_ctr <= "00";
|
| 2871 |
|
|
pc_inc_fg <= '1';
|
| 2872 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2873 |
|
|
when x"DE" => --DEC, x 5th part.
|
| 2874 |
|
|
wr_ctr <= "00";
|
| 2875 |
|
|
pc_inc_fg <= '1';
|
| 2876 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2877 |
|
|
|
| 2878 |
|
|
when x"2E" => --ROL 5th part.
|
| 2879 |
|
|
wr_ctr <= "00";
|
| 2880 |
|
|
pc_inc_fg <= '1';
|
| 2881 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2882 |
|
|
when x"3E" => --ROL, x 5th part.
|
| 2883 |
|
|
wr_ctr <= "00";
|
| 2884 |
|
|
pc_inc_fg <= '1';
|
| 2885 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2886 |
|
|
when x"6E" => --ROR 5th part.
|
| 2887 |
|
|
wr_ctr <= "00";
|
| 2888 |
|
|
pc_inc_fg <= '1';
|
| 2889 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2890 |
|
|
when x"7E" => --ROR, x 5th part.
|
| 2891 |
|
|
wr_ctr <= "00";
|
| 2892 |
|
|
pc_inc_fg <= '1';
|
| 2893 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2894 |
|
|
when x"4E" => --LSR 5th part.
|
| 2895 |
|
|
wr_ctr <= "00";
|
| 2896 |
|
|
pc_inc_fg <= '1';
|
| 2897 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2898 |
|
|
when x"5E" => --LSR, x 5th part.
|
| 2899 |
|
|
wr_ctr <= "00";
|
| 2900 |
|
|
pc_inc_fg <= '1';
|
| 2901 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2902 |
|
|
when x"0E" => --ASL 5th part.
|
| 2903 |
|
|
wr_ctr <= "00";
|
| 2904 |
|
|
pc_inc_fg <= '1';
|
| 2905 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2906 |
|
|
when x"1E" => --ASL, x 5th part.
|
| 2907 |
|
|
wr_ctr <= "00";
|
| 2908 |
|
|
pc_inc_fg <= '1';
|
| 2909 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 2910 |
|
|
-- ............................................................................
|
| 2911 |
|
|
-- ==============================================================================
|
| 2912 |
|
|
when x"A1" => --LDA (zero,x) 5th part proto
|
| 2913 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 2914 |
|
|
flags_fg <= "01";
|
| 2915 |
|
|
dat_out2 <= data_rd;
|
| 2916 |
|
|
pc_inc_fg <= '0';
|
| 2917 |
|
|
cycle_ctr <= x"0";
|
| 2918 |
|
|
when x"B1" => --LDA (zero),y 5th part proto
|
| 2919 |
|
|
reg_a(7 downto 0) <= data_rd;
|
| 2920 |
|
|
flags_fg <= "01";
|
| 2921 |
|
|
dat_out2 <= data_rd;
|
| 2922 |
|
|
pc_inc_fg <= '0';
|
| 2923 |
|
|
cycle_ctr <= x"0";
|
| 2924 |
|
|
|
| 2925 |
|
|
when x"21" => --AND (zero,x) 5th part proto
|
| 2926 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd;
|
| 2927 |
|
|
flags_fg <= "01";
|
| 2928 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 2929 |
|
|
pc_inc_fg <= '0';
|
| 2930 |
|
|
cycle_ctr <= x"0";
|
| 2931 |
|
|
when x"31" => --AND (zero),y 5th part proto
|
| 2932 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) and data_rd;
|
| 2933 |
|
|
flags_fg <= "01";
|
| 2934 |
|
|
dat_out2 <= reg_a(7 downto 0) and data_rd;
|
| 2935 |
|
|
pc_inc_fg <= '0';
|
| 2936 |
|
|
cycle_ctr <= x"0";
|
| 2937 |
|
|
|
| 2938 |
|
|
when x"42" => --EOR (zero,x) 5th part proto
|
| 2939 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd;
|
| 2940 |
|
|
flags_fg <= "01";
|
| 2941 |
|
|
dat_out2 <= reg_a(7 downto 0) xor data_rd;
|
| 2942 |
|
|
pc_inc_fg <= '0';
|
| 2943 |
|
|
cycle_ctr <= x"0";
|
| 2944 |
|
|
when x"51" => --EOR (zero),y 5th part proto
|
| 2945 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) xor data_rd;
|
| 2946 |
|
|
flags_fg <= "01";
|
| 2947 |
|
|
dat_out2 <= reg_a(7 downto 0) xor data_rd;
|
| 2948 |
|
|
pc_inc_fg <= '0';
|
| 2949 |
|
|
cycle_ctr <= x"0";
|
| 2950 |
|
|
|
| 2951 |
|
|
when x"01" => --OR (zero,x) 5th part proto
|
| 2952 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd;
|
| 2953 |
|
|
flags_fg <= "01";
|
| 2954 |
|
|
dat_out2 <= reg_a(7 downto 0) or data_rd;
|
| 2955 |
|
|
pc_inc_fg <= '0';
|
| 2956 |
|
|
cycle_ctr <= x"0";
|
| 2957 |
|
|
when x"11" => --OR (zero),y 5th part proto
|
| 2958 |
|
|
reg_a(7 downto 0) <= reg_a(7 downto 0) or data_rd;
|
| 2959 |
|
|
flags_fg <= "01";
|
| 2960 |
|
|
dat_out2 <= reg_a(7 downto 0) or data_rd;
|
| 2961 |
|
|
pc_inc_fg <= '0';
|
| 2962 |
|
|
cycle_ctr <= x"0";
|
| 2963 |
|
|
|
| 2964 |
|
|
when x"61" => --ADC (zero,x) 5th part proto
|
| 2965 |
|
|
flags_fg <= "01";
|
| 2966 |
|
|
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8));
|
| 2967 |
|
|
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8));
|
| 2968 |
|
|
pc_inc_fg <= '0';
|
| 2969 |
|
|
cycle_ctr <= x"0";
|
| 2970 |
|
|
|
| 2971 |
|
|
when x"71" => --ADC (zero),y 5th part proto
|
| 2972 |
|
|
flags_fg <= "01";
|
| 2973 |
|
|
reg_a <= reg_a + ("0" & data_rd) + ("00000000" & reg_a(8));
|
| 2974 |
|
|
dat_out2 <= reg_a(7 downto 0) + data_rd + ("0000000" & reg_a(8));
|
| 2975 |
|
|
pc_inc_fg <= '0';
|
| 2976 |
|
|
cycle_ctr <= x"0";
|
| 2977 |
|
|
|
| 2978 |
|
|
when x"E1" => --SBC (zero,x) 5th part proto
|
| 2979 |
|
|
flags_fg <= "01";
|
| 2980 |
|
|
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8));
|
| 2981 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8));
|
| 2982 |
|
|
pc_inc_fg <= '0';
|
| 2983 |
|
|
cycle_ctr <= x"0";
|
| 2984 |
|
|
|
| 2985 |
|
|
when x"F1" => --SBC (zero),y 5th part proto
|
| 2986 |
|
|
flags_fg <= "01";
|
| 2987 |
|
|
reg_a <= reg_a - ("0" & data_rd) - ("00000000" & reg_a(8));
|
| 2988 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd - ("0000000" & reg_a(8));
|
| 2989 |
|
|
pc_inc_fg <= '0';
|
| 2990 |
|
|
cycle_ctr <= x"0";
|
| 2991 |
|
|
when x"C1" => --CMP (zero,x) 5th part proto
|
| 2992 |
|
|
flags_fg <= "01";
|
| 2993 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd;
|
| 2994 |
|
|
if reg_a(7 downto 0) > data_rd then
|
| 2995 |
|
|
reg_a(8) <= '1';
|
| 2996 |
|
|
else
|
| 2997 |
|
|
reg_a(8) <= '0';
|
| 2998 |
|
|
end if;
|
| 2999 |
|
|
pc_inc_fg <= '0';
|
| 3000 |
|
|
cycle_ctr <= x"0";
|
| 3001 |
|
|
|
| 3002 |
|
|
when x"D1" => --CMP (zero),y 5th part proto
|
| 3003 |
|
|
flags_fg <= "01";
|
| 3004 |
|
|
dat_out2 <= reg_a(7 downto 0) - data_rd;
|
| 3005 |
|
|
if reg_a(7 downto 0) > data_rd then
|
| 3006 |
|
|
reg_a(8) <= '1';
|
| 3007 |
|
|
else
|
| 3008 |
|
|
reg_a(8) <= '0';
|
| 3009 |
|
|
end if;
|
| 3010 |
|
|
pc_inc_fg <= '0';
|
| 3011 |
|
|
cycle_ctr <= x"0";
|
| 3012 |
|
|
|
| 3013 |
|
|
when x"81" => --STA (zero,x) 5th part proto
|
| 3014 |
|
|
pc_inc_fg <= '1';
|
| 3015 |
|
|
add_fg <= x"0";
|
| 3016 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3017 |
|
|
when x"91" => --STA (zero),y 5th part proto
|
| 3018 |
|
|
pc_inc_fg <= '1';
|
| 3019 |
|
|
add_fg <= x"0";
|
| 3020 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3021 |
|
|
-- ==============================================================================
|
| 3022 |
|
|
when x"4C" => --JMP abs 5th part
|
| 3023 |
|
|
pc_inc_fg <= '0';
|
| 3024 |
|
|
cycle_ctr <= x"0";
|
| 3025 |
|
|
when x"6C" => --JMP indirect 5th part
|
| 3026 |
|
|
pc_inc_fg <= '1';
|
| 3027 |
|
|
dat2pc_fg <= '0';
|
| 3028 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3029 |
|
|
when x"20" => --JSR 5th part
|
| 3030 |
|
|
pc_inc_fg <= '1';
|
| 3031 |
|
|
add_fg <= x"0";
|
| 3032 |
|
|
reg_sp <= reg_sp + "1";
|
| 3033 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3034 |
|
|
when x"60" => --RTS fifth part
|
| 3035 |
|
|
dat2pc_fg <= '0';
|
| 3036 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3037 |
|
|
|
| 3038 |
|
|
when x"40" => --RTI fifth part
|
| 3039 |
|
|
-- reg_sp <= reg_sp + "1";
|
| 3040 |
|
|
add_fg <= x"0";
|
| 3041 |
|
|
-- dat2pc_fg <= '0';
|
| 3042 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3043 |
|
|
|
| 3044 |
|
|
when x"00" => --Break fifth part cyc 4
|
| 3045 |
|
|
wr_ctr <= "00";
|
| 3046 |
|
|
reg_sp <= reg_sp + "1";
|
| 3047 |
|
|
if nmi_fg = '0' then
|
| 3048 |
|
|
add_fg <= x"9"; --Complete stacking start getting vector
|
| 3049 |
|
|
else
|
| 3050 |
|
|
add_fg <= x"A";
|
| 3051 |
|
|
end if;
|
| 3052 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3053 |
|
|
|
| 3054 |
|
|
|
| 3055 |
|
|
when others =>
|
| 3056 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3057 |
|
|
|
| 3058 |
|
|
end case; --Cycle 4
|
| 3059 |
|
|
-- end if;
|
| 3060 |
|
|
------------------------------------------------------------------------
|
| 3061 |
|
|
-- End of cycle 4
|
| 3062 |
|
|
-- Cycle 5 is for 3 byte instructions ie LDA abs
|
| 3063 |
|
|
|
| 3064 |
|
|
when x"5" =>
|
| 3065 |
|
|
case Instruction_in is
|
| 3066 |
|
|
-- =========================================================================
|
| 3067 |
|
|
when x"81" => --STA (zero,x) 6th part proto
|
| 3068 |
|
|
pc_inc_fg <= '0';
|
| 3069 |
|
|
cycle_ctr <= x"0";
|
| 3070 |
|
|
when x"91" => --STA (zero),y 6th part proto
|
| 3071 |
|
|
pc_inc_fg <= '0';
|
| 3072 |
|
|
cycle_ctr <= x"0";
|
| 3073 |
|
|
|
| 3074 |
|
|
|
| 3075 |
|
|
-- ........................................................................................
|
| 3076 |
|
|
when x"E6" => --INC zero 6th part
|
| 3077 |
|
|
pc_inc_fg <= '0';
|
| 3078 |
|
|
cycle_ctr <= x"0";
|
| 3079 |
|
|
when x"c6" => --dec zero 6th part
|
| 3080 |
|
|
pc_inc_fg <= '0';
|
| 3081 |
|
|
cycle_ctr <= x"0";
|
| 3082 |
|
|
when x"26" => --ROL zero 6th part
|
| 3083 |
|
|
pc_inc_fg <= '0';
|
| 3084 |
|
|
cycle_ctr <= x"0";
|
| 3085 |
|
|
|
| 3086 |
|
|
when x"F6" => --INC zero,X 6th part
|
| 3087 |
|
|
pc_inc_fg <= '0';
|
| 3088 |
|
|
cycle_ctr <= x"0";
|
| 3089 |
|
|
when x"46" => --LSR zero 6th part
|
| 3090 |
|
|
pc_inc_fg <= '0';
|
| 3091 |
|
|
cycle_ctr <= x"0";
|
| 3092 |
|
|
when x"56" => --LSR zero,X 6th part
|
| 3093 |
|
|
pc_inc_fg <= '0';
|
| 3094 |
|
|
cycle_ctr <= x"0";
|
| 3095 |
|
|
|
| 3096 |
|
|
when x"66" => --ROR zero 6th part
|
| 3097 |
|
|
pc_inc_fg <= '0';
|
| 3098 |
|
|
cycle_ctr <= x"0";
|
| 3099 |
|
|
when x"76" => --ROR zero,X 6th part
|
| 3100 |
|
|
pc_inc_fg <= '0';
|
| 3101 |
|
|
cycle_ctr <= x"0";
|
| 3102 |
|
|
|
| 3103 |
|
|
when x"36" => --ROL zero,X 6th part
|
| 3104 |
|
|
pc_inc_fg <= '0';
|
| 3105 |
|
|
cycle_ctr <= x"0";
|
| 3106 |
|
|
when x"06" => --ASL zero 6th part
|
| 3107 |
|
|
pc_inc_fg <= '0';
|
| 3108 |
|
|
cycle_ctr <= x"0";
|
| 3109 |
|
|
when x"16" => --ASL zero,X 6th part
|
| 3110 |
|
|
pc_inc_fg <= '0';
|
| 3111 |
|
|
cycle_ctr <= x"0";
|
| 3112 |
|
|
|
| 3113 |
|
|
|
| 3114 |
|
|
--==================================================
|
| 3115 |
|
|
|
| 3116 |
|
|
|
| 3117 |
|
|
when x"EE" => --INC abs 6th part.
|
| 3118 |
|
|
add_fg <= x"0";
|
| 3119 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3120 |
|
|
|
| 3121 |
|
|
when x"FE" => --INC, x 6th part.
|
| 3122 |
|
|
add_fg <= x"0";
|
| 3123 |
|
|
cycle_ctr <= x"0";
|
| 3124 |
|
|
when x"CE" => --DEC 6th part.
|
| 3125 |
|
|
add_fg <= x"0";
|
| 3126 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3127 |
|
|
when x"DE" => --DEC, x 6th part.
|
| 3128 |
|
|
add_fg <= x"0";
|
| 3129 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3130 |
|
|
|
| 3131 |
|
|
when x"2E" => --ROL 6th part.
|
| 3132 |
|
|
add_fg <= x"0";
|
| 3133 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3134 |
|
|
when x"3E" => --ROL, x 6th part.
|
| 3135 |
|
|
add_fg <= x"0";
|
| 3136 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3137 |
|
|
when x"6E" => --ROR 6th part.
|
| 3138 |
|
|
add_fg <= x"0";
|
| 3139 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3140 |
|
|
when x"7E" => --ROR, x 6th part.
|
| 3141 |
|
|
add_fg <= x"0";
|
| 3142 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3143 |
|
|
when x"4E" => --LSR 6th part.
|
| 3144 |
|
|
add_fg <= x"0";
|
| 3145 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3146 |
|
|
when x"5E" => --LSR, x 6th part.
|
| 3147 |
|
|
add_fg <= x"0";
|
| 3148 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3149 |
|
|
when x"0E" => --ASL 6th part.
|
| 3150 |
|
|
add_fg <= x"0";
|
| 3151 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3152 |
|
|
when x"1E" => --ASL, x 6th part.
|
| 3153 |
|
|
add_fg <= x"0";
|
| 3154 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3155 |
|
|
-- ........................................................................................
|
| 3156 |
|
|
when x"6C" => --JMP indirect 6th part
|
| 3157 |
|
|
pc_inc_fg <= '0';
|
| 3158 |
|
|
-- dat2pc_fg <= '0';
|
| 3159 |
|
|
cycle_ctr <= x"0";
|
| 3160 |
|
|
|
| 3161 |
|
|
when x"60" => --RTS 6th part
|
| 3162 |
|
|
pc_inc_fg <= '0';
|
| 3163 |
|
|
cycle_ctr <= x"0";
|
| 3164 |
|
|
|
| 3165 |
|
|
when x"40" => --RTI sixth part
|
| 3166 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3167 |
|
|
pc_inc_fg <= '1';
|
| 3168 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3169 |
|
|
|
| 3170 |
|
|
when x"20" => --JSR 6th part
|
| 3171 |
|
|
pc_inc_fg <= '0';
|
| 3172 |
|
|
cycle_ctr <= x"0";
|
| 3173 |
|
|
|
| 3174 |
|
|
when x"00" => --Break 6th part cyc 5
|
| 3175 |
|
|
add_fg <= x"B";
|
| 3176 |
|
|
irq_fg <= '0';
|
| 3177 |
|
|
nmi_fg <= '0';
|
| 3178 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 3179 |
|
|
|
| 3180 |
|
|
when others =>
|
| 3181 |
|
|
-- cycle_ctr <= x"0";
|
| 3182 |
|
|
cycle_ctr <= cycle_ctr + x"1";
|
| 3183 |
|
|
-- --get_inst_fg <= '0';
|
| 3184 |
|
|
end case; --Cycle 5
|
| 3185 |
|
|
|
| 3186 |
|
|
------------------------------------------------------------------------
|
| 3187 |
|
|
-- End of cycle 5
|
| 3188 |
|
|
-- Cycle 6 is for 3 byte instructions ie LDA abs
|
| 3189 |
|
|
|
| 3190 |
|
|
when x"6" =>
|
| 3191 |
|
|
case Instruction_in is
|
| 3192 |
|
|
|
| 3193 |
|
|
when x"EE" => --INC abs 7th part.
|
| 3194 |
|
|
pc_inc_fg <= '0';
|
| 3195 |
|
|
cycle_ctr <= x"0";
|
| 3196 |
|
|
when x"cE" => --DEC abs 7th part.
|
| 3197 |
|
|
pc_inc_fg <= '0';
|
| 3198 |
|
|
cycle_ctr <= x"0";
|
| 3199 |
|
|
when x"2E" => --ROL abs 7th part.
|
| 3200 |
|
|
pc_inc_fg <= '0';
|
| 3201 |
|
|
cycle_ctr <= x"0";
|
| 3202 |
|
|
when x"3E" => --ROL, x abs 7th part.
|
| 3203 |
|
|
pc_inc_fg <= '0';
|
| 3204 |
|
|
cycle_ctr <= x"0";
|
| 3205 |
|
|
when x"6E" => --ROR abs 7th part.
|
| 3206 |
|
|
pc_inc_fg <= '0';
|
| 3207 |
|
|
cycle_ctr <= x"0";
|
| 3208 |
|
|
when x"7E" => --ROR, x abs 7th part.
|
| 3209 |
|
|
pc_inc_fg <= '0';
|
| 3210 |
|
|
cycle_ctr <= x"0";
|
| 3211 |
|
|
when x"4E" => --LSR abs 7th part.
|
| 3212 |
|
|
pc_inc_fg <= '0';
|
| 3213 |
|
|
cycle_ctr <= x"0";
|
| 3214 |
|
|
when x"5E" => --LSR, x abs 7th part.
|
| 3215 |
|
|
pc_inc_fg <= '0';
|
| 3216 |
|
|
cycle_ctr <= x"0";
|
| 3217 |
|
|
when x"0E" => --ASL abs 7th part.
|
| 3218 |
|
|
pc_inc_fg <= '0';
|
| 3219 |
|
|
cycle_ctr <= x"0";
|
| 3220 |
|
|
when x"1E" => --ASL, x abs 7th part.
|
| 3221 |
|
|
pc_inc_fg <= '0';
|
| 3222 |
|
|
cycle_ctr <= x"0";
|
| 3223 |
|
|
--=============================================================================
|
| 3224 |
|
|
|
| 3225 |
|
|
when x"40" => --RTI 7th part
|
| 3226 |
|
|
pc_inc_fg <= '0';
|
| 3227 |
|
|
cycle_ctr <= x"0";
|
| 3228 |
|
|
|
| 3229 |
|
|
when x"00" => --Break 7th part cyc 6
|
| 3230 |
|
|
dat2pc_fg <= '1';
|
| 3231 |
|
|
add_fg <= x"0";
|
| 3232 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 3233 |
|
|
|
| 3234 |
|
|
when others =>
|
| 3235 |
|
|
cycle_ctr <= x"0";
|
| 3236 |
|
|
--get_inst_fg <= '0';
|
| 3237 |
|
|
|
| 3238 |
|
|
|
| 3239 |
|
|
end case; --Cycle 6
|
| 3240 |
|
|
-- End of cycle 6
|
| 3241 |
|
|
|
| 3242 |
|
|
|
| 3243 |
|
|
-- Cycle 8 is for 3 byte instructions ie LDA abs
|
| 3244 |
|
|
|
| 3245 |
|
|
when x"7" =>
|
| 3246 |
|
|
case Instruction_in is
|
| 3247 |
|
|
|
| 3248 |
|
|
when x"40" => --RTI 8th cyc
|
| 3249 |
|
|
cycle_ctr <= x"0";
|
| 3250 |
|
|
|
| 3251 |
|
|
when x"00" => --Break 8th part cyc 7
|
| 3252 |
|
|
if start_fg = '0' then --When starting don't mess with this
|
| 3253 |
|
|
i_fg <= '1'; --Break irq and start use this logic.
|
| 3254 |
|
|
end if;
|
| 3255 |
|
|
pc_inc_fg <= '1';
|
| 3256 |
|
|
start_fg <= '0';
|
| 3257 |
|
|
dat2pc_fg <= '0';
|
| 3258 |
|
|
-- cycle_ctr <= x"0";
|
| 3259 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 3260 |
|
|
|
| 3261 |
|
|
|
| 3262 |
|
|
when others =>
|
| 3263 |
|
|
cycle_ctr <= x"0";
|
| 3264 |
|
|
--get_inst_fg <= '0';
|
| 3265 |
|
|
|
| 3266 |
|
|
end case; --Cycle 7
|
| 3267 |
|
|
-- Cycle 7
|
| 3268 |
|
|
when x"8" =>
|
| 3269 |
|
|
case Instruction_in is
|
| 3270 |
|
|
|
| 3271 |
|
|
when x"00" => --Break 10th part cyc 8
|
| 3272 |
|
|
pc_inc_fg <= '0';
|
| 3273 |
|
|
cycle_ctr <= x"0";
|
| 3274 |
|
|
|
| 3275 |
|
|
when others =>
|
| 3276 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 3277 |
|
|
pc_inc_fg <= '0';
|
| 3278 |
|
|
|
| 3279 |
|
|
end case; --Cycle 8
|
| 3280 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 3281 |
|
|
-- Cycle 9
|
| 3282 |
|
|
when x"9" =>
|
| 3283 |
|
|
case Instruction_in is
|
| 3284 |
|
|
|
| 3285 |
|
|
when others =>
|
| 3286 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 3287 |
|
|
pc_inc_fg <= '0';
|
| 3288 |
|
|
|
| 3289 |
|
|
end case; --Cycle 9
|
| 3290 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 3291 |
|
|
-- Cycle A
|
| 3292 |
|
|
|
| 3293 |
|
|
when x"A" =>
|
| 3294 |
|
|
case Instruction_in is
|
| 3295 |
|
|
|
| 3296 |
|
|
|
| 3297 |
|
|
when others =>
|
| 3298 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 3299 |
|
|
pc_inc_fg <= '0';
|
| 3300 |
|
|
|
| 3301 |
|
|
end case; --Cycle A
|
| 3302 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 3303 |
|
|
-- Cycle B
|
| 3304 |
|
|
|
| 3305 |
|
|
when x"B" =>
|
| 3306 |
|
|
case Instruction_in is
|
| 3307 |
|
|
|
| 3308 |
|
|
when others =>
|
| 3309 |
|
|
cycle_ctr <= cycle_ctr + "1";
|
| 3310 |
|
|
pc_inc_fg <= '0';
|
| 3311 |
|
|
|
| 3312 |
|
|
end case; --Cycle B
|
| 3313 |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
| 3314 |
|
|
-- Cycle C
|
| 3315 |
|
|
|
| 3316 |
|
|
when x"C" =>
|
| 3317 |
|
|
case Instruction_in is
|
| 3318 |
|
|
|
| 3319 |
|
|
|
| 3320 |
|
|
when others =>
|
| 3321 |
|
|
cycle_ctr <= x"0";
|
| 3322 |
|
|
|
| 3323 |
|
|
end case; --Cycle C
|
| 3324 |
|
|
|
| 3325 |
|
|
-- ==========================================================================
|
| 3326 |
|
|
|
| 3327 |
|
|
|
| 3328 |
|
|
when others =>
|
| 3329 |
|
|
cycle_ctr<= x"0";
|
| 3330 |
|
|
end case; --cycle_ctr
|
| 3331 |
|
|
end if; --Reset stuff
|
| 3332 |
|
|
|
| 3333 |
|
|
end if; --rising edge
|
| 3334 |
|
|
|
| 3335 |
|
|
end process instruction_decode;
|
| 3336 |
|
|
|
| 3337 |
|
|
end P65C02_architecture;
|
| 3338 |
|
|
|
