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idiolatrie |
--------------------------------------------------------------------------------
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-- MIPS™ I CPU --
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--------------------------------------------------------------------------------
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-- --
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-- POSSIBLE FAULTS --
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-- --
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-- o The upper 4bits of a branch/jump instruction depend on the PC of the --
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-- branch delay slot. This special case has not been tested: --
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-- --
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-- PC INSTRUCTION --
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-- +------------+-----------------+ --
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-- | 0x0fffffff | some branch OP | --
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-- | 0x10000000 | ADD $s1, $s1, 1 | --
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-- +------------+-----------------+ --
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-- --
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-- Whenever the upper 4 PC bits of the jump instruction differs from the --
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-- delay slot instruction address, there might be a chance of incorrect --
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-- behavoir. --
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-- --
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-- o Interrupts are still experimental. --
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-- --
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--------------------------------------------------------------------------------
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-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
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-- --
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-- This program is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.mips1.all;
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use work.tcpu.all;
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use work.icpu.all;
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use work.fcpu.all;
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entity cpu is
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port(
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ci : in cpu_in_t;
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co : out cpu_out_t
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);
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end cpu;
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architecture rtl of cpu is
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signal f, fin : fe_t; -- FE: [FETCH STAGE]
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signal d, din : de_t; -- DE: [DECODE STAGE]
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signal e, ein : ex_t; -- EX: [EXECUTION STAGE]
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signal m, min : me_t; -- ME: [MEMORY STAGE]
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signal cp, cpin : cp0_t; -- Coprocessor 0 registers
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-- Interrupt related signals.
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signal intr_bd : boolean; -- Branch delay flag.
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signal intr_bdd : boolean; -- Branch delay delay flag.
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signal intr_im : std_logic_vector(7 downto 0); -- Interrupt mask.
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signal intr_iec : std_logic; -- IEc: Interrupt enable current.
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signal intr_iep : std_logic; -- IEp: Interrupt enable previous.
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signal intr_ieo : std_logic; -- IEo: Interrupt enable old.
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-- Aliases for the instruction's GPR RS and RT addresses.
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alias rs_a : std_logic_vector(4 downto 0) is ci.ins(25 downto 21);
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alias rt_a : std_logic_vector(4 downto 0) is ci.ins(20 downto 16);
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signal rs_o, rt_o : std_logic_vector(31 downto 0); -- GPR output data.
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begin
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-----------------------------------------------------------------------------
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-- FETCH STAGE --
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-----------------------------------------------------------------------------
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fe : process(f.pc, ci.irq, e.f, d.cc, cp.epc, cp.sr, intr_bd, intr_im,
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intr_iec, intr_iep, intr_ieo)
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--------------------------------------------------------------------------
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-- EPC Address --
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--------------------------------------------------------------------------
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-- SETTING: Interrupt handler routine address.
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constant INTR_ADR : unsigned(31 downto 0) := x"200000c0";
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variable v : fe_t;
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variable c : cp0_t;
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variable intr : boolean;
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begin
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v := f;
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c := cp;
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-- Address of the next instruction to be fetched.
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co.iadr <= std_logic_vector(f.pc) & "00";
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-- Program Counter
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-- if e.f.jmp = '1' then
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-- v.pc := e.f.j;
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-- else if d.f.jmp = '1' then
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-- v.pc := d.f.j;
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-- else
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-- v.pc := f.pc + 1;
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-- end if;
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-- Program Counter
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if e.f.jmp = '1' then v.pc := e.f.j; else v.pc := f.pc + 1; end if;
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--------------------------------------------------------------------------
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-- INTR Interrupt --
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--------------------------------------------------------------------------
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-- The interrupt mechanism consists of several tasks: --
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-- o Push a '0' onto the IE stack to avoid further interrupt triggers. --
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-- o Set the EPC to the instruction following the current instruction. --
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-- o Jump to EPC_ADR, which is the hardcoded address of the interrupt --
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-- dispatch routine. --
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--------------------------------------------------------------------------
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-- Restore from exception.
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-- Do before interrupt handling, or else we might push the IE stack twice.
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if d.cc.rfe then c := pop_ie(c); end if;
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-- Set SR of CP0. [DE]
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-- Set (Disable) SR before interrupt handling.
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if d.cc.mtsr then
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c.sr.im := intr_im;
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c.sr.iec := intr_iec;
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c.sr.iep := intr_iep;
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c.sr.ieo := intr_ieo;
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end if;
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-- Delay interrupt if we are in one of the to delay slots.
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-- Push the IE stack, Save return address and jump to the interrupt
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-- handler.
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intr := ( (cp.sr.im and ci.irq) /= x"00" ) and (cp.sr.iec = '1');
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if (not intr_bd) and (not intr_bdd) and intr then
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c := push_ie(c);
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-- Save PC weather it is from a jump or just incremented.
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c.epc := v.pc; -- e.f.j or f.pc + 1.
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v.pc := INTR_ADR(31 downto 2);
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end if;
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fin <= v;
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cpin <= c;
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end process;
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-----------------------------------------------------------------------------
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-- DECODE STAGE --
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-----------------------------------------------------------------------------
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de : process(ci.ins, d, m, m.wc, d.cc, d.dc, d.ec, d.ec.alu, d.ec.alu.src,
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d.ec.jmp, d.mc, d.mc.mem, d.wc)
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variable v : de_t;
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alias rgcp0 : std_logic_vector(4 downto 0) is ci.ins(15 downto 11);
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begin
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v := d;
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-- synthesis translate_off
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co.op <= op(ci.ins);
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co.alu <= aluop(ci.ins);
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co.rimm <= rimmop(ci.ins);
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co.cp0op <= cp0op(ci.ins);
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co.cp0reg <= cp0reg(ci.ins(4 downto 0));
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-- synthesis translate_on
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--------------------------------------------------------------------------
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-- Decode --
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--------------------------------------------------------------------------
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-- Default values emulate a NOP [SLL $0, $0, 0] operation.
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v.cc.mtsr := false; -- Move To Status Register. [INTR]
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v.cc.rfe := false; -- Restore from Exception. [INTR]
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--v.f.jmp := '0';
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--v.f.j := (others => '-');
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v.ec.wbr := RD; -- Write back register.
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v.ec.alu.op := SLL0; -- ALU operation. [ALU]
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v.ec.alu.src.a := REG; -- Source for ALU input A. [ALU Source Choice]
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v.ec.alu.src.b := REG; -- Source for ALU input B. [ALU Source Choice]
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v.ec.jmp.src := REG; -- Jump source. [Branch/Jump]
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v.ec.jmp.op := NOP; -- Jump type. [Branch/Jump]
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v.mc.mem.we := '0'; -- Memory write enable.
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v.mc.mem.ext := ZERO; -- Memory data extension. [Data Extension]
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v.mc.mem.byt := NONE; -- Number of data bytes. [MEMORY STAGE]
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v.mc.src := ALU; -- ALU or MEM to GPR. [MEMORY STAGE]
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v.wc.we := '0'; -- GPR write enable.
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intr_bd <= false; -- Marks a branch delay slot. [INTR]
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case op(ci.ins) is
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when AD =>
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case aluop(ci.ins) is
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when JALR =>
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v := link(v);
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v.ec.jmp.op := JMP;
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intr_bd <= true;
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when JR =>
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v.ec.jmp.op := JMP;
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intr_bd <= true;
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when SLL0 | SRA0 | SRL0 =>
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v.ec.alu.op := aluop(ci.ins);
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v.ec.alu.src.a := SH_CONST;
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v.wc.we := '1';
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when others =>
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v.ec.alu.op := aluop(ci.ins);
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v.wc.we := '1';
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end case;
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-----------------------------------------------------------------------
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-- Immediate Branches --
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-----------------------------------------------------------------------
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when RI =>
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case rimmop(ci.ins) is
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when BGEZ =>
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v.ec.jmp.src := BRA;
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v.ec.jmp.op := GEZ;
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intr_bd <= true;
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when BGEZAL =>
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v := link(v);
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v.ec.wbr := RA;
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v.ec.jmp.src := BRA;
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| 230 |
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v.ec.jmp.op := GEZ;
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| 231 |
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intr_bd <= true;
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| 232 |
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when BLTZ =>
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v.ec.jmp.src := BRA;
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| 234 |
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v.ec.jmp.op := LTZ;
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| 235 |
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intr_bd <= true;
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| 236 |
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when BLTZAL =>
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v := link(v);
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| 238 |
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v.ec.wbr := RA;
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| 239 |
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v.ec.jmp.src := BRA;
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| 240 |
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v.ec.jmp.op := LTZ;
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| 241 |
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intr_bd <= true;
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| 242 |
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when ERR =>
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| 243 |
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end case;
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-----------------------------------------------------------------------
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-- Normal Jumps/Branches --
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| 247 |
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-----------------------------------------------------------------------
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| 248 |
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when J =>
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| 249 |
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-- v.f.jmp := '1';
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| 250 |
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-- v.f.j := f.pc(31 downto 28) & unsigned(ci.ins);
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| 251 |
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v.ec.jmp.src := JMP;
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| 252 |
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v.ec.jmp.op := JMP;
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| 253 |
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intr_bd <= true;
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| 254 |
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when JAL =>
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| 255 |
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v := link(v);
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| 256 |
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v.ec.wbr := RA;
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| 257 |
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-- v.f.jmp := '1';
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| 258 |
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-- v.f.j := f.pc(31 downto 28) & unsigned(ci.ins);
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| 259 |
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v.ec.jmp.src := JMP;
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| 260 |
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v.ec.jmp.op := JMP;
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| 261 |
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intr_bd <= true;
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| 262 |
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when BEQ =>
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| 263 |
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v.ec.jmp.src := BRA;
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| 264 |
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v.ec.jmp.op := EQ;
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| 265 |
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intr_bd <= true;
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| 266 |
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when BNE =>
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| 267 |
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v.ec.jmp.src := BRA;
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| 268 |
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v.ec.jmp.op := NEQ;
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| 269 |
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intr_bd <= true;
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| 270 |
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when BLEZ =>
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| 271 |
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v.ec.jmp.src := BRA;
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| 272 |
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v.ec.jmp.op := LEZ;
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| 273 |
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intr_bd <= true;
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| 274 |
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when BGTZ =>
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| 275 |
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v.ec.jmp.src := BRA;
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| 276 |
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v.ec.jmp.op := GTZ;
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| 277 |
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intr_bd <= true;
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| 278 |
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| 279 |
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-----------------------------------------------------------------------
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| 280 |
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-- Immediate Operations --
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| 281 |
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-----------------------------------------------------------------------
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| 282 |
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when ADDI =>
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| 283 |
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v := simm(v);
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| 284 |
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v.ec.alu.op := ADD;
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| 285 |
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when ADDIU =>
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| 286 |
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v := simm(v);
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| 287 |
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v.ec.alu.op := ADDU;
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| 288 |
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when SLTI =>
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| 289 |
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v := simm(v);
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| 290 |
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v.ec.alu.op := SLT;
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| 291 |
|
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when SLTIU =>
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| 292 |
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v := simm(v);
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| 293 |
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v.ec.alu.op := SLTU;
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| 294 |
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when ANDI =>
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| 295 |
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v := zimm(v);
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| 296 |
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v.ec.alu.op := AND0;
|
| 297 |
|
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when ORI =>
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| 298 |
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v := zimm(v);
|
| 299 |
|
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v.ec.alu.op := OR0;
|
| 300 |
|
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when XORI =>
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| 301 |
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v := zimm(v);
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| 302 |
|
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v.ec.alu.op := XOR0;
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| 303 |
|
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when LUI =>
|
| 304 |
|
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v := zimm(v);
|
| 305 |
|
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v.ec.alu.src.a := SH_16;
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| 306 |
|
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|
| 307 |
|
|
-----------------------------------------------------------------------
|
| 308 |
|
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-- Load And Store Data --
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| 309 |
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-----------------------------------------------------------------------
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| 310 |
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when LB =>
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| 311 |
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v := load(v);
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| 312 |
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v.mc.mem.ext := SIGN;
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| 313 |
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v.mc.mem.byt := BYTE;
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| 314 |
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when LH =>
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| 315 |
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v := load(v);
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| 316 |
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v.mc.mem.ext := SIGN;
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| 317 |
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v.mc.mem.byt := HALF;
|
| 318 |
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when LW =>
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| 319 |
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v := load(v);
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| 320 |
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v.mc.mem.byt := WORD;
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| 321 |
|
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when LBU =>
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| 322 |
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v := load(v);
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| 323 |
|
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v.mc.mem.byt := BYTE;
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| 324 |
|
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when LHU =>
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| 325 |
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v := load(v);
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| 326 |
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v.mc.mem.byt := HALF;
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| 327 |
|
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when SB =>
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| 328 |
|
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v := store(v);
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| 329 |
|
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v.mc.mem.byt := BYTE;
|
| 330 |
|
|
when SH =>
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| 331 |
|
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v := store(v);
|
| 332 |
|
|
v.mc.mem.byt := HALF;
|
| 333 |
|
|
when SW =>
|
| 334 |
|
|
v := store(v);
|
| 335 |
|
|
v.mc.mem.byt := WORD;
|
| 336 |
|
|
|
| 337 |
|
|
-----------------------------------------------------------------------
|
| 338 |
|
|
-- Co-Processor 0 --
|
| 339 |
|
|
-----------------------------------------------------------------------
|
| 340 |
|
|
when CP0 =>
|
| 341 |
|
|
case cp0op(ci.ins) is
|
| 342 |
|
|
when MFCP0 =>
|
| 343 |
|
|
v.ec.wbr := RT;
|
| 344 |
|
|
v.ec.alu.op := MFCP0;
|
| 345 |
|
|
v.wc.we := '1';
|
| 346 |
|
|
when MTCP0 =>
|
| 347 |
|
|
v.ec.alu.op := MTCP0;
|
| 348 |
|
|
if cp0reg(rgcp0) = SR then v.cc.mtsr := true; end if;
|
| 349 |
|
|
when RFE =>
|
| 350 |
|
|
v.ec.alu.op := RFE;
|
| 351 |
|
|
v.cc.rfe := true;
|
| 352 |
|
|
when ERR =>
|
| 353 |
|
|
end case;
|
| 354 |
|
|
when ERR =>
|
| 355 |
|
|
end case;
|
| 356 |
|
|
|
| 357 |
|
|
v.i := ci.ins(25 downto 0);
|
| 358 |
|
|
v.dc.we := m.wc.we; -- Forward write enable.
|
| 359 |
|
|
v.rd := m.rd; -- Forward destination register.
|
| 360 |
|
|
v.res := m.res; -- Forward data.
|
| 361 |
|
|
din <= v;
|
| 362 |
|
|
end process;
|
| 363 |
|
|
|
| 364 |
|
|
-----------------------------------------------------------------------------
|
| 365 |
|
|
-- GPR General Purpose Registers --
|
| 366 |
|
|
-----------------------------------------------------------------------------
|
| 367 |
|
|
gp : gpr port map(
|
| 368 |
|
|
clk_i => ci.clk, -- Clock.
|
| 369 |
|
|
hld_i => ci.hld, -- Hold register data.
|
| 370 |
|
|
rs_a => rs_a, -- RS register address.
|
| 371 |
|
|
rt_a => rt_a, -- RT register address.
|
| 372 |
|
|
rd_a => m.rd, -- Write back register address.
|
| 373 |
|
|
rd_we => m.wc.we, -- Write back enable.
|
| 374 |
|
|
rd_i => m.res, -- Write back register data.
|
| 375 |
|
|
rs_o => rs_o, -- RS register data.
|
| 376 |
|
|
rt_o => rt_o -- RT register data.
|
| 377 |
|
|
);
|
| 378 |
|
|
|
| 379 |
|
|
|
| 380 |
|
|
|
| 381 |
|
|
-----------------------------------------------------------------------------
|
| 382 |
|
|
-- EXECUTION STAGE --
|
| 383 |
|
|
-----------------------------------------------------------------------------
|
| 384 |
|
|
ex : process(ci.irq, rs_o, rt_o, cp, cp.sr, f, d, d.dc, d.ec, d.ec.alu,
|
| 385 |
|
|
d.ec.alu.src, d.ec.jmp, d.mc, d.mc.mem, d.wc, e, e.f, e.mc,
|
| 386 |
|
|
e.mc.mem, e.wc, m, m.wc)
|
| 387 |
|
|
|
| 388 |
|
|
variable v : ex_t;
|
| 389 |
|
|
variable a, b : std_logic_vector(31 downto 0); -- ALU input.
|
| 390 |
|
|
variable fa, fb : std_logic_vector(31 downto 0); -- Forwarded data.
|
| 391 |
|
|
variable equ, eqz : std_logic; -- fa=fb, fa=0
|
| 392 |
|
|
variable atmp : std_logic_vector(31 downto 0); -- Temporary result.
|
| 393 |
|
|
|
| 394 |
|
|
--------------------------------------------------------------------------
|
| 395 |
|
|
-- R-Type Register --
|
| 396 |
|
|
-- +--------------------------------------------------------------+ --
|
| 397 |
|
|
-- | | rgs | rgt | rgd | smt | | --
|
| 398 |
|
|
-- +--------------------------------------------------------------+ --
|
| 399 |
|
|
-- I-Type Register --
|
| 400 |
|
|
-- +--------------------------------------------------------------+ --
|
| 401 |
|
|
-- | | imm | --
|
| 402 |
|
|
-- +--------------------------------------------------------------+ --
|
| 403 |
|
|
--------------------------------------------------------------------------
|
| 404 |
|
|
alias rgs : std_logic_vector(4 downto 0) is d.i(25 downto 21);
|
| 405 |
|
|
alias rgt : std_logic_vector(4 downto 0) is d.i(20 downto 16);
|
| 406 |
|
|
alias rgd : std_logic_vector(4 downto 0) is d.i(15 downto 11);
|
| 407 |
|
|
alias imm : std_logic_vector(15 downto 0) is d.i(15 downto 0);
|
| 408 |
|
|
alias smt : std_logic_vector(4 downto 0) is d.i(10 downto 6);
|
| 409 |
|
|
begin
|
| 410 |
|
|
v := e;
|
| 411 |
|
|
|
| 412 |
|
|
-- Choose the write back register.
|
| 413 |
|
|
case d.ec.wbr is
|
| 414 |
|
|
when RD => v.rd := rgd;
|
| 415 |
|
|
when RT => v.rd := rgt;
|
| 416 |
|
|
when RA => v.rd := b"11111";
|
| 417 |
|
|
end case;
|
| 418 |
|
|
|
| 419 |
|
|
--------------------------------------------------------------------------
|
| 420 |
|
|
-- Forwarding --
|
| 421 |
|
|
--------------------------------------------------------------------------
|
| 422 |
|
|
-- In a pipeline there can be data that has not been written into the --
|
| 423 |
|
|
-- GPR registers yet. For example see: --
|
| 424 |
|
|
-- --
|
| 425 |
|
|
-- addu $t0, $t1, $t2 -+ --
|
| 426 |
|
|
-- sll $t3, $t0, 4 -+- $t0 --
|
| 427 |
|
|
-- --
|
| 428 |
|
|
-- Here GPR $t0 is not up to date, since the instruction addu --
|
| 429 |
|
|
-- manipulates $t0, but is available after EX, so we choose the newer --
|
| 430 |
|
|
-- data from after the EX stage instead of the GPR data. --
|
| 431 |
|
|
-- However, if we load data and use it in the next instruction, we get --
|
| 432 |
|
|
-- the wrong result. Loaded data is available two cycles after the load --
|
| 433 |
|
|
-- instruction. The compiler solves this problem, since it inserts an --
|
| 434 |
|
|
-- independend instruction or a NOP operation. --
|
| 435 |
|
|
-- Other problems arise when: --
|
| 436 |
|
|
-- --
|
| 437 |
|
|
-- ori $t0, $s1, 3 -+ --
|
| 438 |
|
|
-- sw $s2, 4($sp) | --
|
| 439 |
|
|
-- subu $s2, $t0, $s3 -+- $t0 --
|
| 440 |
|
|
-- --
|
| 441 |
|
|
-- In the second example, the updated data is available after the ME --
|
| 442 |
|
|
-- stage. Up untill now we considered the situation from the viewpoint --
|
| 443 |
|
|
-- of the EX stage. --
|
| 444 |
|
|
-- --
|
| 445 |
|
|
-- andi $t0, $t0, 1 -+ --
|
| 446 |
|
|
-- lui $s1, 0xf4 | --
|
| 447 |
|
|
-- lw $s2, 0($sp) | --
|
| 448 |
|
|
-- sra $t1, $t0, 3 -+- $t0 --
|
| 449 |
|
|
-- --
|
| 450 |
|
|
-- The third example shows a problem that arrises one cycle earlier. --
|
| 451 |
|
|
-- When we read the register contents. The data to be written is --
|
| 452 |
|
|
-- present as well but not available yet. One solution might be, to --
|
| 453 |
|
|
-- prefer write before read operations. the other way suggests to store --
|
| 454 |
|
|
-- the write back data, address and write enable flag one more cycle. --
|
| 455 |
|
|
-- We can then decide in the EX stage again if the data is more recent. --
|
| 456 |
|
|
--------------------------------------------------------------------------
|
| 457 |
|
|
fa := rs_o;
|
| 458 |
|
|
fb := rt_o;
|
| 459 |
|
|
|
| 460 |
|
|
-- Forward from Write Back Stage (Data stored in DE Stage).
|
| 461 |
|
|
if (d.rd /= "00000") and (d.dc.we = '1') then
|
| 462 |
|
|
if rgs = d.rd then fa := d.res; end if;
|
| 463 |
|
|
if rgt = d.rd then fb := d.res; end if;
|
| 464 |
|
|
end if;
|
| 465 |
|
|
|
| 466 |
|
|
-- Forward from Memory Stage.
|
| 467 |
|
|
if (m.rd /= "00000") and (m.wc.we = '1') then
|
| 468 |
|
|
if rgs = m.rd then fa := m.res; end if;
|
| 469 |
|
|
if rgt = m.rd then fb := m.res; end if;
|
| 470 |
|
|
end if;
|
| 471 |
|
|
|
| 472 |
|
|
-- Forward from Execution Stage.
|
| 473 |
|
|
if (e.rd /= "00000") and (e.wc.we = '1') then
|
| 474 |
|
|
if rgs = e.rd then fa := e.res; end if;
|
| 475 |
|
|
if rgt = e.rd then fb := e.res; end if;
|
| 476 |
|
|
end if;
|
| 477 |
|
|
|
| 478 |
|
|
--------------------------------------------------------------------------
|
| 479 |
|
|
-- ALU Source Choice --
|
| 480 |
|
|
--------------------------------------------------------------------------
|
| 481 |
|
|
-- SH_CONST: Constant shift amount (SLL, SRL, SRA). --
|
| 482 |
|
|
-- SH_16: Shift 16-bit (LUI). --
|
| 483 |
|
|
-- ADD_4: Plus 4. --
|
| 484 |
|
|
-- REG: Forwarded RS register value. [Forwarding] --
|
| 485 |
|
|
--------------------------------------------------------------------------
|
| 486 |
|
|
case d.ec.alu.src.a is
|
| 487 |
|
|
when SH_CONST => a := zext(smt, 32);
|
| 488 |
|
|
when SH_16 => a := zext(b"10000", 32);
|
| 489 |
|
|
when ADD_4 => a := zext(b"00100", 32);
|
| 490 |
|
|
when REG => a := fa;
|
| 491 |
|
|
end case;
|
| 492 |
|
|
|
| 493 |
|
|
--------------------------------------------------------------------------
|
| 494 |
|
|
-- SIGN: Sign extend 16-bit immediate value according to MSB. --
|
| 495 |
|
|
-- ZERO: Zero extend 16-bit immediate value. --
|
| 496 |
|
|
-- PC: Current PC value. --
|
| 497 |
|
|
-- REG: Forwarded RT register value. [Forwarding] --
|
| 498 |
|
|
--------------------------------------------------------------------------
|
| 499 |
|
|
case d.ec.alu.src.b is
|
| 500 |
|
|
when SIGN => b := sext(imm, 32);
|
| 501 |
|
|
when ZERO => b := zext(imm, 32);
|
| 502 |
|
|
when PC => b := std_logic_vector(f.pc) & "00";
|
| 503 |
|
|
when REG => b := fb;
|
| 504 |
|
|
end case;
|
| 505 |
|
|
|
| 506 |
|
|
--------------------------------------------------------------------------
|
| 507 |
|
|
-- ALU --
|
| 508 |
|
|
--------------------------------------------------------------------------
|
| 509 |
|
|
-- IMPROVE: optimze SLT,SLTU.
|
| 510 |
|
|
intr_iec <= b(0); -- IEc: Interrupt enable current. [INTR]
|
| 511 |
|
|
intr_iep <= b(2); -- IEp: Interrupt enable previous. [INTR]
|
| 512 |
|
|
intr_ieo <= b(4); -- IEo: Interrupt enable old. [INTR]
|
| 513 |
|
|
intr_im <= b(15 downto 8); -- Interrupt mask. [INTR]
|
| 514 |
|
|
|
| 515 |
|
|
atmp := addsub(a, b, d.ec.alu.op);
|
| 516 |
|
|
v.res := (others => '0');
|
| 517 |
|
|
|
| 518 |
|
|
case d.ec.alu.op is
|
| 519 |
|
|
when ADD | ADDU |
|
| 520 |
|
|
SUB | SUBU => v.res := atmp;
|
| 521 |
|
|
when SLT => v.res := fslt(a, b);
|
| 522 |
|
|
when SLTU => v.res := fsltu(a, b);
|
| 523 |
|
|
when SLL0 | SLLV => v.res := fsll(b, a(4 downto 0));
|
| 524 |
|
|
when SRA0 | SRAV => v.res := fsra(b, a(4 downto 0));
|
| 525 |
|
|
when SRL0 | SRLV => v.res := fsrl(b, a(4 downto 0));
|
| 526 |
|
|
when AND0 => v.res := a and b;
|
| 527 |
|
|
when OR0 => v.res := a or b;
|
| 528 |
|
|
when NOR0 => v.res := a nor b;
|
| 529 |
|
|
when XOR0 => v.res := a xor b;
|
| 530 |
|
|
when JALR | JR =>
|
| 531 |
|
|
when MFCP0 =>
|
| 532 |
|
|
case cp0reg(rgd) is
|
| 533 |
|
|
when SR => v.res := get_sr(cp);
|
| 534 |
|
|
when CAUSE => v.res(15 downto 8) := ci.irq;
|
| 535 |
|
|
when EPC => v.res := std_logic_vector(cp.epc) & "00";
|
| 536 |
|
|
when ERR =>
|
| 537 |
|
|
end case;
|
| 538 |
|
|
when MTCP0 => -- MTCP0 and RFE operations are handled at the
|
| 539 |
|
|
when RFE => -- IF stage.
|
| 540 |
|
|
when ERR =>
|
| 541 |
|
|
end case;
|
| 542 |
|
|
|
| 543 |
|
|
--------------------------------------------------------------------------
|
| 544 |
|
|
-- Branch/Jump --
|
| 545 |
|
|
--------------------------------------------------------------------------
|
| 546 |
|
|
-- IMPROVE: move jump to DE stage.
|
| 547 |
|
|
if fa = fb then equ := '1'; else equ := '0'; end if;
|
| 548 |
|
|
if fa = x"00000000" then eqz := '1'; else eqz := '0'; end if;
|
| 549 |
|
|
|
| 550 |
|
|
case d.ec.jmp.op is
|
| 551 |
|
|
when NOP => v.f.jmp := '0';
|
| 552 |
|
|
when JMP => v.f.jmp := '1';
|
| 553 |
|
|
when EQ => v.f.jmp := equ;
|
| 554 |
|
|
when NEQ => v.f.jmp := not equ;
|
| 555 |
|
|
when LTZ => v.f.jmp := fa(31);
|
| 556 |
|
|
when GTZ => v.f.jmp := not (fa(31) or eqz);
|
| 557 |
|
|
when LEZ => v.f.jmp := fa(31) or eqz;
|
| 558 |
|
|
when GEZ => v.f.jmp := not fa(31);
|
| 559 |
|
|
end case;
|
| 560 |
|
|
|
| 561 |
|
|
case d.ec.jmp.src is
|
| 562 |
|
|
when REG => v.f.j := unsigned(fa(31 downto 2));
|
| 563 |
|
|
when JMP => v.f.j := f.pc(31 downto 28) & unsigned(d.i);
|
| 564 |
|
|
when BRA => v.f.j := unsigned(to_integer(f.pc) + signed(sext(imm,30)));
|
| 565 |
|
|
end case;
|
| 566 |
|
|
|
| 567 |
|
|
v.mc := d.mc;
|
| 568 |
|
|
v.wc := d.wc;
|
| 569 |
|
|
v.str := fb;
|
| 570 |
|
|
ein <= v;
|
| 571 |
|
|
end process;
|
| 572 |
|
|
|
| 573 |
|
|
|
| 574 |
|
|
|
| 575 |
|
|
-----------------------------------------------------------------------------
|
| 576 |
|
|
-- MEMORY STAGE --
|
| 577 |
|
|
-----------------------------------------------------------------------------
|
| 578 |
|
|
me : process(ci.dat, e, e.mc, e.mc.mem, e.wc, m, m.wc)
|
| 579 |
|
|
variable v : me_t;
|
| 580 |
|
|
variable dat : std_logic_vector(31 downto 0); -- Fetched memory data
|
| 581 |
|
|
begin
|
| 582 |
|
|
v := m;
|
| 583 |
|
|
|
| 584 |
|
|
co.we <= e.mc.mem.we;
|
| 585 |
|
|
co.dadr <= e.res;
|
| 586 |
|
|
co.dat <= e.str;
|
| 587 |
|
|
|
| 588 |
|
|
--------------------------------------------------------------------------
|
| 589 |
|
|
-- Address Decode --
|
| 590 |
|
|
--------------------------------------------------------------------------
|
| 591 |
|
|
-- Translate lower address bits to Wishbone Bus selection scheme. --
|
| 592 |
|
|
--------------------------------------------------------------------------
|
| 593 |
|
|
case e.mc.mem.byt is
|
| 594 |
|
|
when NONE => co.sel <= "0000";
|
| 595 |
|
|
when BYTE =>
|
| 596 |
|
|
case e.res(1 downto 0) is
|
| 597 |
|
|
when "00" => co.sel <= "1000";
|
| 598 |
|
|
when "01" => co.sel <= "0100";
|
| 599 |
|
|
when "10" => co.sel <= "0010";
|
| 600 |
|
|
when "11" => co.sel <= "0001";
|
| 601 |
|
|
when others => co.sel <= "0000";
|
| 602 |
|
|
end case;
|
| 603 |
|
|
when HALF =>
|
| 604 |
|
|
case e.res(1) is
|
| 605 |
|
|
when '0' => co.sel <= "1100";
|
| 606 |
|
|
when '1' => co.sel <= "0011";
|
| 607 |
|
|
when others => co.sel <= "0000";
|
| 608 |
|
|
end case;
|
| 609 |
|
|
when WORD => co.sel <= "1111";
|
| 610 |
|
|
end case;
|
| 611 |
|
|
|
| 612 |
|
|
--------------------------------------------------------------------------
|
| 613 |
|
|
-- Data Extension --
|
| 614 |
|
|
--------------------------------------------------------------------------
|
| 615 |
|
|
-- Fetched data can be extended with zeros or according to its MSB. --
|
| 616 |
|
|
--------------------------------------------------------------------------
|
| 617 |
|
|
case e.mc.mem.byt is
|
| 618 |
|
|
when NONE => dat := (others => '0'); -- AREA: (others => '-');
|
| 619 |
|
|
when BYTE =>
|
| 620 |
|
|
case e.mc.mem.ext is
|
| 621 |
|
|
when ZERO => dat := zext(ci.dat(7 downto 0), 32);
|
| 622 |
|
|
when SIGN => dat := sext(ci.dat(7 downto 0), 32);
|
| 623 |
|
|
end case;
|
| 624 |
|
|
when HALF =>
|
| 625 |
|
|
case e.mc.mem.ext is
|
| 626 |
|
|
when ZERO => dat := zext(ci.dat(15 downto 0), 32);
|
| 627 |
|
|
when SIGN => dat := sext(ci.dat(15 downto 0), 32);
|
| 628 |
|
|
end case;
|
| 629 |
|
|
when WORD => dat := ci.dat;
|
| 630 |
|
|
end case;
|
| 631 |
|
|
|
| 632 |
|
|
case e.mc.src is
|
| 633 |
|
|
when ALU => v.res := e.res; -- Take either the result of the ALU
|
| 634 |
|
|
when MEM => v.res := dat; -- or the loaded data from memory.
|
| 635 |
|
|
end case;
|
| 636 |
|
|
|
| 637 |
|
|
v.wc := e.wc;
|
| 638 |
|
|
v.rd := e.rd;
|
| 639 |
|
|
min <= v;
|
| 640 |
|
|
end process;
|
| 641 |
|
|
|
| 642 |
|
|
|
| 643 |
|
|
|
| 644 |
|
|
-----------------------------------------------------------------------------
|
| 645 |
|
|
-- REGISTERS --
|
| 646 |
|
|
-----------------------------------------------------------------------------
|
| 647 |
|
|
reg : process(ci.clk)
|
| 648 |
|
|
begin
|
| 649 |
|
|
if rising_edge(ci.clk) then
|
| 650 |
|
|
if ci.hld = '0' then
|
| 651 |
|
|
f <= fin; -- IF
|
| 652 |
|
|
d <= din; -- DE
|
| 653 |
|
|
e <= ein; -- EX
|
| 654 |
|
|
m <= min; -- ME
|
| 655 |
|
|
cp <= cpin; -- CP0
|
| 656 |
|
|
|
| 657 |
|
|
--------------------------------------------------------------------
|
| 658 |
|
|
-- Branch Correction --
|
| 659 |
|
|
--------------------------------------------------------------------
|
| 660 |
|
|
-- The simplest way one can think of, is to consider every branch --
|
| 661 |
|
|
-- or jump to be NOT taken and to load instructions in sequence. --
|
| 662 |
|
|
-- If we actually do jump, we already loaded an incorrect --
|
| 663 |
|
|
-- instruction in the IF stage. To anihilate the effects of this --
|
| 664 |
|
|
-- instruction, we will clear the DE stage one cycle later. --
|
| 665 |
|
|
-- [fcpu.clear(v_i : de_t)] --
|
| 666 |
|
|
--------------------------------------------------------------------
|
| 667 |
|
|
if e.f.jmp = '1' then d <= clear(d); end if;
|
| 668 |
|
|
|
| 669 |
|
|
-- Set Branch Delay Delay slot flag.
|
| 670 |
|
|
intr_bdd <= intr_bd;
|
| 671 |
|
|
end if;
|
| 672 |
|
|
|
| 673 |
|
|
-- On reset clear all relevant control signals.
|
| 674 |
|
|
if ci.rst = '1' then
|
| 675 |
|
|
f <= clear(f); -- IF
|
| 676 |
|
|
d <= clear(d); -- DE
|
| 677 |
|
|
e <= clear(e); -- EX
|
| 678 |
|
|
m <= clear(m); -- ME
|
| 679 |
|
|
cp <= clear(cp); -- CP0
|
| 680 |
|
|
end if;
|
| 681 |
|
|
end if;
|
| 682 |
|
|
end process;
|
| 683 |
|
|
end rtl;
|
