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idiolatrie |
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-- MIPS™ I CPU --
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-- --
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-- REFERENCES --
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-- --
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-- [1] David A. Patterson, John L. Hennessy, --
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-- Computer Organization and Design, The Hardware/Software Interface, --
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-- Morgan Kaufmann; 4 edition (November 10, 2008), --
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-- ISBN 978-0123744937 --
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-- --
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-- [2] IDT R30xx Family Software Reference Manual --
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-- Revision 1.0, ©1994 Integrated Device Technology, Inc. --
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-- [3] Ion - MIPS(tm) compatible CPU --
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-- <http://opencores.org/project,ion> --
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-- [4] Plasma - most MIPS I(TM) opcodes --
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-- <http://opencores.org/project,plasma> --
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-- --
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--------------------------------------------------------------------------------
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-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
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-- --
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-- This program is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.mips1.all;
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use work.tcpu.all;
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package icpu is
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type cpu_in_t is record
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clk : std_logic;
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rst : std_logic;
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hld : std_logic;
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irq : std_logic_vector(7 downto 0);
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ins : std_logic_vector(31 downto 0);
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dat : std_logic_vector(31 downto 0);
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end record;
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type cpu_out_t is record
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iadr : std_logic_vector(31 downto 0);
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dadr : std_logic_vector(31 downto 0);
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we : std_logic;
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sel : std_logic_vector(3 downto 0);
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dat : std_logic_vector(31 downto 0);
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-- synthesis translate_off
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op : op_t;
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alu : alu_op_t;
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rimm : rimm_op_t;
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cp0op : cp0_op_t;
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cp0reg : cp0_reg_t;
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-- synthesis translate_on
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end record;
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component cpu is
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port(
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ci : in cpu_in_t;
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co : out cpu_out_t
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);
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end component;
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end icpu;
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