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--------------------------------------------------------------------------------
-- MIPS� I CPU - Instruction Set                                              --
--------------------------------------------------------------------------------
-- Type definitions of the MIPS� I instruction (sub-)set and some convenience --
-- functions to convert binary operation representations to symbolic          --
-- equivalents.                                                               --
--                                                                            --
--------------------------------------------------------------------------------
-- Copyright (C)2011  Mathias H�rtnagl <mathias.hoertnagl@gmail.comt>         --
--                                                                            --
-- This program is free software: you can redistribute it and/or modify       --
-- it under the terms of the GNU General Public License as published by       --
-- the Free Software Foundation, either version 3 of the License, or          --
-- (at your option) any later version.                                        --
--                                                                            --
-- This program is distributed in the hope that it will be useful,            --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --
-- GNU General Public License for more details.                               --
--                                                                            --
-- You should have received a copy of the GNU General Public License          --
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.      --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package mips1 is
 
   -----------------------------------------------------------------------------
   -- OP Codes                                                                --
   -----------------------------------------------------------------------------
   type op_t is (
      AD,    -- Operations with AluOp
      RI,    -- Additional Branches
      J,     -- Jump
      JAL,   -- Jump And Link to $ra
      BEQ,   -- Branch On Equal
      BNE,   -- Branch On Not Equal
      BLEZ,  -- Branch Less Equal Zero
      BGTZ,  -- Branch Greater Than Zero
      ADDI,  -- Add Immediate
      ADDIU, -- Add Immediate Unsigned
      SLTI,  -- SLT Immediate
      SLTIU, -- SLT Immediate Unsigned
      ANDI,  -- And Immediate
      ORI,   -- Or Immediate
      XORI,  -- Xor Immediate
      LUI,   -- Load Upper Immediate
      LB,    -- Load Byte
      LH,    -- Load Half Word
      LW,    -- Load Word
      LBU,   -- Load Byte Unsigned
      LHU,   -- Load Half Word Unsigned
      SB,    -- Store Byte
      SH,    -- Store Half Word
      SW,    -- Store Word
      CP0,   -- Co-Processor 0 Operations
      ERR    -- Unknown OP
   );
 
   function op(i : std_logic_vector) return op_t;
 
   -----------------------------------------------------------------------------
   -- ALU OP Codes                                                            --
   -----------------------------------------------------------------------------
   -- In this implementation of the MIPS� I instruction set, ADD, ADDU and    --
   -- SUB, SUBU cause indentical behaviour. This means that ADDU and SUBU do  --
   -- NOT trap on overflow.                                                   --
   -----------------------------------------------------------------------------
   type alu_op_t is (
      ADD,   -- Addition
      ADDU,  -- Add Unsigned
      SUB,   -- Subtraction
      SUBU,  -- Subtract Unsigned
      AND0,  -- Logic and
      OR0,   -- Logic or
      NOR0,  -- Logic nor
      XOR0,  -- Logic xor
      SLT,   -- Set On Less Than
      SLTU,  -- SLT Unsigned
      SLL0,  -- Shift Left Logical
      SLLV,  -- SLL Variable
      SRA0,  -- Shift Right Arith
      SRAV,  -- SRA Variable
      SRL0,  -- Shift Right Logical
      SRLV,  -- SRL Variable
      JALR,  -- Jump And Link Reg
      JR,    -- Jump Reg
      MFCP0, -- Move From Co-Processor 0
      MTCP0, -- Move To Co-Processor 0
      RFE,   -- Restore From Exception
      ERR    -- Unknown ALU OP
   );
 
   -- Convert ALU Op bit pattern into its symbolic representation.
   function aluop(i : std_logic_vector) return alu_op_t;
 
   -----------------------------------------------------------------------------
   -- REGIMM Codes                                                            --
   -----------------------------------------------------------------------------
   type rimm_op_t is (
      BGEZ,   -- Branch Greater Equal 0
      BGEZAL, -- BGEZ And Link
      BLTZ,   -- Branch Less Than 0
      BLTZAL, -- BLTZ And Link
      ERR     -- Unknown RIMM OP
   );
 
   -- Convert Reg Immediate Op bit pattern into its symbolic representation.
   function rimmop(i : std_logic_vector) return rimm_op_t;
 
   -----------------------------------------------------------------------------
   -- CP0 Codes                                                               --
   -----------------------------------------------------------------------------
   type cp0_op_t is (
      MFCP0, -- Move From Co-Processor 0
      MTCP0, -- Move To Co-Processor 0
      RFE,   -- Restore From Exception
      ERR    -- Unknown CP0 OP
   );
 
   type cp0_reg_t is (
      SR,    -- Status Register
      CAUSE, -- Cause Register
      EPC,   -- EPC
      ERR    -- Unknown CP0 REG
   );
 
   -- Convert CP0 Op and Reg Addresses bit patterns into its symbolic
   -- representation.
   function cp0op(i : std_logic_vector) return cp0_op_t;
   function cp0reg(i : std_logic_vector) return cp0_reg_t;
 
end mips1;
 
package body mips1 is
 
   function op(i : std_logic_vector) return op_t is
   begin
      case i(31 downto 26) is
         when "000000" => return AD;    -- Operations with AluOp
         when "000001" => return RI;    -- Additional Branches
         when "000010" => return J;     -- Jump
         when "000011" => return JAL;   -- Jump And Link to $ra
         when "000100" => return BEQ;   -- Branch On Equal
         when "000101" => return BNE;   -- Branch On Not Equal
         when "000110" => return BLEZ;  -- Branch Less Equal Zero
         when "000111" => return BGTZ;  -- Branch Greater Than Zero
         when "001000" => return ADDI;  -- Add Immediate
         when "001001" => return ADDIU; -- Add Immediate Unsigned
         when "001010" => return SLTI;  -- SLT Immediate
         when "001011" => return SLTIU; -- SLT Immediate Unsigned
         when "001100" => return ANDI;  -- And Immediate
         when "001101" => return ORI;   -- Or Immediate
         when "001110" => return XORI;  -- Xor Immediate
         when "001111" => return LUI;   -- Load Upper Immediate
         when "100000" => return LB;    -- Load Byte
         when "100001" => return LH;    -- Load Half Word
         when "100011" => return LW;    -- Load Word
         when "100100" => return LBU;   -- Load Byte Unsigned
         when "100101" => return LHU;   -- Load Half Word Unsigned
         when "101000" => return SB;    -- Store Byte
         when "101001" => return SH;    -- Store Half Word
         when "101011" => return SW;    -- Store Word
         when "010000" => return CP0;   -- Co-Processor 0 Operations
         when others   => return ERR;   -- Unknown OP
      end case;
   end op;
 
   function aluop(i : std_logic_vector) return alu_op_t is
   begin
      case i(5 downto 0) is
         when "100000" => return ADD;  -- Addition
         when "100001" => return ADDU; -- Add Unsigned
         when "100010" => return SUB;  -- Subtract
         when "100011" => return SUBU; -- Subtract Unsigned
         when "100100" => return AND0; -- Logic and
         when "100101" => return OR0;  -- Logic or
         when "100111" => return NOR0; -- Logic nor
         when "100110" => return XOR0; -- Logic xor
         when "101010" => return SLT;  -- Set On Less Than
         when "101011" => return SLTU; -- SLT Unsigned
         when "000000" => return SLL0; -- Shift Left Logical
         when "000100" => return SLLV; -- SLL Variable
         when "000011" => return SRA0; -- Shift Right Arith
         when "000111" => return SRAV; -- SRA Variable
         when "000010" => return SRL0; -- Shift Right Logical
         when "000110" => return SRLV; -- SRL Variable
         when "001001" => return JALR; -- Jump And Link Reg
         when "001000" => return JR;   -- Jump Reg
         when others   => return ERR;  -- Unknown ALU OP
      end case;
   end aluop;
 
   function rimmop(i : std_logic_vector) return rimm_op_t is
   begin
      case i(20 downto 16) is
      when "00001" => return BGEZ;   -- Branch Greater Equal 0
      when "10001" => return BGEZAL; -- BGEZ And Link
      when "00000" => return BLTZ;   -- Branch Less Than 0
      when "10000" => return BLTZAL; -- BLTZ And Link
      when others  => return ERR;    -- Unknown RIMM OP
      end case;
   end rimmop;
 
   function cp0op(i : std_logic_vector) return cp0_op_t is
   begin
      case i(25 downto 21) is
      when "00000" => return MFCP0; -- Move From Co-Processor 0
      when "00100" => return MTCP0; -- Move To Co-Processor 0
      when "10000" => return RFE;   -- Restore From Exception
      when others  => return ERR;   -- Unknown CP0 OP
      end case;
   end cp0op;
 
   function cp0reg(i : std_logic_vector) return cp0_reg_t is
   begin
      case i(4 downto 0) is
      when "01100" => return SR;    -- Status Register
      when "01101" => return CAUSE; -- Cause Register
      when "01110" => return EPC;   -- EPC
      when others  => return ERR;   -- Unknown CP0 REG
      end case;
   end cp0reg;
 
end mips1;

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[/] [layer2/] [trunk/] [vhdl/] [cpu/] [rtl/] [mips1.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	idiolatrie	`--------------------------------------------------------------------------------`
2			`-- MIPS� I CPU - Instruction Set --`
3			`--------------------------------------------------------------------------------`
4			`-- Type definitions of the MIPS� I instruction (sub-)set and some convenience --`
5			`-- functions to convert binary operation representations to symbolic --`
6			`-- equivalents. --`
7			`-- --`
8			`--------------------------------------------------------------------------------`
9			`-- Copyright (C)2011 Mathias H�rtnagl <mathias.hoertnagl@gmail.comt> --`
10			`-- --`
11			`-- This program is free software: you can redistribute it and/or modify --`
12			`-- it under the terms of the GNU General Public License as published by --`
13			`-- the Free Software Foundation, either version 3 of the License, or --`
14			`-- (at your option) any later version. --`
15			`-- --`
16			`-- This program is distributed in the hope that it will be useful, --`
17			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of --`
18			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --`
19			`-- GNU General Public License for more details. --`
20			`-- --`
21			`-- You should have received a copy of the GNU General Public License --`
22			`-- along with this program. If not, see <http://www.gnu.org/licenses/>. --`
23			`--------------------------------------------------------------------------------`
24			`library ieee;`
25			`use ieee.std_logic_1164.all;`
26			`use ieee.numeric_std.all;`
27
28			`package mips1 is`
29
30			`-----------------------------------------------------------------------------`
31			`-- OP Codes --`
32			`-----------------------------------------------------------------------------`
33			`type op_t is (`
34			`AD, -- Operations with AluOp`
35			`RI, -- Additional Branches`
36			`J, -- Jump`
37			`JAL, -- Jump And Link to $ra`
38			`BEQ, -- Branch On Equal`
39			`BNE, -- Branch On Not Equal`
40			`BLEZ, -- Branch Less Equal Zero`
41			`BGTZ, -- Branch Greater Than Zero`
42			`ADDI, -- Add Immediate`
43			`ADDIU, -- Add Immediate Unsigned`
44			`SLTI, -- SLT Immediate`
45			`SLTIU, -- SLT Immediate Unsigned`
46			`ANDI, -- And Immediate`
47			`ORI, -- Or Immediate`
48			`XORI, -- Xor Immediate`
49			`LUI, -- Load Upper Immediate`
50			`LB, -- Load Byte`
51			`LH, -- Load Half Word`
52			`LW, -- Load Word`
53			`LBU, -- Load Byte Unsigned`
54			`LHU, -- Load Half Word Unsigned`
55			`SB, -- Store Byte`
56			`SH, -- Store Half Word`
57			`SW, -- Store Word`
58			`CP0, -- Co-Processor 0 Operations`
59			`ERR -- Unknown OP`
60			`);`
61
62			`function op(i : std_logic_vector) return op_t;`
63
64			`-----------------------------------------------------------------------------`
65			`-- ALU OP Codes --`
66			`-----------------------------------------------------------------------------`
67			`-- In this implementation of the MIPS� I instruction set, ADD, ADDU and --`
68			`-- SUB, SUBU cause indentical behaviour. This means that ADDU and SUBU do --`
69			`-- NOT trap on overflow. --`
70			`-----------------------------------------------------------------------------`
71			`type alu_op_t is (`
72			`ADD, -- Addition`
73			`ADDU, -- Add Unsigned`
74			`SUB, -- Subtraction`
75			`SUBU, -- Subtract Unsigned`
76			`AND0, -- Logic and`
77			`OR0, -- Logic or`
78			`NOR0, -- Logic nor`
79			`XOR0, -- Logic xor`
80			`SLT, -- Set On Less Than`
81			`SLTU, -- SLT Unsigned`
82			`SLL0, -- Shift Left Logical`
83			`SLLV, -- SLL Variable`
84			`SRA0, -- Shift Right Arith`
85			`SRAV, -- SRA Variable`
86			`SRL0, -- Shift Right Logical`
87			`SRLV, -- SRL Variable`
88			`JALR, -- Jump And Link Reg`
89			`JR, -- Jump Reg`
90			`MFCP0, -- Move From Co-Processor 0`
91			`MTCP0, -- Move To Co-Processor 0`
92			`RFE, -- Restore From Exception`
93			`ERR -- Unknown ALU OP`
94			`);`
95
96			`-- Convert ALU Op bit pattern into its symbolic representation.`
97			`function aluop(i : std_logic_vector) return alu_op_t;`
98
99			`-----------------------------------------------------------------------------`
100			`-- REGIMM Codes --`
101			`-----------------------------------------------------------------------------`
102			`type rimm_op_t is (`
103			`BGEZ, -- Branch Greater Equal 0`
104			`BGEZAL, -- BGEZ And Link`
105			`BLTZ, -- Branch Less Than 0`
106			`BLTZAL, -- BLTZ And Link`
107			`ERR -- Unknown RIMM OP`
108			`);`
109
110			`-- Convert Reg Immediate Op bit pattern into its symbolic representation.`
111			`function rimmop(i : std_logic_vector) return rimm_op_t;`
112
113			`-----------------------------------------------------------------------------`
114			`-- CP0 Codes --`
115			`-----------------------------------------------------------------------------`
116			`type cp0_op_t is (`
117			`MFCP0, -- Move From Co-Processor 0`
118			`MTCP0, -- Move To Co-Processor 0`
119			`RFE, -- Restore From Exception`
120			`ERR -- Unknown CP0 OP`
121			`);`
122
123			`type cp0_reg_t is (`
124			`SR, -- Status Register`
125			`CAUSE, -- Cause Register`
126			`EPC, -- EPC`
127			`ERR -- Unknown CP0 REG`
128			`);`
129
130			`-- Convert CP0 Op and Reg Addresses bit patterns into its symbolic`
131			`-- representation.`
132			`function cp0op(i : std_logic_vector) return cp0_op_t;`
133			`function cp0reg(i : std_logic_vector) return cp0_reg_t;`
134
135			`end mips1;`
136
137			`package body mips1 is`
138
139			`function op(i : std_logic_vector) return op_t is`
140			`begin`
141			`case i(31 downto 26) is`
142			`when "000000" => return AD; -- Operations with AluOp`
143			`when "000001" => return RI; -- Additional Branches`
144			`when "000010" => return J; -- Jump`
145			`when "000011" => return JAL; -- Jump And Link to $ra`
146			`when "000100" => return BEQ; -- Branch On Equal`
147			`when "000101" => return BNE; -- Branch On Not Equal`
148			`when "000110" => return BLEZ; -- Branch Less Equal Zero`
149			`when "000111" => return BGTZ; -- Branch Greater Than Zero`
150			`when "001000" => return ADDI; -- Add Immediate`
151			`when "001001" => return ADDIU; -- Add Immediate Unsigned`
152			`when "001010" => return SLTI; -- SLT Immediate`
153			`when "001011" => return SLTIU; -- SLT Immediate Unsigned`
154			`when "001100" => return ANDI; -- And Immediate`
155			`when "001101" => return ORI; -- Or Immediate`
156			`when "001110" => return XORI; -- Xor Immediate`
157			`when "001111" => return LUI; -- Load Upper Immediate`
158			`when "100000" => return LB; -- Load Byte`
159			`when "100001" => return LH; -- Load Half Word`
160			`when "100011" => return LW; -- Load Word`
161			`when "100100" => return LBU; -- Load Byte Unsigned`
162			`when "100101" => return LHU; -- Load Half Word Unsigned`
163			`when "101000" => return SB; -- Store Byte`
164			`when "101001" => return SH; -- Store Half Word`
165			`when "101011" => return SW; -- Store Word`
166			`when "010000" => return CP0; -- Co-Processor 0 Operations`
167			`when others => return ERR; -- Unknown OP`
168			`end case;`
169			`end op;`
170
171			`function aluop(i : std_logic_vector) return alu_op_t is`
172			`begin`
173			`case i(5 downto 0) is`
174			`when "100000" => return ADD; -- Addition`
175			`when "100001" => return ADDU; -- Add Unsigned`
176			`when "100010" => return SUB; -- Subtract`
177			`when "100011" => return SUBU; -- Subtract Unsigned`
178			`when "100100" => return AND0; -- Logic and`
179			`when "100101" => return OR0; -- Logic or`
180			`when "100111" => return NOR0; -- Logic nor`
181			`when "100110" => return XOR0; -- Logic xor`
182			`when "101010" => return SLT; -- Set On Less Than`
183			`when "101011" => return SLTU; -- SLT Unsigned`
184			`when "000000" => return SLL0; -- Shift Left Logical`
185			`when "000100" => return SLLV; -- SLL Variable`
186			`when "000011" => return SRA0; -- Shift Right Arith`
187			`when "000111" => return SRAV; -- SRA Variable`
188			`when "000010" => return SRL0; -- Shift Right Logical`
189			`when "000110" => return SRLV; -- SRL Variable`
190			`when "001001" => return JALR; -- Jump And Link Reg`
191			`when "001000" => return JR; -- Jump Reg`
192			`when others => return ERR; -- Unknown ALU OP`
193			`end case;`
194			`end aluop;`
195
196			`function rimmop(i : std_logic_vector) return rimm_op_t is`
197			`begin`
198			`case i(20 downto 16) is`
199			`when "00001" => return BGEZ; -- Branch Greater Equal 0`
200			`when "10001" => return BGEZAL; -- BGEZ And Link`
201			`when "00000" => return BLTZ; -- Branch Less Than 0`
202			`when "10000" => return BLTZAL; -- BLTZ And Link`
203			`when others => return ERR; -- Unknown RIMM OP`
204			`end case;`
205			`end rimmop;`
206
207			`function cp0op(i : std_logic_vector) return cp0_op_t is`
208			`begin`
209			`case i(25 downto 21) is`
210			`when "00000" => return MFCP0; -- Move From Co-Processor 0`
211			`when "00100" => return MTCP0; -- Move To Co-Processor 0`
212			`when "10000" => return RFE; -- Restore From Exception`
213			`when others => return ERR; -- Unknown CP0 OP`
214			`end case;`
215			`end cp0op;`
216
217			`function cp0reg(i : std_logic_vector) return cp0_reg_t is`
218			`begin`
219			`case i(4 downto 0) is`
220			`when "01100" => return SR; -- Status Register`
221			`when "01101" => return CAUSE; -- Cause Register`
222			`when "01110" => return EPC; -- EPC`
223			`when others => return ERR; -- Unknown CP0 REG`
224			`end case;`
225			`end cp0reg;`
226
227			`end mips1;`