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idiolatrie |
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-- MIPS™ I CPU - Type Definitions --
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-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
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-- --
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-- This program is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.mips1.all;
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package tcpu is
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component gpr is
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port(
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clk_i : in std_logic;
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hld_i : in std_logic;
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rs_a : in std_logic_vector(4 downto 0);
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rt_a : in std_logic_vector(4 downto 0);
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rd_a : in std_logic_vector(4 downto 0);
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rd_we : in std_logic;
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rd_i : in std_logic_vector(31 downto 0);
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rs_o : out std_logic_vector(31 downto 0);
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rt_o : out std_logic_vector(31 downto 0)
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);
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end component;
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-----------------------------------------------------------------------------
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-- MEMORY STAGE --
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-----------------------------------------------------------------------------
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type wc_t is record
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we : std_logic; -- Write back enable.
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end record;
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type me_t is record
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wc : wc_t; -- Write Back Stage control.
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rd : std_logic_vector(4 downto 0); -- Write back register address.
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res : std_logic_vector(31 downto 0); -- Write back data (ALU or Memory).
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end record;
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-----------------------------------------------------------------------------
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-- EXECUTION STAGE --
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-----------------------------------------------------------------------------
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type mem_ext_t is (ZERO, SIGN);
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type mem_byt_t is (NONE, BYTE, HALF, WORD);
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type jadr_t is record
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j : unsigned(31 downto 2); -- Jump/Branch address.
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jmp : std_logic; -- Jump or don't jump. That's ...
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end record;
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type mem_t is record
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we : std_logic; -- Stored data write enable.
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ext : mem_ext_t; -- Loaded Data extension.
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byt : mem_byt_t; -- Data width.
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end record;
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type ret_t is (ALU, MEM);
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type mc_t is record
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src : ret_t; -- Either ALU or Memory result.
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mem : mem_t; -- Load/Store control signals.
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end record;
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type ex_t is record
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mc : mc_t; -- Memory Stage control.
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wc : wc_t; -- Write Back Stage control.
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rd : std_logic_vector(4 downto 0); -- Write back register address.
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f : jadr_t; -- Jump/Branch information for IF.
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str : std_logic_vector(31 downto 0); -- ALU source B saved to memory.
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res : std_logic_vector(31 downto 0); -- ALU result.
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end record;
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-----------------------------------------------------------------------------
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-- DECODE STAGE --
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-----------------------------------------------------------------------------
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type jmp_op_t is (NOP, JMP, EQ, NEQ, GTZ, LTZ, GEZ, LEZ);
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type jmp_src_t is (REG, JMP, BRA);
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type jmp_t is record
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op : jmp_op_t; -- Possible branching conditions.
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src : jmp_src_t; -- Possile jump/branch sources.
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end record;
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type alu_src_a_t is (SH_CONST, SH_16, ADD_4, REG);
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type alu_src_b_t is (ZERO, SIGN, PC, REG);
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type alu_src_t is record
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a : alu_src_a_t; -- Sources for input A.
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b : alu_src_b_t; -- Sources for input B.
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end record;
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type alu_t is record
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op : alu_op_t; -- ALU Ops [Mips1.vhd]
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src : alu_src_t; -- ALU sources.
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end record;
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type wbr_t is (RD, RT, RA); -- Possible write back addresses.
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type ec_t is record
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wbr : wbr_t; -- Write back register type.
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alu : alu_t; -- ALU control signals.
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jmp : jmp_t; -- Jump/Branch control signals.
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end record;
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type cc_t is record
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mtsr : boolean; -- CP0 move to SR enable.
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rfe : boolean; -- Restore from exception.
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end record;
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type dc_t is record
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we : std_logic; -- WB forward write enable.
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end record;
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type de_t is record
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cc : cc_t; -- CP0 control.
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dc : dc_t; -- Decode Stage control.
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ec : ec_t; -- Execution Stage control.
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mc : mc_t; -- Memory Stage control.
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wc : wc_t; -- Write Back Stage control.
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--f : jadr_t; -- J, JAL control signals.
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rd : std_logic_vector(4 downto 0); -- WB forward destination address.
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res : std_logic_vector(31 downto 0); -- WB forward data.
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i : std_logic_vector(25 downto 0); -- Instruction (without OP code).
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end record;
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-----------------------------------------------------------------------------
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-- FETCH STAGE --
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-----------------------------------------------------------------------------
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type fe_t is record
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pc : unsigned(31 downto 2); -- Program counter.
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end record;
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-----------------------------------------------------------------------------
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-- CO-PROCESSOR 0 --
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-----------------------------------------------------------------------------
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type sr_t is record
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im : std_logic_vector(7 downto 0); -- Interrupt mask.
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iec : std_logic; -- IEc: Interrupt enable current.
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iep : std_logic; -- IEp: Interrupt enable previous.
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ieo : std_logic; -- IEo: Interrupt enable old.
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end record;
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type cp0_t is record
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sr : sr_t; -- Status register.
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epc : unsigned(29 downto 0); -- Exception program counter.
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end record;
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end tcpu;
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