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idiolatrie |
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-- Mycron® DDR SDRAM - MT46V32M16 - 8 Meg x 16 x 4 banks --
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--------------------------------------------------------------------------------
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-- Copyright (C)2012 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
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-- --
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-- This program is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ddr_init is
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port (
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clk0 : in std_logic;
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rst : in std_logic;
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SD_CKE : out std_logic;
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SD_BA : out std_logic_vector(1 downto 0);
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SD_A : out std_logic_vector(12 downto 0);
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SD_CMD : out std_logic_vector(3 downto 0);
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init_done : out boolean
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);
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end ddr_init;
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architecture rtl of ddr_init is
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-----------------------------------------------------------------------------
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-- Controller Commands --
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-----------------------------------------------------------------------------
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constant CMD_LMR : std_logic_vector(3 downto 0) := "0000";
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constant CMD_AUTO_REFRESH : std_logic_vector(3 downto 0) := "0001";
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constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010";
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constant CMD_NOP : std_logic_vector(3 downto 0) := "0111";
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-----------------------------------------------------------------------------
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-- Mode Rgister Addresses --
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-----------------------------------------------------------------------------
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-- Addresses for the two mode registers, selected via SD_BA.
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constant BMR_ADDR : std_logic_vector(1 downto 0) := "00";
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constant EMR_ADDR : std_logic_vector(1 downto 0) := "01";
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-----------------------------------------------------------------------------
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-- Base Mode Rgister --
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-----------------------------------------------------------------------------
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-- Operating modes.
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constant OP_NORMAL : std_logic_vector(5 downto 0) := "000000";
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constant OP_DLL_RST : std_logic_vector(5 downto 0) := "000010";
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-- CAS latency.
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constant CAS_2 : std_logic_vector(2 downto 0) := "010";
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-- Burst type.
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constant BT_S : std_logic := '0'; -- Sequential.
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-- Burst lengths.
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constant BL_2 : std_logic_vector(2 downto 0) := "001";
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-----------------------------------------------------------------------------
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-- Extended Mode Rgister --
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-----------------------------------------------------------------------------
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-- DLL.
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constant DLL_ENABLE : std_logic := '0';
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constant DLL_DISABLE : std_logic := '1';
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-- Drive strength.
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constant DS_NORMAL : std_logic := '0';
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-----------------------------------------------------------------------------
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-- Initialization --
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-----------------------------------------------------------------------------
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type init_state_t is (
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Wait20000, -- Wait for 200µs.
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CKE_High, -- Assert CKE.
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Precharge0, Precharge0Wait, -- First precharge.
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ProgramEMR, ProgramEMRWait, -- Set Extended Mode Register.
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ProgramMR, ProgramMRWait, -- Set Base Mode Register.
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Precharge1, Precharge1Wait, -- second precharge.
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AutoRefresh0, AutoRefresh0Wait, -- First autorefresh.
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AutoRefresh1, AutoRefresh1Wait, -- Second autorefresh.
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ProgramMR1, ProgramMR1Wait, -- Set Base Mode Register.
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Wait200, -- Wait for 200 cycles.
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Done -- Initialization done!
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);
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type init_t is record
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s : init_state_t;
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c : natural range 0 to 19999;
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end record;
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constant init_d : init_t := init_t'( Wait20000, 0);
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signal i, iin : init_t := init_d;
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begin
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-----------------------------------------------------------------------------
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-- Initialization --
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-----------------------------------------------------------------------------
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initial : process(i)
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begin
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iin <= i;
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SD_CKE <= '1';
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SD_BA <= "00";
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SD_CMD <= CMD_NOP;
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SD_A <= (others => '0');
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init_done <= false;
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case i.s is
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-----------------------------------------------------------------------
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-- 5. Wait for 200µs. --
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-----------------------------------------------------------------------
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when Wait20000 =>
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SD_CKE <= '0';
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if i.c = 19999 then
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iin.c <= 0;
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iin.s <= CKE_High;
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else
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iin.c <= i.c + 1;
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end if;
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-----------------------------------------------------------------------
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-- 6. Bring CKE high. --
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-----------------------------------------------------------------------
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when CKE_High =>
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iin.s <= Precharge0;
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-----------------------------------------------------------------------
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-- 7. Precharge all banks. --
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-----------------------------------------------------------------------
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when Precharge0 =>
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SD_CMD <= CMD_PRECHARGE;
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SD_A(10) <= '1'; -- Precharge all operation.
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iin.s <= Precharge0Wait;
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-- PRECHARGE command period tRP: 15ns
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when Precharge0Wait =>
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if i.c = 1 then
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iin.c <= 0;
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iin.s <= ProgramEMR;
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else
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iin.c <= i.c + 1;
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end if;
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-----------------------------------------------------------------------
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-- 9. Program the Extended Mode Register. --
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-----------------------------------------------------------------------
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when ProgramEMR =>
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SD_CMD <= CMD_LMR;
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SD_BA <= EMR_ADDR; -- Select Extended Mode Register.
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SD_A <= "00000000000" & DS_NORMAL & DLL_DISABLE;
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iin.s <= ProgramEMRWait;
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-- LOAD MODE REGISTER command cycle time tMRD: 12ns
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when ProgramEMRWait =>
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if i.c = 1 then
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iin.c <= 0;
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iin.s <= ProgramMR;
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else
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iin.c <= i.c + 1;
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end if;
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-----------------------------------------------------------------------
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-- 11. Program the Mode Rgister --
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-----------------------------------------------------------------------
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when ProgramMR =>
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SD_CMD <= CMD_LMR;
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SD_BA <= BMR_ADDR; -- Select Base Mode Register.
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SD_A <= OP_NORMAL & CAS_2 & BT_S & BL_2;
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iin.s <= ProgramMRWait;
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-- LOAD MODE REGISTER command cycle time tMRD: 12ns
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when ProgramMRWait =>
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if i.c = 1 then
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iin.c <= 0;
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iin.s <= Precharge1;
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else
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iin.c <= i.c + 1;
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end if;
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-----------------------------------------------------------------------
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-- 13. Precharge all banks. --
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-----------------------------------------------------------------------
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when Precharge1 =>
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SD_CMD <= CMD_PRECHARGE;
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SD_A(10) <= '1'; -- Precharge all operation.
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iin.s <= Precharge1Wait;
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-- PRECHARGE command period tRP: 15ns
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when Precharge1Wait =>
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if i.c = 1 then
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iin.c <= 0;
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iin.s <= AutoRefresh0;
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else
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iin.c <= i.c + 1;
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end if;
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-----------------------------------------------------------------------
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-- 15. Auto Refresh. --
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-----------------------------------------------------------------------
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when AutoRefresh0 =>
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SD_CMD <= CMD_AUTO_REFRESH;
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iin.s <= AutoRefresh0Wait;
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-- AUTO REFRESH command period tRFC: 72ns
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when AutoRefresh0Wait =>
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if i.c = 7 then
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iin.c <= 0;
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iin.s <= AutoRefresh1;
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else
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iin.c <= i.c + 1;
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end if;
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-----------------------------------------------------------------------
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-- 17. Auto Refresh. --
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-----------------------------------------------------------------------
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when AutoRefresh1 =>
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SD_CMD <= CMD_AUTO_REFRESH;
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iin.s <= AutoRefresh1Wait;
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-- AUTO REFRESH command period tRFC: 72ns
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when AutoRefresh1Wait =>
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if i.c = 7 then
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iin.c <= 0;
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iin.s <= ProgramMR1;
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else
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iin.c <= i.c + 1;
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end if;
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-----------------------------------------------------------------------
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-- 19. Program the Mode Rgister (Clear DLL Bit) --
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-----------------------------------------------------------------------
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when ProgramMR1 =>
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SD_CMD <= CMD_LMR;
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SD_BA <= BMR_ADDR; -- Select Base Mode Register.
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SD_A <= OP_NORMAL & CAS_2 & BT_S & BL_2;
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iin.s <= ProgramMR1Wait;
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-- LOAD MODE REGISTER command cycle time tMRD: 12ns
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when ProgramMR1Wait =>
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if i.c = 1 then
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iin.c <= 0;
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iin.s <= Wait200;
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else
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iin.c <= i.c + 1;
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end if;
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-----------------------------------------------------------------------
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-- 21. Wait for 200 cycles. --
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-----------------------------------------------------------------------
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when Wait200 =>
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if i.c = 199 then
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iin.c <= 0;
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iin.s <= Done;
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else
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iin.c <= i.c + 1;
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end if;
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-----------------------------------------------------------------------
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-- Initialization done. --
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-----------------------------------------------------------------------
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when Done =>
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init_done <= true;
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end case;
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end process;
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-----------------------------------------------------------------------------
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-- Register --
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-----------------------------------------------------------------------------
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reg : process(clk0)
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begin
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if rising_edge(clk0) then
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if rst = '1' then i <= init_d; else i <= iin; end if;
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end if;
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end process;
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end rtl;
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