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idiolatrie |
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-- Wishbone Shared Bus Intercon --
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--------------------------------------------------------------------------------
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-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
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-- --
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-- This program is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.icon.all;
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use work.iwb.all;
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entity intercon is
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port(
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CLK50_I : in std_logic;
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CLK25_I : in std_logic;
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RST_I : in std_logic;
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mi : out master_in_t;
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mo : in master_out_t;
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brami : out slave_in_t;
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bramo : in slave_out_t;
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flasi : out slave_in_t;
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flaso : in slave_out_t;
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ddri : out slave_in_t;
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ddro : in slave_out_t;
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dispi : out slave_in_t;
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dispo : in slave_out_t;
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keybi : out slave_in_t;
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keybo : in slave_out_t;
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piti : out slave_in_t;
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pito : in slave_out_t;
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uartri : out slave_in_t;
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uartro : in slave_out_t;
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uartti : out slave_in_t;
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uartto : in slave_out_t
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);
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end intercon;
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architecture sbus of intercon is
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-- Set default slave signals.
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function setDefault(mo : master_out_t; CLK, RST : std_logic)
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return slave_in_t is
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variable v : slave_in_t;
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begin
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v.clk := CLK;
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v.rst := RST;
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v.stb := '0';
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v.we := '0';
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v.dat := mo.dat;
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v.sel := mo.sel;
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v.adr := mo.adr;
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return v;
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end setDefault;
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begin
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mux : process(CLK50_I, RST_I, mo, bramo, dispo, keybo, pito, flaso, uartro,
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uartto, ddro, CLK25_I)
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variable padr : std_logic_vector(27 downto 0);
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begin
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mi.clk <= CLK50_I;
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mi.rst <= RST_I;
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mi.dat <= (others => '0');
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-- NOTE: Set mi.ack = '1' if you want to continue execution outside the
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-- valid address space. If set to zero and your programm reads or
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-- writes outside the specified addresses the cpu waits infinitly
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-- for an acknolege.
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mi.ack <= '0';
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brami <= setDefault(mo, CLK50_I, RST_I);
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flasi <= setDefault(mo, CLK50_I, RST_I);
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ddri <= setDefault(mo, CLK50_I, RST_I);
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dispi <= setDefault(mo, CLK50_I, RST_I);
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keybi <= setDefault(mo, CLK50_I, RST_I);
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piti <= setDefault(mo, CLK50_I, RST_I);
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uartri <= setDefault(mo, CLK50_I, RST_I);
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uartti <= setDefault(mo, CLK50_I, RST_I);
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padr := mo.adr(27 downto 0);
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case mo.adr(31 downto 28) is
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-----------------------------------------------------------------------
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-- Block Memory --
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-----------------------------------------------------------------------
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when X"0" =>
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-- if (padr >= X"0000000") and (padr < X"0004000") then
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brami.stb <= mo.stb;
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brami.we <= mo.we;
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mi.dat <= bramo.dat;
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mi.ack <= bramo.ack;
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-- end if;
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-----------------------------------------------------------------------
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-- Flash Memory --
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-----------------------------------------------------------------------
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when X"1" =>
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--if (padr >= X"0000000") and (padr < X"1000000") then
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flasi.stb <= mo.stb;
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flasi.we <= mo.we;
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mi.dat <= flaso.dat;
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mi.ack <= flaso.ack;
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--end if;
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-----------------------------------------------------------------------
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-- DDR2 Memory --
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-----------------------------------------------------------------------
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when x"2" =>
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ddri.stb <= mo.stb;
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ddri.we <= mo.we;
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mi.dat <= ddro.dat;
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mi.ack <= ddro.ack;
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-----------------------------------------------------------------------
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-- Peripheral IO --
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-----------------------------------------------------------------------
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when X"F" =>
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--------------------------------------------------------------------
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-- Display --
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--------------------------------------------------------------------
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-- 4096 blocks, 16bit per block = 8192 (0x2000)
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if (padr >= X"FFF0000") and (padr < X"FFF2000") then
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dispi.stb <= mo.stb;
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dispi.we <= mo.we;
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mi.dat <= dispo.dat;
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mi.ack <= dispo.ack;
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-- NOTE: The following addresses are strict. If you try to load or
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-- store a halfword or a byte, the addresses obviously do NOT
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-- match.
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--------------------------------------------------------------------
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-- Keyboard --
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--------------------------------------------------------------------
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-- 1 block, 32bit, read only
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elsif padr = X"FFF3000" then
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keybi.stb <= mo.stb;
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keybi.we <= mo.we;
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mi.dat <= keybo.dat;
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mi.ack <= keybo.ack;
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--------------------------------------------------------------------
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-- RS-232 Serial Port --
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--------------------------------------------------------------------
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-- 1 block, 32bit, read only
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elsif padr = X"FFF4000" then
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uartri.stb <= mo.stb;
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uartri.we <= mo.we;
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mi.dat <= uartro.dat;
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mi.ack <= uartro.ack;
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-- 1 block, 32bit, write only
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elsif padr = X"FFF4004" then
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uartti.stb <= mo.stb;
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uartti.we <= mo.we;
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mi.dat <= uartto.dat;
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mi.ack <= uartto.ack;
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--------------------------------------------------------------------
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-- Timer --
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--------------------------------------------------------------------
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-- 1 block, 32bit, r/w
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elsif padr = X"FFFF000" then
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piti.stb <= mo.stb;
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piti.we <= mo.we;
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mi.dat <= pito.dat;
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mi.ack <= pito.ack;
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end if;
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when others =>
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end case;
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end process;
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end sbus;
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