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[/] [layer2/] [trunk/] [vhdl/] [rs232/] [rtl/] [counter.vhd] - Blame information for rev 4
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idiolatrie |
--------------------------------------------------------------------------------
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-- Baud Rate Counter --
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--------------------------------------------------------------------------------
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-- Copyright (C)2011 Mathias Hörtnagl <mathias.hoertnagl@gmail.comt> --
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-- --
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-- This program is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity counter is
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generic(
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FREQ : positive := 50; -- Clock frequency in MHz.
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RATE : positive := 19200 -- Baud rate (times sampling rate).
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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tick : out std_logic
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);
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end counter;
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architecture rtl of counter is
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constant MAX : positive := (FREQ*1000000)/(RATE*16);
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signal c, cin : natural range 0 to MAX;
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begin
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tick <= '1' when c = MAX else '0';
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cin <= 0 when c = MAX else c + 1;
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reg : process (clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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c <= 0;
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else
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c <= cin;
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end if;
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end if;
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end process;
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end rtl;
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