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[/] [layer2/] [trunk/] [vhdl/] [rs232/] [rtl/] [uartt.vhd] - Blame information for rev 2

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--------------------------------------------------------------------------------
-- UART Transmitter 19200/8N1                                                 --
--------------------------------------------------------------------------------
-- Copyright (C)2011  Mathias H�rtnagl <mathias.hoertnagl@gmail.comt>         --
--                                                                            --
-- This program is free software: you can redistribute it and/or modify       --
-- it under the terms of the GNU General Public License as published by       --
-- the Free Software Foundation, either version 3 of the License, or          --
-- (at your option) any later version.                                        --
--                                                                            --
-- This program is distributed in the hope that it will be useful,            --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --
-- GNU General Public License for more details.                               --
--                                                                            --
-- You should have received a copy of the GNU General Public License          --
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.      --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library work;
use work.iwb.all;
use work.iuart.all;
 
entity uartt is
   port(
      si            : in  slave_in_t;
      so            : out slave_out_t;
   -- Non-Wishbone Signals
      RS232_DCE_TXD : out std_logic
   );
end uartt;
 
architecture rtl of uartt is
 
   type state_t is (Idle, Start, Data, Stop, Ack);
 
   type sender_t is record
      s : state_t;                           -- Sender state.
      n : natural range 0 to 15;             -- Tick counter.
      m : natural range 0 to 7;              -- Data bits counter.
      d : std_logic_vector(7 downto 0);      -- Data bits shift register.
   end record;
 
   type tx_t is record
      tick : std_logic;
      rst  : std_logic;
      ack  : std_logic;
   end record;
 
   signal snd, sndin : sender_t;
   signal tx : tx_t;
begin
 
   -----------------------------------------------------------------------------
   -- Transmitter Rate Generator                                              --
   -----------------------------------------------------------------------------
   tx_rate : counter
      generic map(
         FREQ => 50,
         RATE => 19200
      )
      port map(
         clk  => si.clk,
         rst  => tx.rst,
         tick => tx.tick
      );
 
   -----------------------------------------------------------------------------
   -- Transmitter Controller                                                  --
   -----------------------------------------------------------------------------
   receiver : process(snd, tx.tick, si)
   begin
 
      sndin         <= snd;
      tx.rst        <= '0';
      tx.ack        <= '0';
      RS232_DCE_TXD <= '1';                     -- Idle line is alwasys '1'.
 
      case snd.s is
         when Idle =>
            tx.rst <= '1';
            if wb_write(si) then
               sndin.n <= 0;
               sndin.d <= si.dat(7 downto 0);
               sndin.s <= Start;
            end if;
 
         when Start =>
            RS232_DCE_TXD <= '0';
            if tx.tick = '1' then
               if snd.n = 15 then
                  sndin.n <= 0;
                  sndin.m <= 0;
                  sndin.s <= Data;
               else
                  sndin.n <= snd.n + 1;
               end if;
            end if;
 
         when Data =>
            RS232_DCE_TXD <= snd.d(0);
            if tx.tick = '1' then
               if snd.n = 15 then
                  sndin.n <= 0;
                  sndin.d <= '0' & snd.d(7 downto 1);
                  if snd.m = 7 then
                     sndin.s <= Stop;
                  else
                     sndin.m <= snd.m + 1;
                  end if;
               else
                  sndin.n <= snd.n + 1;
               end if;
            end if;
 
         when Stop =>
            if tx.tick = '1' then
               if snd.n = 15 then
                  sndin.s <= Ack;
               else
                  sndin.n <= snd.n + 1;
               end if;
            end if;
 
         when Ack =>
            tx.ack <= '1';
            if si.stb = '0' then
               sndin.s <= Idle;
            end if;
 
      end case;
   end process;
 
   so.dat <= (others => '-');
   so.ack <= tx.ack;
 
   -----------------------------------------------------------------------------
   -- Registers                                                               --
   -----------------------------------------------------------------------------
   reg : process(si.clk)
   begin
      if rising_edge(si.clk) then
         snd <= sndin;
         if si.rst = '1' then
            snd.s <= Idle;
         end if;
      end if;
   end process;
end rtl;

Line No.	Rev	Author	Line
1	2	idiolatrie	`--------------------------------------------------------------------------------`
2			`-- UART Transmitter 19200/8N1 --`
3			`--------------------------------------------------------------------------------`
4			`-- Copyright (C)2011 Mathias H�rtnagl <mathias.hoertnagl@gmail.comt> --`
5			`-- --`
6			`-- This program is free software: you can redistribute it and/or modify --`
7			`-- it under the terms of the GNU General Public License as published by --`
8			`-- the Free Software Foundation, either version 3 of the License, or --`
9			`-- (at your option) any later version. --`
10			`-- --`
11			`-- This program is distributed in the hope that it will be useful, --`
12			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of --`
13			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --`
14			`-- GNU General Public License for more details. --`
15			`-- --`
16			`-- You should have received a copy of the GNU General Public License --`
17			`-- along with this program. If not, see <http://www.gnu.org/licenses/>. --`
18			`--------------------------------------------------------------------------------`
19			`library ieee;`
20			`use ieee.std_logic_1164.all;`
21			`use ieee.numeric_std.all;`
22
23			`library work;`
24			`use work.iwb.all;`
25			`use work.iuart.all;`
26
27			`entity uartt is`
28			`port(`
29			`si : in slave_in_t;`
30			`so : out slave_out_t;`
31			`-- Non-Wishbone Signals`
32			`RS232_DCE_TXD : out std_logic`
33			`);`
34			`end uartt;`
35
36			`architecture rtl of uartt is`
37
38			`type state_t is (Idle, Start, Data, Stop, Ack);`
39
40			`type sender_t is record`
41			`s : state_t; -- Sender state.`
42			`n : natural range 0 to 15; -- Tick counter.`
43			`m : natural range 0 to 7; -- Data bits counter.`
44			`d : std_logic_vector(7 downto 0); -- Data bits shift register.`
45			`end record;`
46
47			`type tx_t is record`
48			`tick : std_logic;`
49			`rst : std_logic;`
50			`ack : std_logic;`
51			`end record;`
52
53			`signal snd, sndin : sender_t;`
54			`signal tx : tx_t;`
55			`begin`
56
57			`-----------------------------------------------------------------------------`
58			`-- Transmitter Rate Generator --`
59			`-----------------------------------------------------------------------------`
60			`tx_rate : counter`
61			`generic map(`
62			`FREQ => 50,`
63			`RATE => 19200`
64			`)`
65			`port map(`
66			`clk => si.clk,`
67			`rst => tx.rst,`
68			`tick => tx.tick`
69			`);`
70
71			`-----------------------------------------------------------------------------`
72			`-- Transmitter Controller --`
73			`-----------------------------------------------------------------------------`
74			`receiver : process(snd, tx.tick, si)`
75			`begin`
76
77			`sndin <= snd;`
78			`tx.rst <= '0';`
79			`tx.ack <= '0';`
80			`RS232_DCE_TXD <= '1'; -- Idle line is alwasys '1'.`
81
82			`case snd.s is`
83			`when Idle =>`
84			`tx.rst <= '1';`
85			`if wb_write(si) then`
86			`sndin.n <= 0;`
87			`sndin.d <= si.dat(7 downto 0);`
88			`sndin.s <= Start;`
89			`end if;`
90
91			`when Start =>`
92			`RS232_DCE_TXD <= '0';`
93			`if tx.tick = '1' then`
94			`if snd.n = 15 then`
95			`sndin.n <= 0;`
96			`sndin.m <= 0;`
97			`sndin.s <= Data;`
98			`else`
99			`sndin.n <= snd.n + 1;`
100			`end if;`
101			`end if;`
102
103			`when Data =>`
104			`RS232_DCE_TXD <= snd.d(0);`
105			`if tx.tick = '1' then`
106			`if snd.n = 15 then`
107			`sndin.n <= 0;`
108			`sndin.d <= '0' & snd.d(7 downto 1);`
109			`if snd.m = 7 then`
110			`sndin.s <= Stop;`
111			`else`
112			`sndin.m <= snd.m + 1;`
113			`end if;`
114			`else`
115			`sndin.n <= snd.n + 1;`
116			`end if;`
117			`end if;`
118
119			`when Stop =>`
120			`if tx.tick = '1' then`
121			`if snd.n = 15 then`
122			`sndin.s <= Ack;`
123			`else`
124			`sndin.n <= snd.n + 1;`
125			`end if;`
126			`end if;`
127
128			`when Ack =>`
129			`tx.ack <= '1';`
130			`if si.stb = '0' then`
131			`sndin.s <= Idle;`
132			`end if;`
133
134			`end case;`
135			`end process;`
136
137			`so.dat <= (others => '-');`
138			`so.ack <= tx.ack;`
139
140			`-----------------------------------------------------------------------------`
141			`-- Registers --`
142			`-----------------------------------------------------------------------------`
143			`reg : process(si.clk)`
144			`begin`
145			`if rising_edge(si.clk) then`
146			`snd <= sndin;`
147			`if si.rst = '1' then`
148			`snd.s <= Idle;`
149			`end if;`
150			`end if;`
151			`end process;`
152			`end rtl;`

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[/] [layer2/] [trunk/] [vhdl/] [rs232/] [rtl/] [uartt.vhd] - Blame information for rev 2