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URL https://opencores.org/ocsvn/layer2/layer2/trunk

Subversion Repositories layer2

[/] [layer2/] [trunk/] [xilinx/] [layer2.prj] - Blame information for rev 9

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Line No. Rev Author Line
1 4 idiolatrie
vhdl work "../vhdl/intercon/rtl/iwb.vhd"
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vhdl work "../vhdl/cpu/rtl/mips1.vhd"
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vhdl work "../vhdl/mem/rtl/imem.vhd"
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vhdl work "../vhdl/cpu/rtl/tcpu.vhd"
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vhdl work "../vhdl/vga/rtl/rom.vhd"
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vhdl work "../vhdl/vga/rtl/ram.vhd"
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vhdl work "../vhdl/rs232/rtl/iuart.vhd"
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vhdl work "../vhdl/rs232/rtl/counter.vhd"
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vhdl work "../vhdl/keyb/rtl/ps2.vhd"
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vhdl work "../vhdl/keyb/rtl/ascii.vhd"
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vhdl work "../vhdl/intercon/rtl/icon.vhd"
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vhdl work "../vhdl/ddr/rtl/iddr.vhd"
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vhdl work "../vhdl/ddr/rtl/ddr_init.vhd"
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vhdl work "../vhdl/cpu/rtl/icpu.vhd"
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vhdl work "../vhdl/cpu/rtl/gpr.vhd"
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vhdl work "../vhdl/cpu/rtl/fcpu.vhd"
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vhdl work "../sw/bin/data.vhd"
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vhdl work "clock.vhd"
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vhdl work "../vhdl/vga/rtl/vga.vhd"
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vhdl work "../vhdl/vga/rtl/ivga.vhd"
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vhdl work "../vhdl/rs232/rtl/uartt.vhd"
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vhdl work "../vhdl/rs232/rtl/uartr.vhd"
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vhdl work "../vhdl/pit/rtl/pit.vhd"
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vhdl work "../vhdl/pit/rtl/ipit.vhd"
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vhdl work "../vhdl/mem/rtl/mem.vhd"
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vhdl work "../vhdl/keyb/rtl/keyb.vhd"
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vhdl work "../vhdl/keyb/rtl/ikeyb.vhd"
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vhdl work "../vhdl/intercon/rtl/intercon.vhd"
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vhdl work "../vhdl/flash/rtl/iflash.vhd"
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vhdl work "../vhdl/flash/rtl/flash.vhd"
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vhdl work "../vhdl/ddr/rtl/ddr.vhd"
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vhdl work "../vhdl/cpu/rtl/wbm.vhd"
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vhdl work "../vhdl/cpu/rtl/iwbm.vhd"
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vhdl work "../vhdl/cpu/rtl/cpu.vhd"
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vhdl work "layer2.vhd"

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