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<html>
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<head>
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<title>OPENCORES.ORG</title>
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<META NAME="keywords" CONTENT="cores, VHDL, Verilog HDL, ASIC, Synthesizable,
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standard cell, IP, Intellectual Property, 32-bit RISC, UART, PCI, SDRAM,
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designs, developers, C, Linux, eCos, open, free, open source cores, RTL code,
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system-on-a-chip, circuits, digital, GNU, GPL, core, controller, processor,
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system design, chip design, EDA, design methodology, design tools, ASICs, programmable logic,
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FPGA's, PLDs, CPLDs, verification, Synthesis, HDL, Simulation, IC design software,
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semiconductor design, integrated circuits, system designs, chip designs, EDAs,
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design methodologies, design tool, ASIC, programmable logics, FPGA, PLD, CPLD, Synthesis,
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circuit, Synopsys, system design, chip design, programmable logic, FPGA's, PLDs,
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CPLDs, verification, Simulation">
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<META NAME="description" CONTENT="OPENCORES.ORG endorses development and hosts
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a repository of free, open source IP cores (chip designs, System-on-a-Chip) and
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supplemental boards.">
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</head>
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<body bgcolor=#ffffff>
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<table width="100%" cellspacing=5 cellpadding=0 border=0>
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<tr valign="top"><td>
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<center>
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<table cellspacing=0 cellpadding=5 width="100%" valign="top" border=0>
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<tr valign="top"><td bgcolor=#f0f0f0 valign="top">
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<center><font size=+3><b>OPENCORES.ORG</b></font>
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<br><font size=-4><font color=#ffffff>.</font></font>
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<br>
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</center>
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</td></tr></table>
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</center>
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</td></tr>
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<tr valign="top"><td>
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<table border=0 cellspacing=0 cellpadding=5 width="100%"><tr valign="top"><td bgcolor="#f8f8f0">
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</td>
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<td valign="top">
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<table cellpadding=5 width="672"><tr><td valign="top" width="656">
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<font SIZE="2">-- VHDL structural description generated from `decoder`
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<p>-- date : Tue Feb 20 13:55:50 2001</p>
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<p> </p>
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<p>-- Entity Declaration</p>
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<p>ENTITY decoder IS</p>
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<p>PORT (</p>
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<p>a : in BIT_VECTOR (0 TO 3); -- a</p>
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<p>en : in BIT; -- en</p>
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<p>ck : in BIT; -- ck</p>
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<p>res : in BIT; -- res</p>
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<p>vdd : in BIT; -- vdd</p>
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<p>vss : in BIT; -- vss</p>
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<p>c : out BIT_VECTOR (0 TO 15) -- c</p>
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<p>);</p>
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<p>END decoder;</p>
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<p>-- Architecture Declaration</p>
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<p>ARCHITECTURE VST OF decoder IS</p>
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<p>COMPONENT n1_y</p>
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<p>port (</p>
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<p>i : in BIT; -- i</p>
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<p>f : out BIT; -- f</p>
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<p>vdd : in BIT; -- vdd</p>
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<p>vss : in BIT -- vss</p>
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<p>);</p>
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<p>END COMPONENT;</p>
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<p>COMPONENT a4_y</p>
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<p>port (</p>
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<p>i0 : in BIT; -- i0</p>
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<p>i1 : in BIT; -- i1</p>
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<p>i2 : in BIT; -- i2</p>
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<p>i3 : in BIT; -- i3</p>
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<p>t : out BIT; -- t</p>
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<p>vdd : in BIT; -- vdd</p>
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<p>vss : in BIT -- vss</p>
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<p>);</p>
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<p>END COMPONENT;</p>
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<p>COMPONENT a2_y</p>
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<p>port (</p>
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<p>i0 : in BIT; -- i0</p>
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<p>i1 : in BIT; -- i1</p>
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<p>t : out BIT; -- t</p>
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<p>vdd : in BIT; -- vdd</p>
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<p>vss : in BIT -- vss</p>
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<p>);</p>
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<p>END COMPONENT;</p>
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<p>SIGNAL o_0an0 : BIT; -- o_0an0</p>
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<p>SIGNAL o_10an0 : BIT; -- o_10an0</p>
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<p>SIGNAL o_11an0 : BIT; -- o_11an0</p>
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<p>SIGNAL o_12an0 : BIT; -- o_12an0</p>
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<p>SIGNAL o_13an0 : BIT; -- o_13an0</p>
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<p>SIGNAL o_14an0 : BIT; -- o_14an0</p>
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<p>SIGNAL o_15an0 : BIT; -- o_15an0</p>
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<p>SIGNAL o_1an0 : BIT; -- o_1an0</p>
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<p>SIGNAL o_2an0 : BIT; -- o_2an0</p>
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<p>SIGNAL o_3an0 : BIT; -- o_3an0</p>
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<p>SIGNAL o_4an0 : BIT; -- o_4an0</p>
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<p>SIGNAL o_5an0 : BIT; -- o_5an0</p>
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<p>SIGNAL o_6an0 : BIT; -- o_6an0</p>
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<p>SIGNAL o_7an0 : BIT; -- o_7an0</p>
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<p>SIGNAL o_8an0 : BIT; -- o_8an0</p>
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<p>SIGNAL o_9an0 : BIT; -- o_9an0</p>
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<p>SIGNAL o_inv0 : BIT; -- o_inv0</p>
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<p>SIGNAL o_inv1 : BIT; -- o_inv1</p>
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<p>SIGNAL o_inv2 : BIT; -- o_inv2</p>
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<p>SIGNAL o_inv3 : BIT; -- o_inv3</p>
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<p>BEGIN</p>
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<p>inv0 : n1_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>f => o_inv0,</p>
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<p>i => a(0));</p>
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<p>inv1 : n1_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>f => o_inv1,</p>
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<p>i => a(1));</p>
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<p>inv2 : n1_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>f => o_inv2,</p>
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<p>i => a(2));</p>
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<p>inv3 : n1_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>f => o_inv3,</p>
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<p>i => a(3));</p>
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<p>noname0an0 : a4_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => o_0an0,</p>
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<p>i3 => o_inv0,</p>
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<p>i2 => o_inv1,</p>
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<p>i1 => o_inv2,</p>
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<p>i0 => o_inv3);</p>
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<p>noname0an1 : a2_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => c(0),</p>
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<p>i1 => o_0an0,</p>
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<p>i0 => en);</p>
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<p>noname1an0 : a4_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => o_1an0,</p>
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<p>i3 => a(0),</p>
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<p>i2 => o_inv1,</p>
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<p>i1 => o_inv2,</p>
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<p>i0 => o_inv3);</p>
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<p>noname1an1 : a2_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => c(1),</p>
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<p>i1 => o_1an0,</p>
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<p>i0 => en);</p>
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<p>noname2an0 : a4_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => o_2an0,</p>
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<p>i3 => o_inv0,</p>
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<p>i2 => a(1),</p>
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<p>i1 => o_inv2,</p>
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<p>i0 => o_inv3);</p>
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<p>noname2an1 : a2_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => c(2),</p>
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<p>i1 => o_2an0,</p>
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<p>i0 => en);</p>
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<p>noname3an0 : a4_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => o_3an0,</p>
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<p>i3 => a(0),</p>
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<p>i2 => a(1),</p>
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<p>i1 => o_inv2,</p>
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<p>i0 => o_inv3);</p>
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<p>noname3an1 : a2_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => c(3),</p>
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<p>i1 => o_3an0,</p>
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<p>i0 => en);</p>
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<p>noname4an0 : a4_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => o_4an0,</p>
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<p>i3 => o_inv0,</p>
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<p>i2 => o_inv1,</p>
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<p>i1 => a(2),</p>
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<p>i0 => o_inv3);</p>
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<p>noname4an1 : a2_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => c(4),</p>
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<p>i1 => o_4an0,</p>
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<p>i0 => en);</p>
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<p>noname5an0 : a4_y</p>
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => o_5an0,</p>
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<p>i3 => a(0),</p>
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<p>i2 => o_inv1,</p>
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<p>i1 => a(2),</p>
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<p>i0 => o_inv3);</p>
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<p>noname5an1 : a2_y</p>
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| 229 |
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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<p>t => c(5),</p>
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<p>i1 => o_5an0,</p>
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<p>i0 => en);</p>
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<p>noname6an0 : a4_y</p>
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| 236 |
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<p>PORT MAP (</p>
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| 237 |
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<p>vss => vss,</p>
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| 238 |
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<p>vdd => vdd,</p>
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<p>t => o_6an0,</p>
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<p>i3 => o_inv0,</p>
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<p>i2 => a(1),</p>
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<p>i1 => a(2),</p>
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<p>i0 => o_inv3);</p>
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| 244 |
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<p>noname6an1 : a2_y</p>
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| 245 |
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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<p>vdd => vdd,</p>
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| 248 |
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<p>t => c(6),</p>
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<p>i1 => o_6an0,</p>
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<p>i0 => en);</p>
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| 251 |
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<p>noname7an0 : a4_y</p>
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| 252 |
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<p>PORT MAP (</p>
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<p>vss => vss,</p>
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| 254 |
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<p>vdd => vdd,</p>
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| 255 |
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<p>t => o_7an0,</p>
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| 256 |
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<p>i3 => a(0),</p>
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<p>i2 => a(1),</p>
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<p>i1 => a(2),</p>
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<p>i0 => o_inv3);</p>
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<p>noname7an1 : a2_y</p>
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| 261 |
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<p>PORT MAP (</p>
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| 262 |
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<p>vss => vss,</p>
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| 263 |
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<p>vdd => vdd,</p>
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<p>t => c(7),</p>
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<p>i1 => o_7an0,</p>
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<p>i0 => en);</p>
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| 267 |
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<p>noname8an0 : a4_y</p>
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| 268 |
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<p>PORT MAP (</p>
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| 269 |
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<p>vss => vss,</p>
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| 270 |
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<p>vdd => vdd,</p>
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| 271 |
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<p>t => o_8an0,</p>
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<p>i3 => o_inv0,</p>
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| 273 |
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<p>i2 => o_inv1,</p>
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<p>i1 => o_inv2,</p>
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| 275 |
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<p>i0 => a(3));</p>
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| 276 |
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<p>noname8an1 : a2_y</p>
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| 277 |
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<p>PORT MAP (</p>
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| 278 |
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<p>vss => vss,</p>
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| 279 |
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<p>vdd => vdd,</p>
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| 280 |
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<p>t => c(8),</p>
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| 281 |
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<p>i1 => o_8an0,</p>
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| 282 |
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<p>i0 => en);</p>
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| 283 |
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<p>noname9an0 : a4_y</p>
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| 284 |
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<p>PORT MAP (</p>
|
| 285 |
|
|
<p>vss => vss,</p>
|
| 286 |
|
|
<p>vdd => vdd,</p>
|
| 287 |
|
|
<p>t => o_9an0,</p>
|
| 288 |
|
|
<p>i3 => a(0),</p>
|
| 289 |
|
|
<p>i2 => o_inv1,</p>
|
| 290 |
|
|
<p>i1 => o_inv2,</p>
|
| 291 |
|
|
<p>i0 => a(3));</p>
|
| 292 |
|
|
<p>noname9an1 : a2_y</p>
|
| 293 |
|
|
<p>PORT MAP (</p>
|
| 294 |
|
|
<p>vss => vss,</p>
|
| 295 |
|
|
<p>vdd => vdd,</p>
|
| 296 |
|
|
<p>t => c(9),</p>
|
| 297 |
|
|
<p>i1 => o_9an0,</p>
|
| 298 |
|
|
<p>i0 => en);</p>
|
| 299 |
|
|
<p>noname10an0 : a4_y</p>
|
| 300 |
|
|
<p>PORT MAP (</p>
|
| 301 |
|
|
<p>vss => vss,</p>
|
| 302 |
|
|
<p>vdd => vdd,</p>
|
| 303 |
|
|
<p>t => o_10an0,</p>
|
| 304 |
|
|
<p>i3 => o_inv0,</p>
|
| 305 |
|
|
<p>i2 => a(1),</p>
|
| 306 |
|
|
<p>i1 => o_inv2,</p>
|
| 307 |
|
|
<p>i0 => a(3));</p>
|
| 308 |
|
|
<p>noname10an1 : a2_y</p>
|
| 309 |
|
|
<p>PORT MAP (</p>
|
| 310 |
|
|
<p>vss => vss,</p>
|
| 311 |
|
|
<p>vdd => vdd,</p>
|
| 312 |
|
|
<p>t => c(10),</p>
|
| 313 |
|
|
<p>i1 => o_10an0,</p>
|
| 314 |
|
|
<p>i0 => en);</p>
|
| 315 |
|
|
<p>noname11an0 : a4_y</p>
|
| 316 |
|
|
<p>PORT MAP (</p>
|
| 317 |
|
|
<p>vss => vss,</p>
|
| 318 |
|
|
<p>vdd => vdd,</p>
|
| 319 |
|
|
<p>t => o_11an0,</p>
|
| 320 |
|
|
<p>i3 => a(0),</p>
|
| 321 |
|
|
<p>i2 => a(1),</p>
|
| 322 |
|
|
<p>i1 => o_inv2,</p>
|
| 323 |
|
|
<p>i0 => a(3));</p>
|
| 324 |
|
|
<p>noname11an1 : a2_y</p>
|
| 325 |
|
|
<p>PORT MAP (</p>
|
| 326 |
|
|
<p>vss => vss,</p>
|
| 327 |
|
|
<p>vdd => vdd,</p>
|
| 328 |
|
|
<p>t => c(11),</p>
|
| 329 |
|
|
<p>i1 => o_11an0,</p>
|
| 330 |
|
|
<p>i0 => en);</p>
|
| 331 |
|
|
<p>noname12an0 : a4_y</p>
|
| 332 |
|
|
<p>PORT MAP (</p>
|
| 333 |
|
|
<p>vss => vss,</p>
|
| 334 |
|
|
<p>vdd => vdd,</p>
|
| 335 |
|
|
<p>t => o_12an0,</p>
|
| 336 |
|
|
<p>i3 => o_inv0,</p>
|
| 337 |
|
|
<p>i2 => o_inv1,</p>
|
| 338 |
|
|
<p>i1 => a(2),</p>
|
| 339 |
|
|
<p>i0 => a(3));</p>
|
| 340 |
|
|
<p>noname12an1 : a2_y</p>
|
| 341 |
|
|
<p>PORT MAP (</p>
|
| 342 |
|
|
<p>vss => vss,</p>
|
| 343 |
|
|
<p>vdd => vdd,</p>
|
| 344 |
|
|
<p>t => c(12),</p>
|
| 345 |
|
|
<p>i1 => o_12an0,</p>
|
| 346 |
|
|
<p>i0 => en);</p>
|
| 347 |
|
|
<p>noname13an0 : a4_y</p>
|
| 348 |
|
|
<p>PORT MAP (</p>
|
| 349 |
|
|
<p>vss => vss,</p>
|
| 350 |
|
|
<p>vdd => vdd,</p>
|
| 351 |
|
|
<p>t => o_13an0,</p>
|
| 352 |
|
|
<p>i3 => a(0),</p>
|
| 353 |
|
|
<p>i2 => o_inv1,</p>
|
| 354 |
|
|
<p>i1 => a(2),</p>
|
| 355 |
|
|
<p>i0 => a(3));</p>
|
| 356 |
|
|
<p>noname13an1 : a2_y</p>
|
| 357 |
|
|
<p>PORT MAP (</p>
|
| 358 |
|
|
<p>vss => vss,</p>
|
| 359 |
|
|
<p>vdd => vdd,</p>
|
| 360 |
|
|
<p>t => c(13),</p>
|
| 361 |
|
|
<p>i1 => o_13an0,</p>
|
| 362 |
|
|
<p>i0 => en);</p>
|
| 363 |
|
|
<p>noname14an0 : a4_y</p>
|
| 364 |
|
|
<p>PORT MAP (</p>
|
| 365 |
|
|
<p>vss => vss,</p>
|
| 366 |
|
|
<p>vdd => vdd,</p>
|
| 367 |
|
|
<p>t => o_14an0,</p>
|
| 368 |
|
|
<p>i3 => o_inv0,</p>
|
| 369 |
|
|
<p>i2 => a(1),</p>
|
| 370 |
|
|
<p>i1 => a(2),</p>
|
| 371 |
|
|
<p>i0 => a(3));</p>
|
| 372 |
|
|
<p>noname14an1 : a2_y</p>
|
| 373 |
|
|
<p>PORT MAP (</p>
|
| 374 |
|
|
<p>vss => vss,</p>
|
| 375 |
|
|
<p>vdd => vdd,</p>
|
| 376 |
|
|
<p>t => c(14),</p>
|
| 377 |
|
|
<p>i1 => o_14an0,</p>
|
| 378 |
|
|
<p>i0 => en);</p>
|
| 379 |
|
|
<p>noname15an0 : a4_y</p>
|
| 380 |
|
|
<p>PORT MAP (</p>
|
| 381 |
|
|
<p>vss => vss,</p>
|
| 382 |
|
|
<p>vdd => vdd,</p>
|
| 383 |
|
|
<p>t => o_15an0,</p>
|
| 384 |
|
|
<p>i3 => a(0),</p>
|
| 385 |
|
|
<p>i2 => a(1),</p>
|
| 386 |
|
|
<p>i1 => a(2),</p>
|
| 387 |
|
|
<p>i0 => a(3));</p>
|
| 388 |
|
|
<p>noname15an1 : a2_y</p>
|
| 389 |
|
|
<p>PORT MAP (</p>
|
| 390 |
|
|
<p>vss => vss,</p>
|
| 391 |
|
|
<p>vdd => vdd,</p>
|
| 392 |
|
|
<p>t => c(15),</p>
|
| 393 |
|
|
<p>i1 => o_15an0,</p>
|
| 394 |
|
|
<p>i0 => en);</p>
|
| 395 |
|
|
<p>end VST;</p>
|
| 396 |
|
|
</font>
|
| 397 |
|
|
|
| 398 |
|
|
<b><font size=+1>Maintainers and Authors :</font></b>
|
| 399 |
|
|
<p>LCD Driver development team
|
| 400 |
|
|
<p>current members:
|
| 401 |
|
|
|
| 402 |
|
|
<ul>
|
| 403 |
|
|
<li>
|
| 404 |
|
|
<a href="mailto:marta@vlsi.itb.ac.id">Hendra Gunawan</a></li>
|
| 405 |
|
|
|
| 406 |
|
|
<li>
|
| 407 |
|
|
<a href="mailto:sigit@students.ee.itb.ac.id">Nurhadi Wiyono</a></li>
|
| 408 |
|
|
|
| 409 |
|
|
<li>
|
| 410 |
|
|
<a href="mailto:sigit@students.ee.itb.ac.id">Kharisma Sinung P</a></li>
|
| 411 |
|
|
|
| 412 |
|
|
</ul>
|
| 413 |
|
|
|
| 414 |
|
|
<p>
|
| 415 |
|
|
<b><font size=+1>Mailing-list:</font></b>
|
| 416 |
|
|
<ul><a href="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</a></ul>
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
|
| 423 |
|
|
</td></tr></table>
|
| 424 |
|
|
</td></tr>
|
| 425 |
|
|
<tr><td bgcolor="#f8f8f0"> </td>
|
| 426 |
|
|
<td valign="bottom">
|
| 427 |
|
|
<table cellspacing=0 cellpadding=4 border=0 width="100%"bgcolor="#f0f0f0"><tr>
|
| 428 |
|
|
<td align=left><i><small>Last modified on Sunday, 17-Sep-2000 03:58:04 JAVT</i></td>
|
| 429 |
|
|
<td align=right><i><small>Copyright © 1999-2000 OPENCORES.ORG. All rights reserved.</td>
|
| 430 |
|
|
</tr></table>
|
| 431 |
|
|
|
| 432 |
|
|
</td></tr></table>
|
| 433 |
|
|
|
| 434 |
|
|
</td></tr></table>
|
| 435 |
|
|
|
| 436 |
|
|
</body></html>
|
