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vlib work -- create work library fo the simulation

vmap work work -- this map the new work library, the second work is the path

to the library, could be vsim/work or something like this.

vcom -quiet -93 -work work my_vhdl_file_to_compile.vhd

-----

vlib    -- create library

vmap    -- list all mapped librarys

vmap    -- map logical library to real one

vmap -del       -- delete logical mapping

vcom -93 -check_synthesis -force_refresh -work   --if you specifiy more than one file, you must start with the lowest file

in the hierarchie. You should comile the design vhdl source files and the

testbench vhdl file.

vsim .  --start vsim and specify the TOP-Level

=modelsim/work

=work

= could be logical name "work" or unix path "modelsim/work"

=src/abc.vhd

=work.dff_tb

----

vsim -c work.dff_tb -do first.do

--tlc1 is ok?, tlc2 is ok but green is 3ms longer, tlc3 is absolutely ok but

should be corrected in order to synthesize,