Subversion Repositories lcd_block

##############################################################

#

# Xilinx Core Generator version 13.4

# Date: Tue May 22 22:08:27 2012

#

##############################################################

#

#  This file contains the customisation parameters for a

#  Xilinx CORE Generator IP GUI. It is strongly recommended

#  that you do not manually alter this file as it may cause

#  unexpected and unsupported behavior.

#

##############################################################

#

#  Generated from component: xilinx.com:ip:chipscope_icon:1.06.a

#

##############################################################

#

# BEGIN Project Options

SET addpads = false

SET asysymbol = true

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = false

SET designentry = Verilog

SET device = xc3s500e

SET devicefamily = spartan3e

SET flowvendor = Other

SET formalverification = false

SET foundationsym = false

SET implementationfiletype = Ngc

SET package = fg320

SET removerpms = false

SET simulationfiles = Structural

SET speedgrade = -4

SET verilogsim = true

SET vhdlsim = false

# END Project Options

# BEGIN Select

SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a

# END Select

# BEGIN Parameters

CSET component_name=coreICON

CSET constraint_type=external

CSET enable_jtag_bufg=true

CSET example_design=true

CSET number_control_ports=2

CSET use_ext_bscan=false

CSET use_softbscan=false

CSET use_unused_bscan=false

CSET user_scan_chain=USER1

# END Parameters

# BEGIN Extra information

MISC pkg_timestamp=2012-01-07T09:19:07Z

# END Extra information

GENERATE

# CRC: d9309160