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[/] [lcd_block/] [trunk/] [hdl/] [iseProject/] [lcd_wishbone_slave.v] - Blame information for rev 5

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`timescale 1ns / 1ps
/*
        Wishbone slave
        (Verilog 2001)
*/
module lcd_wishbone_slave(
    input clk_i,
    input rst_i,
    input [1:0] wb_adr_i,
    input [7:0] wb_dat_i,
    output [7:0] wb_dat_o,
    input wb_we_i,
    input SEL_I0,
    input wb_stb_i,
    output wb_ack_o,
    input CYC_I
    );
 
 
endmodule

Line No.	Rev	Author	Line
1	3	leonardoar	`timescale 1ns / 1ps
2			`/*`
3			`Wishbone slave`
4			`(Verilog 2001)`
5			`*/`
6			`module lcd_wishbone_slave(`
7	5	leonardoar	`input clk_i,`
8			`input rst_i,`
9			`input [1:0] wb_adr_i,`
10			`input [7:0] wb_dat_i,`
11			`output [7:0] wb_dat_o,`
12			`input wb_we_i,`
13	3	leonardoar	`input SEL_I0,`
14	5	leonardoar	`input wb_stb_i,`
15			`output wb_ack_o,`
16	3	leonardoar	`input CYC_I`
17			`);`
18
19
20			`endmodule`

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[/] [lcd_block/] [trunk/] [hdl/] [iseProject/] [lcd_wishbone_slave.v] - Blame information for rev 5