URL https://opencores.org/ocsvn/lcd_block/lcd_block/trunk

Subversion Repositories lcd_block

[/] [lcd_block/] [trunk/] [hdl/] [iseProject/] [lcd_wishbone_slave.v] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log


`timescale 1ns / 1ps
/*
        Wishbone slave
        (Verilog 2001)
*/
module lcd_wishbone_slave(
    input RST_I,
    input CLK_I,
    input [1:0] ADR_I0,
    input DAT_I0,
    output [7:0] DAT_O0,
    input WE_I,
    input SEL_I0,
    input STB_I,
    output ACK_O,
    input CYC_I
    );
 
 
endmodule

Line No.	Rev	Author	Line
1	3	leonardoar	`timescale 1ns / 1ps
2			`/*`
3			`Wishbone slave`
4			`(Verilog 2001)`
5			`*/`
6			`module lcd_wishbone_slave(`
7			`input RST_I,`
8			`input CLK_I,`
9			`input [1:0] ADR_I0,`
10			`input DAT_I0,`
11			`output [7:0] DAT_O0,`
12			`input WE_I,`
13			`input SEL_I0,`
14			`input STB_I,`
15			`output ACK_O,`
16			`input CYC_I`
17			`);`
18
19
20			`endmodule`

Browse

Tools

Subversion Repositories lcd_block

[/] [lcd_block/] [trunk/] [hdl/] [iseProject/] [lcd_wishbone_slave.v] - Blame information for rev 3