OpenCores
URL https://opencores.org/ocsvn/lcd_block/lcd_block/trunk

Subversion Repositories lcd_block

[/] [lcd_block/] [trunk/] [hdl/] [iseProject/] [top_hw_testbench.v] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 leonardoar
`timescale 1ns / 1ps
2
/*
3
Top module that will instantiate and connect our DUT (lcd_controller) the ICON, VIO , ILA cores
4
*/
5
module top_hw_testbench(
6 12 leonardoar
    input clk/*,
7
         output hw_lcd_e,
8
         output hw_lcd_rs,
9
         output hw_lcd_rw,
10
         output [3:0] hw_lcd_nibble,
11
         output hw_strata_flash_disable*/
12 11 leonardoar
    );
13
 
14
        // Declare some wires to connect the components
15
        wire rst;
16
        wire rs_in,strobe_in;
17
        wire[7:0] data_in, period_clk_ns;
18
        wire [3:0] lcd_nibble;
19
        wire lcd_e,lcd_rs,lcd_rw,disable_flash,done;
20
 
21
        // Declare the ICON wires
22
        wire [35: 0] control0;
23
        wire [35: 0] control1;
24
        // Declare VIO wires
25
        wire [18: 0] async_out;
26
        // Declare ILA wires
27
        wire trig_0;
28
        wire [16:0] data;
29
 
30
        // Instantiate our Device under test
31
        lcd_controller DUT (
32
                rst,
33
                clk,
34
                rs_in,
35
                data_in,
36
                strobe_in,
37
                period_clk_ns,
38
                lcd_e,
39
                lcd_nibble,
40
                lcd_rs,
41
                lcd_rw,
42
                disable_flash,
43
                done
44
                );
45
 
46
        coreICON integratedController (
47
      .CONTROL0(control0), // INOUT BUS [35:0]
48
      .CONTROL1(control1)
49
                ); // INOUT BUS [35:0]
50
 
51
 
52
        coreILA integratedLogicAnalyser (
53
      .CONTROL(control0), // INOUT BUS [35:0]
54
      .CLK(clk), // IN
55
      .DATA(data), // DATA [16:0];
56
      .TRIG0(trig_0)
57
        ); // IN BUS [0:0]
58
 
59
        coreVIO VIO_inst
60
    (
61
      .CONTROL(control1), // INOUT BUS [35:0]
62
      .ASYNC_OUT(async_out)
63
        ); // IN BUS [18:0]
64
 
65
        assign trig_0 = lcd_e;
66
        assign {rst, rs_in, data_in, strobe_in, period_clk_ns} = async_out;
67
        assign data = {7'd1,lcd_e, lcd_nibble[3:0], lcd_rs, lcd_rw, disable_flash, done, strobe_in};
68 12 leonardoar
 
69
        // Send all interest output to outside
70
        /*assign hw_lcd_e = lcd_e;
71
        assign hw_lcd_rs = lcd_rs;
72
        assign hw_lcd_rw = lcd_rw;
73
        assign hw_lcd_nibble = lcd_nibble;
74
        assign hw_strata_flash_disable = disable_flash;*/
75 11 leonardoar
 
76
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.