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[/] [leros/] [trunk/] [asm/] [blink.asm] - Blame information for rev 4

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1 3 martin 
// Register definitions
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//R0 = ?
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//R1 = ?
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//R2 = ?
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// first instruction is not executed
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        nop
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// second instruction is executed twice
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// A real blink in SW with 0.5 Hz
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//      100.000.000 cycle loop
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// 100 MHz clock, inner loop is 3 cycles
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// inner loop 65635*3 = 196605
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// outer loop 509 ca. 512 is ok
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start:
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        load 0
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        loadh 2
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        store r0
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ll1:    load 255
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        loadh 255
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ll2:    sub 1
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        nop             // we don't know yet about branch slot
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        brnz ll2
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        nop
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        load r0
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        sub 1
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        store r0
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        brnz ll1
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        nop
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        load 0
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        out 0
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        load 0
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        loadh 2
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        store r0
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ll3:    load 255
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        loadh 255
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ll4:    sub 1
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        nop             // we don't know yet about branch slot
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        brnz ll4
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        nop
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        load r0
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        sub 1
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        store r0
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        brnz ll3
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        nop
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        load 1
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        out 0
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        load 1
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        nop
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        brnz start
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