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[/] [leros/] [trunk/] [asm/] [loadstore.asm] - Blame information for rev 3

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1 3 martin
// Test code
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// first instruction is not executed
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        nop
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// second instruction is executed twice
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start:
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        load 127
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        store r1
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        load 7
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        store r3
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        nop // there is a store/load delay on registers, right?
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        load 15
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        loadaddr r3
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        store (ar+1)
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        load 0
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        loadaddr r3
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        load (ar+1)
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        load r1
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        out 0
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