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[/] [leros/] [trunk/] [asm/] [loadstore.asm] - Blame information for rev 4

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// Test code
 
// first instruction is not executed
        nop
// second instruction is executed twice
 
start:
        load 127
        store r1
        load 7
        store r3
        nop // there is a store/load delay on registers, right?
        load 15
        loadaddr r3
        store (ar+1)
        load 0
        loadaddr r3
        load (ar+1)
        load r1
        out 0
 
 
 

Line No.	Rev	Author	Line
1	3	martin	`// Test code`
2
3			`// first instruction is not executed`
4			`nop`
5			`// second instruction is executed twice`
6
7			`start:`
8			`load 127`
9			`store r1`
10			`load 7`
11			`store r3`
12			`nop // there is a store/load delay on registers, right?`
13			`load 15`
14			`loadaddr r3`
15			`store (ar+1)`
16			`load 0`
17			`loadaddr r3`
18			`load (ar+1)`
19			`load r1`
20			`out 0`
21
22
23

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[/] [leros/] [trunk/] [asm/] [loadstore.asm] - Blame information for rev 4