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[/] [leros/] [trunk/] [doc/] [notes.txt] - Blame information for rev 4
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martin |
Some possible changes/enhancements:
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The address register for indirect load/stores could be made
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permanent and visible. One could reuse the loaded contents
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for several DM accesses (e.g. local variables on the stack).
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Would need an additional register and a MUX selecting from
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that register or forwarding the just read address from the
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DM.
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If not implementing this address register, the combination
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of load address and load/store should be implemented as
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a pseudo instruction in the assembler to avoid programming
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errors:
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load (Rx+n)
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store (Rx+n)
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The content of A could also be written into DM in the next
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cycle. This would extend the pipeline to three stages. But
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it would be a funny mix between a register architecture and
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an accumulator architecture, where the result is written
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into two places (A and Rx). Would safe a store sometimes.
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A + Rx -> A, Ry
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