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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2010 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 10.1 Build 153 11/29/2010 SJ Web Edition
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# Date created = 16:33:34 February 20, 2011
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# leros_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C70F896C6
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set_global_assignment -name TOP_LEVEL_ENTITY leros_top_de2
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:33:34 FEBRUARY 20, 2011"
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set_global_assignment -name LAST_QUARTUS_VERSION 10.1
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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# Pin & Location Assignments
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# ==========================
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set_location_assignment PIN_AD15 -to clk
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set_location_assignment PIN_D21 -to ser_rxd
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set_location_assignment PIN_E21 -to ser_txd
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set_location_assignment PIN_W27 -to oLEDG[0]
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set_location_assignment PIN_W25 -to oLEDG[1]
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set_location_assignment PIN_W23 -to oLEDG[2]
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set_location_assignment PIN_Y27 -to oLEDG[3]
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set_location_assignment PIN_Y24 -to oLEDG[4]
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set_location_assignment PIN_Y23 -to oLEDG[5]
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set_location_assignment PIN_AA27 -to oLEDG[6]
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set_location_assignment PIN_AA24 -to oLEDG[7]
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set_location_assignment PIN_T29 -to iKEY[0]
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set_location_assignment PIN_T28 -to iKEY[1]
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set_location_assignment PIN_U30 -to iKEY[2]
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set_location_assignment PIN_U29 -to iKEY[3]
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
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set_global_assignment -name VHDL_FILE ../../vhdl/core/leros_types.vhd
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set_global_assignment -name VHDL_FILE ../../vhdl/generated/leros_rom.vhd
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set_global_assignment -name VHDL_FILE ../../vhdl/core/leros_im.vhd
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set_global_assignment -name VHDL_FILE ../../vhdl/core/leros_decode.vhd
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set_global_assignment -name VHDL_FILE ../../vhdl/core/leros_fedec.vhd
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set_global_assignment -name VHDL_FILE ../../vhdl/core/leros_ex.vhd
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set_global_assignment -name VHDL_FILE ../../vhdl/core/leros.vhd
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set_global_assignment -name VHDL_FILE ../../vhdl/io/uart.vhd
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set_global_assignment -name VHDL_FILE ../../vhdl/altera/cyc2_pll.vhd
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set_global_assignment -name VHDL_FILE "../../vhdl/top/leros_de2-70.vhd"
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set_global_assignment -name OUTPUT_PIN_LOAD 5 -section_id "3.3-V LVCMOS"
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set_global_assignment -name OUTPUT_PIN_LOAD 10 -section_id "3.3-V PCI"
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set_global_assignment -name OUTPUT_PIN_LOAD 10 -section_id "3.3-V PCI-X"
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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