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[/] [leros/] [trunk/] [quartus/] [fmax/] [leros.sdc] - Blame information for rev 3

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Line No. Rev Author Line
1 3 martin
###########################################################################
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# SDC files for Cycore based boards
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###########################################################################
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# Clock in input pin (20 MHz)
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create_clock -period 50.0 [get_ports clk]
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# Create generated clocks based on PLLs
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derive_pll_clocks
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derive_clock_uncertainty
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# ** Input/Output Delays
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#    -------------------
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# MS: I want following constrains for the SRAM connection
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# Input:
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#    maximum Tsu 2.2 ns
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#    maximum Tho ? ns (could be 0-2, will be negative anyway)
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# Output:
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#    maximum Tco 3 ns
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#
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# Are the following constraints correct?
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# I'm confused by the min/max input delay notion.
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# Use FPGA-centric constraints (general pins)
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# Tsu 5 ns
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set_max_delay -from [all_inputs] -to [all_registers] 5
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# the value is -th, so a negative hold time would be positive
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set_min_delay -from [all_inputs] -to [all_registers] -0.0
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# Tco 10 ns
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set_max_delay -from [all_registers] -to [all_outputs] 10
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# WTF shall this constraint be? A hold time on an output port?
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set_min_delay -from [all_registers] -to [all_outputs] -0.0
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# Use FPGA-centric constraints (SRAM pins)
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# Tsu 2 ns
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set_max_delay -from [get_ports *] -to [get_registers {*ram*}] 2.2
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# Tco 3 ns
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set_max_delay -from [get_registers *] -to [get_ports {ram*}] 3
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