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--

--

--  This file is a part of JOP, the Java Optimized Processor

--

--  Copyright (C) 2001-2008, Martin Schoeberl (martin@jopdesign.com)

--

--  This program is free software: you can redistribute it and/or modify

--  it under the terms of the GNU General Public License as published by

--  the Free Software Foundation, either version 3 of the License, or

--  (at your option) any later version.

--

--  This program is distributed in the hope that it will be useful,

--  but WITHOUT ANY WARRANTY; without even the implied warranty of

--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--  GNU General Public License for more details.

--

--  You should have received a copy of the GNU General Public License

--  along with this program.  If not, see <http://www.gnu.org/licenses/>.

--

-- as generated by the wizzard and added generic

-- used by altde2 board with Cyclone II

-- clock 2 is 180 degree phase shifted, but that's only

-- true when the frequency is set to 100 MHz (factor 5) 

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY pll IS

        generic (multiply_by : natural; divide_by : natural);

        PORT

        (

                inclk0          : IN STD_LOGIC  := '0';

                c0              : OUT STD_LOGIC ;

                c1              : OUT STD_LOGIC ;

                locked          : OUT STD_LOGIC

        );

END pll;

ARCHITECTURE SYN OF pll IS

        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (5 DOWNTO 0);

        SIGNAL sub_wire1        : STD_LOGIC ;

        SIGNAL sub_wire2        : STD_LOGIC ;

        SIGNAL sub_wire3        : STD_LOGIC ;

        SIGNAL sub_wire4        : STD_LOGIC ;

        SIGNAL sub_wire5        : STD_LOGIC_VECTOR (1 DOWNTO 0);

        SIGNAL sub_wire6_bv     : BIT_VECTOR (0 DOWNTO 0);

        SIGNAL sub_wire6        : STD_LOGIC_VECTOR (0 DOWNTO 0);

        COMPONENT altpll

        GENERIC (

                clk0_divide_by          : NATURAL;

                clk0_duty_cycle         : NATURAL;

                clk0_multiply_by                : NATURAL;

                clk0_phase_shift                : STRING;

                clk1_divide_by          : NATURAL;

                clk1_duty_cycle         : NATURAL;

                clk1_multiply_by                : NATURAL;

                clk1_phase_shift                : STRING;

                compensate_clock                : STRING;

                gate_lock_signal                : STRING;

                inclk0_input_frequency          : NATURAL;

                intended_device_family          : STRING;

                invalid_lock_multiplier         : NATURAL;

                lpm_hint                : STRING;

                lpm_type                : STRING;

                operation_mode          : STRING;

                port_activeclock                : STRING;

                port_areset             : STRING;

                port_clkbad0            : STRING;

                port_clkbad1            : STRING;

                port_clkloss            : STRING;

                port_clkswitch          : STRING;

                port_configupdate               : STRING;

                port_fbin               : STRING;

                port_inclk0             : STRING;

                port_inclk1             : STRING;

                port_locked             : STRING;

                port_pfdena             : STRING;

                port_phasecounterselect         : STRING;

                port_phasedone          : STRING;

                port_phasestep          : STRING;

                port_phaseupdown                : STRING;

                port_pllena             : STRING;

                port_scanaclr           : STRING;

                port_scanclk            : STRING;

                port_scanclkena         : STRING;

                port_scandata           : STRING;

                port_scandataout                : STRING;

                port_scandone           : STRING;

                port_scanread           : STRING;

                port_scanwrite          : STRING;

                port_clk0               : STRING;

                port_clk1               : STRING;

                port_clk2               : STRING;

                port_clk3               : STRING;

                port_clk4               : STRING;

                port_clk5               : STRING;

                port_clkena0            : STRING;

                port_clkena1            : STRING;

                port_clkena2            : STRING;

                port_clkena3            : STRING;

                port_clkena4            : STRING;

                port_clkena5            : STRING;

                port_extclk0            : STRING;

                port_extclk1            : STRING;

                port_extclk2            : STRING;

                port_extclk3            : STRING;

                valid_lock_multiplier           : NATURAL

        );

        PORT (

                        clk     : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);

                        inclk   : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

                        locked  : OUT STD_LOGIC

        );

        END COMPONENT;

BEGIN

        sub_wire6_bv(0 DOWNTO 0) <= "0";

        sub_wire6    <= To_stdlogicvector(sub_wire6_bv);

        sub_wire3    <= sub_wire0(0);

        sub_wire1    <= sub_wire0(1);

        c1    <= sub_wire1;

        locked    <= sub_wire2;

        c0    <= sub_wire3;

        sub_wire4    <= inclk0;

        sub_wire5    <= sub_wire6(0 DOWNTO 0) & sub_wire4;

        altpll_component : altpll

        GENERIC MAP (

                clk0_divide_by => divide_by,

                clk0_duty_cycle => 50,

                clk0_multiply_by => multiply_by,

                clk0_phase_shift => "0",

                clk1_divide_by => divide_by,

                clk1_duty_cycle => 50,

                clk1_multiply_by => multiply_by,

                clk1_phase_shift => "5000", -- this is in ps, and shall be an inverted clock

                compensate_clock => "CLK0",

                gate_lock_signal => "NO",

                inclk0_input_frequency => 20000, -- 50 Mhz = 20000 ps

                intended_device_family => "Cyclone II",

                invalid_lock_multiplier => 5,

                lpm_hint => "CBX_MODULE_PREFIX=pll2",

                lpm_type => "altpll",

                operation_mode => "NORMAL",

                port_activeclock => "PORT_UNUSED",

                port_areset => "PORT_UNUSED",

                port_clkbad0 => "PORT_UNUSED",

                port_clkbad1 => "PORT_UNUSED",

                port_clkloss => "PORT_UNUSED",

                port_clkswitch => "PORT_UNUSED",

                port_configupdate => "PORT_UNUSED",

                port_fbin => "PORT_UNUSED",

                port_inclk0 => "PORT_USED",

                port_inclk1 => "PORT_UNUSED",

                port_locked => "PORT_USED",

                port_pfdena => "PORT_UNUSED",

                port_phasecounterselect => "PORT_UNUSED",

                port_phasedone => "PORT_UNUSED",

                port_phasestep => "PORT_UNUSED",

                port_phaseupdown => "PORT_UNUSED",

                port_pllena => "PORT_UNUSED",

                port_scanaclr => "PORT_UNUSED",

                port_scanclk => "PORT_UNUSED",

                port_scanclkena => "PORT_UNUSED",

                port_scandata => "PORT_UNUSED",

                port_scandataout => "PORT_UNUSED",

                port_scandone => "PORT_UNUSED",

                port_scanread => "PORT_UNUSED",

                port_scanwrite => "PORT_UNUSED",

                port_clk0 => "PORT_USED",

                port_clk1 => "PORT_USED",

                port_clk2 => "PORT_UNUSED",

                port_clk3 => "PORT_UNUSED",

                port_clk4 => "PORT_UNUSED",

                port_clk5 => "PORT_UNUSED",

                port_clkena0 => "PORT_UNUSED",

                port_clkena1 => "PORT_UNUSED",

                port_clkena2 => "PORT_UNUSED",

                port_clkena3 => "PORT_UNUSED",

                port_clkena4 => "PORT_UNUSED",

                port_clkena5 => "PORT_UNUSED",

                port_extclk0 => "PORT_UNUSED",

                port_extclk1 => "PORT_UNUSED",

                port_extclk2 => "PORT_UNUSED",

                port_extclk3 => "PORT_UNUSED",

                valid_lock_multiplier => 1

        )

        PORT MAP (

                inclk => sub_wire5,

                clk => sub_wire0,

                locked => sub_wire2

        );

END SYN;