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[/] [leros/] [trunk/] [vhdl/] [altera/] [cyc3_pll.vhd] - Blame information for rev 3

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1 3 martin
-- megafunction wizard: %ALTPLL%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altpll 
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-- ============================================================
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-- File Name: cyc3_pll.vhd
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-- Megafunction Name(s):
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--                      altpll
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--
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-- Simulation Library Files(s):
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--                      altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 10.1 Build 153 11/29/2010 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2010 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions 
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--and other software and tools, and its AMPP partner logic 
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--functions, and any output files from any of the foregoing 
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--(including device programming or simulation files), and any 
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--associated documentation or information are expressly subject 
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--to the terms and conditions of the Altera Program License 
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--Subscription Agreement, Altera MegaCore Function License 
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--Agreement, or other applicable license agreement, including, 
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--without limitation, that your use is for the sole purpose of 
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--programming logic devices manufactured by Altera and sold by 
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--Altera or its authorized distributors.  Please refer to the 
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY pll IS
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        generic (multiply_by : natural; divide_by : natural);
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        PORT
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        (
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                inclk0          : IN STD_LOGIC  := '0';
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                c0              : OUT STD_LOGIC
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        );
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END pll;
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ARCHITECTURE SYN OF pll IS
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        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (4 DOWNTO 0);
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        SIGNAL sub_wire1        : STD_LOGIC ;
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        SIGNAL sub_wire2        : STD_LOGIC ;
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        SIGNAL sub_wire3        : STD_LOGIC_VECTOR (1 DOWNTO 0);
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        SIGNAL sub_wire4_bv     : BIT_VECTOR (0 DOWNTO 0);
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        SIGNAL sub_wire4        : STD_LOGIC_VECTOR (0 DOWNTO 0);
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        COMPONENT altpll
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        GENERIC (
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                bandwidth_type          : STRING;
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                clk0_divide_by          : NATURAL;
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                clk0_duty_cycle         : NATURAL;
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                clk0_multiply_by                : NATURAL;
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                clk0_phase_shift                : STRING;
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                compensate_clock                : STRING;
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                inclk0_input_frequency          : NATURAL;
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                intended_device_family          : STRING;
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                lpm_hint                : STRING;
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                lpm_type                : STRING;
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                operation_mode          : STRING;
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                pll_type                : STRING;
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                port_activeclock                : STRING;
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                port_areset             : STRING;
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                port_clkbad0            : STRING;
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                port_clkbad1            : STRING;
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                port_clkloss            : STRING;
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                port_clkswitch          : STRING;
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                port_configupdate               : STRING;
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                port_fbin               : STRING;
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                port_inclk0             : STRING;
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                port_inclk1             : STRING;
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                port_locked             : STRING;
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                port_pfdena             : STRING;
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                port_phasecounterselect         : STRING;
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                port_phasedone          : STRING;
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                port_phasestep          : STRING;
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                port_phaseupdown                : STRING;
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                port_pllena             : STRING;
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                port_scanaclr           : STRING;
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                port_scanclk            : STRING;
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                port_scanclkena         : STRING;
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                port_scandata           : STRING;
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                port_scandataout                : STRING;
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                port_scandone           : STRING;
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                port_scanread           : STRING;
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                port_scanwrite          : STRING;
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                port_clk0               : STRING;
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                port_clk1               : STRING;
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                port_clk2               : STRING;
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                port_clk3               : STRING;
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                port_clk4               : STRING;
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                port_clk5               : STRING;
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                port_clkena0            : STRING;
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                port_clkena1            : STRING;
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                port_clkena2            : STRING;
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                port_clkena3            : STRING;
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                port_clkena4            : STRING;
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                port_clkena5            : STRING;
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                port_extclk0            : STRING;
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                port_extclk1            : STRING;
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                port_extclk2            : STRING;
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                port_extclk3            : STRING;
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                width_clock             : NATURAL
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        );
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        PORT (
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                        clk     : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
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                        inclk   : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
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        );
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        END COMPONENT;
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BEGIN
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        sub_wire4_bv(0 DOWNTO 0) <= "0";
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        sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
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        sub_wire1    <= sub_wire0(0);
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        c0    <= sub_wire1;
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        sub_wire2    <= inclk0;
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        sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
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        altpll_component : altpll
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        GENERIC MAP (
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                bandwidth_type => "AUTO",
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                clk0_divide_by => divide_by,
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                clk0_duty_cycle => 50,
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                clk0_multiply_by => multiply_by,
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                clk0_phase_shift => "0",
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                compensate_clock => "CLK0",
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                inclk0_input_frequency => 50000,
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                intended_device_family => "Cyclone III",
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                lpm_hint => "CBX_MODULE_PREFIX=pll",
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                lpm_type => "altpll",
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                operation_mode => "NORMAL",
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                pll_type => "AUTO",
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                port_activeclock => "PORT_UNUSED",
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                port_areset => "PORT_UNUSED",
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                port_clkbad0 => "PORT_UNUSED",
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                port_clkbad1 => "PORT_UNUSED",
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                port_clkloss => "PORT_UNUSED",
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                port_clkswitch => "PORT_UNUSED",
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                port_configupdate => "PORT_UNUSED",
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                port_fbin => "PORT_UNUSED",
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                port_inclk0 => "PORT_USED",
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                port_inclk1 => "PORT_UNUSED",
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                port_locked => "PORT_UNUSED",
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                port_pfdena => "PORT_UNUSED",
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                port_phasecounterselect => "PORT_UNUSED",
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                port_phasedone => "PORT_UNUSED",
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                port_phasestep => "PORT_UNUSED",
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                port_phaseupdown => "PORT_UNUSED",
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                port_pllena => "PORT_UNUSED",
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                port_scanaclr => "PORT_UNUSED",
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                port_scanclk => "PORT_UNUSED",
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                port_scanclkena => "PORT_UNUSED",
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                port_scandata => "PORT_UNUSED",
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                port_scandataout => "PORT_UNUSED",
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                port_scandone => "PORT_UNUSED",
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                port_scanread => "PORT_UNUSED",
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                port_scanwrite => "PORT_UNUSED",
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                port_clk0 => "PORT_USED",
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                port_clk1 => "PORT_UNUSED",
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                port_clk2 => "PORT_UNUSED",
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                port_clk3 => "PORT_UNUSED",
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                port_clk4 => "PORT_UNUSED",
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                port_clk5 => "PORT_UNUSED",
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                port_clkena0 => "PORT_UNUSED",
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                port_clkena1 => "PORT_UNUSED",
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                port_clkena2 => "PORT_UNUSED",
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                port_clkena3 => "PORT_UNUSED",
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                port_clkena4 => "PORT_UNUSED",
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                port_clkena5 => "PORT_UNUSED",
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                port_extclk0 => "PORT_UNUSED",
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                port_extclk1 => "PORT_UNUSED",
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                port_extclk2 => "PORT_UNUSED",
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                port_extclk3 => "PORT_UNUSED",
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                width_clock => 5
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        )
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        PORT MAP (
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                inclk => sub_wire3,
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                clk => sub_wire0
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        );
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END SYN;
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