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[/] [leros/] [trunk/] [vhdl/] [altera/] [cyc_pll.vhd] - Blame information for rev 3

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1 3 martin
--
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--
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--  This file is a part of JOP, the Java Optimized Processor
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--
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--  Copyright (C) 2001-2008, Martin Schoeberl (martin@jopdesign.com)
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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-- as generated by the wizzard and added generic
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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ENTITY pll IS
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        generic (multiply_by : natural; divide_by : natural);
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        PORT
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        (
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                inclk0          : IN STD_LOGIC  := '0';
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                c0              : OUT STD_LOGIC
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        );
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END pll;
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ARCHITECTURE SYN OF pll IS
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        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (5 DOWNTO 0);
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        SIGNAL sub_wire1        : STD_LOGIC ;
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        SIGNAL sub_wire2        : STD_LOGIC ;
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        SIGNAL sub_wire3        : STD_LOGIC_VECTOR (1 DOWNTO 0);
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        SIGNAL sub_wire4_bv     : BIT_VECTOR (0 DOWNTO 0);
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        SIGNAL sub_wire4        : STD_LOGIC_VECTOR (0 DOWNTO 0);
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        COMPONENT altpll
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        GENERIC (
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                clk0_duty_cycle         : NATURAL;
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                lpm_type                : STRING;
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                clk0_multiply_by                : NATURAL;
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                inclk0_input_frequency          : NATURAL;
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                clk0_divide_by          : NATURAL;
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                pll_type                : STRING;
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                clk0_time_delay         : STRING;
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                intended_device_family          : STRING;
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                operation_mode          : STRING;
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                compensate_clock                : STRING;
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                clk0_phase_shift                : STRING
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        );
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        PORT (
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                        inclk   : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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                        clk     : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
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        );
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        END COMPONENT;
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BEGIN
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        sub_wire4_bv(0 DOWNTO 0) <= "0";
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        sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
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        sub_wire1    <= sub_wire0(0);
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        c0    <= sub_wire1;
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        sub_wire2    <= inclk0;
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        sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
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        altpll_component : altpll
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        GENERIC MAP (
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                clk0_duty_cycle => 50,
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                lpm_type => "altpll",
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                clk0_multiply_by => multiply_by,
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                inclk0_input_frequency => 50000,        -- 20MHz = 50000ps
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                clk0_divide_by => divide_by,
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                pll_type => "AUTO",
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                clk0_time_delay => "0",
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                intended_device_family => "Cyclone",
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                operation_mode => "NORMAL",
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                compensate_clock => "CLK0",
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                clk0_phase_shift => "0"
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        )
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        PORT MAP (
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                inclk => sub_wire3,
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                clk => sub_wire0
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        );
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END SYN;
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