Subversion Repositories leros

--

--  Copyright 2011 Martin Schoeberl <masca@imm.dtu.dk>,

--                 Technical University of Denmark, DTU Informatics. 

--  All rights reserved.

--

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions are met:

-- 

--    1. Redistributions of source code must retain the above copyright notice,

--       this list of conditions and the following disclaimer.

-- 

--    2. Redistributions in binary form must reproduce the above copyright

--       notice, this list of conditions and the following disclaimer in the

--       documentation and/or other materials provided with the distribution.

-- 

-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY EXPRESS

-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN

-- NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY

-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-- 

-- The views and conclusions contained in the software and documentation are

-- those of the authors and should not be interpreted as representing official

-- policies, either expressed or implied, of the copyright holder.

-- 

--

-- Top level of the Leros CPU

-- That should be instanziated in a FPGA specific top level

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.leros_types.all;

entity leros is

        port  (

                clk : in std_logic;

                reset : in std_logic;

                ioout : out io_out_type;

                ioin : in io_in_type

        );

end leros;

architecture rtl of leros is

        signal fdin : fedec_in_type;

        signal fdout : fedec_out_type;

        signal exout : ex_out_type;

begin

        fdin.accu <= exout.accu;

        fdin.dm_data <= exout.dm_data;

        ioout.addr <= fdout.imm(7 downto 0);

        ioout.rd <= fdout.dec.inp;

        ioout.wr <= fdout.dec.outp;

        ioout.wrdata <= exout.accu;

        fd: entity work.leros_fedec port map (

                clk, reset, fdin, fdout

        );

        ex: entity work.leros_ex port map(

                clk, reset, fdout, ioin, exout

        );

end rtl;