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--
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-- Copyright 2011 Martin Schoeberl <masca@imm.dtu.dk>,
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-- Technical University of Denmark, DTU Informatics.
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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-- NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- The views and conclusions contained in the software and documentation are
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-- those of the authors and should not be interpreted as representing official
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-- policies, either expressed or implied, of the copyright holder.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.leros_types.all;
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-- instruction memory
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-- write is ignored for now
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-- the content should be generated by an assembler
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entity leros_im is
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port (
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clk : in std_logic;
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reset : in std_logic;
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din : in im_in_type;
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dout : out im_out_type
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);
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end leros_im;
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architecture rtl of leros_im is
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signal areg : std_logic_vector(IM_BITS-1 downto 0);
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signal data : std_logic_vector(15 downto 0);
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begin
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process(clk) begin
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if rising_edge(clk) then
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areg <= din.rdaddr;
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end if;
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end process;
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dout.data <= data;
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rom: entity work.leros_rom port map(areg, data);
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-- use generated table
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-- process(areg) begin
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--
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-- case areg is
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--
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-- when X"00" => data <= X"0000"; -- never executed
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-- when X"01" => data <= X"0805"; -- load imm
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-- when X"02" => data <= X"0e01"; -- sub 1
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-- when X"03" => data <= X"0e01"; -- sub 1
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-- when X"04" => data <= X"f000"; -- nop
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-- when X"05" => data <= X"10fe"; -- brnz
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-- when X"06" => data <= X"f000"; -- nop
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-- when X"07" => data <= X"0801"; -- load 1
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-- when X"08" => data <= X"2000"; -- outp
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-- when X"09" => data <= X"0805"; -- load imm
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-- when X"0a" => data <= X"0e01"; -- sub 1
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-- when X"0b" => data <= X"0e01"; -- sub 1
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-- when X"0c" => data <= X"f000"; -- nop
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-- when X"0d" => data <= X"10fe"; -- brnz
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-- when X"0e" => data <= X"f000"; -- nop
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-- when X"0f" => data <= X"0800"; -- load 0
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-- when X"10" => data <= X"2000"; -- outp
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-- when X"11" => data <= X"0801"; -- load imm
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-- when X"12" => data <= X"f000"; -- nop
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-- when X"13" => data <= X"10ee"; -- brnz
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-- when others => data <= X"f000";
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-- end case;
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-- end process;
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end rtl;
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