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--
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-- Copyright 2011 Martin Schoeberl <masca@imm.dtu.dk>,
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-- Technical University of Denmark, DTU Informatics.
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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-- NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- The views and conclusions contained in the software and documentation are
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-- those of the authors and should not be interpreted as representing official
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-- policies, either expressed or implied, of the copyright holder.
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--
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--
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-- Just test fmax of memory with registered input and output
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity memfmax is
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port (
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clk : std_logic;
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din : in std_logic_vector(15 downto 0);
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rd_addr, wr_addr : in std_logic_vector(7 downto 0);
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wr : in std_logic;
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dout : out std_logic_vector(15 downto 0)
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);
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end memfmax;
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architecture rtl of memfmax is
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signal clk_int : std_logic;
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-- the data ram
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constant nwords : integer := 2 ** 8;
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type ram_type is array(0 to nwords-1) of std_logic_vector(15 downto 0);
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signal ram : ram_type;
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signal wr_reg : std_logic;
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signal wrdata, rddata : std_logic_vector(15 downto 0);
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signal wraddr, rdaddr : std_logic_vector(7 downto 0);
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begin
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-- -- Altera PLL
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-- -- assume 20 or 50 MHz input clock
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-- pll_inst : entity work.pll generic map(
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-- multiply_by => 20, -- 300 MHz
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-- divide_by => 1
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-- )
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-- port map (
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-- inclk0 => clk,
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-- c0 => clk_int
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-- );
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-- Xilinx DCM
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-- input clock is 50 MHz
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-- let's go for 200 MHz ;-)
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pll_inst : entity work.sp3epll generic map(
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multiply_by => 8,
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divide_by => 1
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)
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port map (
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CLKIN_IN => clk,
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RST_IN => '0',
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CLKFX_OUT => clk_int,
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CLKIN_IBUFG_OUT => open,
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CLK0_OUT => open,
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LOCKED_OUT => open
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);
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process (clk_int)
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begin
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if rising_edge(clk_int) then
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if wr_reg='1' then
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ram(to_integer(unsigned(wraddr))) <= wrdata;
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end if;
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rddata <= ram(to_integer(unsigned(rdaddr)));
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wrdata <= din;
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rdaddr <= rd_addr;
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wraddr <= wr_addr;
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wr_reg <= wr;
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dout <= rddata;
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end if;
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end process;
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end rtl;
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