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[/] [lfsr_randgen/] [trunk/] [lfsr_tb.vhd] - Blame information for rev 4

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1 2 lal87
----------------------------------------------------------------------------
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---- Create Date:    20:14:07 07/28/2010                                                                                        ----            
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---- Design Name: lfsr_tb                                                                                                                               ----                            
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---- Project Name: lfsr_randgen                                                                                                    ---- 
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---- Description:                                                                                                                                               ----    
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----  A testbench code for the lfsr.vhd code                            ----
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----                                                                                                                                                                                    ----    
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----------------------------------------------------------------------------
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----                                                                    ----
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---- This file is a part of the lfsr_randgen project at                 ----
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---- http://www.opencores.org/                                                                  ----
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----                                                                    ----
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---- Author(s):                                                         ----
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----   Vipin Lal, lalnitt@gmail.com                                     ----
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----                                                                    ----
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----------------------------------------------------------------------------
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----                                                                    ----
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---- Copyright (C) 2010 Authors and OPENCORES.ORG                       ----
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----                                                                    ----
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---- This source file may be used and distributed without               ----
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---- restriction provided that this copyright statement is not          ----
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---- removed from the file and that any derivative work contains        ----
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---- the original copyright notice and the associated disclaimer.       ----
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----                                                                    ----
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---- This source file is free software; you can redistribute it         ----
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---- and/or modify it under the terms of the GNU Lesser General         ----
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---- Public License as published by the Free Software Foundation;       ----
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---- either version 2.1 of the License, or (at your option) any         ----
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---- later version.                                                     ----
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----                                                                    ----
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---- This source is distributed in the hope that it will be             ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied         ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ----
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---- PURPOSE. See the GNU Lesser General Public License for more        ----
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---- details.                                                           ----
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----                                                                    ----
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---- You should have received a copy of the GNU Lesser General          ----
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---- Public License along with this source; if not, download it         ----
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---- from http://www.opencores.org/lgpl.shtml                           ----
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----                                                                    ----
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity lfsr_tb is
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end lfsr_tb;
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architecture behavior of lfsr_tb is
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        constant width : integer :=8;     --change the width value here for a different regsiter width.
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   signal clk,set_seed : std_logic := '0';
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   signal seed : std_logic_vector(width-1 downto 0) := (0 => '1',others => '0');
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   signal rand_out : std_logic_vector(width-1 downto 0);
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   -- clock period definitions
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   constant clk_period : time := 1 ns;
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begin
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        -- entity instantiation for the lfsr component.
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   uut: entity work.lfsr generic map (width => width)    --change the width value here for a different regsiter width.
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        PORT MAP (
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          clk => clk,
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                         set_seed => set_seed,
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          seed => seed,
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          rand_out => rand_out
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        );
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   -- Clock process definitions
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   clk_process :process
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   begin
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                clk <= '0';
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                wait for clk_period/2;
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                clk <= '1';
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                wait for clk_period/2;
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   end process;
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   -- Applying stimulation inputs.
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   stim_proc: process
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   begin
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        wait for 10 ns;
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        set_seed <= '1';
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        wait for 1 ns;
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        set_seed <= '0';
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        wait for 20 ns;
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      wait;
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   end process;
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END;

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