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#***********************************************************************************
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#* Project: Avnet Spartan-3A Evaluation Board (XC3S400A-4FTG256C)
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#*
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#* File Name: Avnet_Sp3A_Eval.ucf
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#* Revision: 1.1
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#* Date: December 1, 2008
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#*
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#* Description: Master UCF for the Sp3A Eval board
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#*
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#************************************************************************************
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CONFIG VCCAUX = "3.3" ;
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# Clock Period Constraint, 16 MHz on-board clock
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Net CLK_16MHZ TNM_NET = CLK_16MHZ;
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TIMESPEC TS_CLK_16MHZ = PERIOD CLK_16MHZ 62.50 ns;
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# I/O Timing Constraints
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OFFSET = IN 10 ns BEFORE CLK_16MHZ;
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OFFSET = OUT 10 ns AFTER CLK_16MHZ;
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# I/O Location Constraints
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# Clocks
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NET CLK_12MHZ LOC = N9 | IOSTANDARD = LVCMOS33 ; # CLK_12MHZ
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NET CLK_16MHZ LOC = C10 | IOSTANDARD = LVCMOS33 ; # CLK_16MHZ
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NET CLK_32KHZ LOC = T7 | IOSTANDARD = LVCMOS33 ; # CLK_32KHZ
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# Parallel Flash
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NET FLASH_A[0] LOC = P16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[0, also D15
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NET FLASH_A[1] LOC = N16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[1
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NET FLASH_A[2] LOC = L13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[2
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NET FLASH_A[3] LOC = K13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[3
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NET FLASH_A[4] LOC = M15 | IOSTANDARD = LVCMOS33 ; # FLASH_A[4
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NET FLASH_A[5] LOC = M16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[5
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NET FLASH_A[6] LOC = L14 | IOSTANDARD = LVCMOS33 ; # FLASH_A[6
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NET FLASH_A[7] LOC = L16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[7
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NET FLASH_A[8] LOC = J12 | IOSTANDARD = LVCMOS33 ; # FLASH_A[8
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NET FLASH_A[9] LOC = J13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[9
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NET FLASH_A[10] LOC = G16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[10
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NET FLASH_A[11] LOC = F16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[11
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NET FLASH_A[12] LOC = H13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[12
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NET FLASH_A[13] LOC = G14 | IOSTANDARD = LVCMOS33 ; # FLASH_A[13
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NET FLASH_A[14] LOC = E16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[14
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NET FLASH_A[15] LOC = F15 | IOSTANDARD = LVCMOS33 ; # FLASH_A[15
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NET FLASH_A[16] LOC = G13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[16
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NET FLASH_A[17] LOC = F14 | IOSTANDARD = LVCMOS33 ; # FLASH_A[17
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NET FLASH_A[18] LOC = E14 | IOSTANDARD = LVCMOS33 ; # FLASH_A[18
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NET FLASH_A[19] LOC = F13 | IOSTANDARD = LVCMOS33 ; # FLASH_A[19
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NET FLASH_A[20] LOC = D16 | IOSTANDARD = LVCMOS33 ; # FLASH_A[20
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NET FLASH_A[21] LOC = D15 | IOSTANDARD = LVCMOS33 ; # FLASH_A[21
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NET FLASH_BYTEn LOC = N14 | IOSTANDARD = LVCMOS33 ; # FLASH_BYTE#
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NET FLASH_CEn LOC = P15 | IOSTANDARD = LVCMOS33 ; # FLASH_CE#
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NET FLASH_D[0] LOC = T14 | IOSTANDARD = LVCMOS33 ; # FLASH_D0
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NET FLASH_D[1] LOC = R13 | IOSTANDARD = LVCMOS33 ; # FLASH_D1
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NET FLASH_D[2] LOC = T13 | IOSTANDARD = LVCMOS33 ; # FLASH_D2
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NET FLASH_D[3] LOC = P12 | IOSTANDARD = LVCMOS33 ; # FLASH_D3
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NET FLASH_D[4] LOC = N8 | IOSTANDARD = LVCMOS33 ; # FLASH_D4
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NET FLASH_D[5] LOC = P7 | IOSTANDARD = LVCMOS33 ; # FLASH_D5
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NET FLASH_D[6] LOC = T6 | IOSTANDARD = LVCMOS33 ; # FLASH_D6
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NET FLASH_D[7] LOC = T5 | IOSTANDARD = LVCMOS33 ; # FLASH_D7
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NET FLASH_D[8] LOC = P11 | IOSTANDARD = LVCMOS33 ; # FLASH_D8
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NET FLASH_D[9] LOC = R3 | IOSTANDARD = LVCMOS33 ; # FLASH_D9
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NET FLASH_D[10] LOC = N11 | IOSTANDARD = LVCMOS33 ; # FLASH_D10
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NET FLASH_D[11] LOC = N7 | IOSTANDARD = LVCMOS33 ; # FLASH_D11
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NET FLASH_D[12] LOC = R5 | IOSTANDARD = LVCMOS33 ; # FLASH_D12
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NET FLASH_D[13] LOC = T4 | IOSTANDARD = LVCMOS33 ; # FLASH_D13
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NET FLASH_D[14] LOC = P6 | IOSTANDARD = LVCMOS33 ; # FLASH_D14
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NET FLASH_OEn LOC = R15 | IOSTANDARD = LVCMOS33 ; # FLASH_OE#
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NET FLASH_RESETn LOC = T10 | IOSTANDARD = LVCMOS33 ; # FLASH_RESET#
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NET FLASH_RY_BYn LOC = A4 | IOSTANDARD = LVCMOS33 ; # FLASH_RY/BY#
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NET FLASH_WEn LOC = N13 | IOSTANDARD = LVCMOS33 ; # FLASH_WE#
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# Serial flash
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NET FPGA_MOSI LOC = P10 | IOSTANDARD = LVCMOS33 ; # NetR53_2
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NET FPGA_SPI_SELn LOC = T2 | IOSTANDARD = LVCMOS33 ; # FPGA_SPI_SEL#
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NET SF_HOLDn LOC = P13 | IOSTANDARD = LVCMOS33 ; # SF_HOLD#
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NET SF_Wn LOC = N12 | IOSTANDARD = LVCMOS33 ; # SF_W#
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NET SPI_CLK LOC = R14 | IOSTANDARD = LVCMOS33 ; # SPI_CLK
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#NET FLASH_D00 LOC = T14 | IOSTANDARD = LVCMOS33 ; # MISO, shared with parallel flash
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# User I/O
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NET FPGA_RESET LOC = H4 | IOSTANDARD = LVCMOS33 ; # FPGA_RESET
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NET FPGA_PUSH_A LOC = K3 | IOSTANDARD = LVCMOS33 ; # FPGA_PUSH_A
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NET FPGA_PUSH_B LOC = H5 | IOSTANDARD = LVCMOS33 ; # FPGA_PUSH_B
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NET FPGA_PUSH_C LOC = L3 | IOSTANDARD = LVCMOS33 ; # FPGA_PUSH_C
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NET LEDS[0] LOC = D14 | IOSTANDARD = LVCMOS33 ; # LED1
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NET LEDS[1] LOC = C16 | IOSTANDARD = LVCMOS33 ; # LED2
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NET LEDS[2] LOC = C15 | IOSTANDARD = LVCMOS33 ; # LED3
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NET LEDS[3] LOC = B15 | IOSTANDARD = LVCMOS33 ; # LED4
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# I2C
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NET IIC_SCL LOC = M14 | IOSTANDARD = LVCMOS33 ; # IIC_SCL
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NET IIC_SDA LOC = M13 | IOSTANDARD = LVCMOS33 ; # IIC_SDA
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# PSoC
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NET PSOC_P0_4 LOC = J1 | IOSTANDARD = LVCMOS33 ; # PSOC_P0_4
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NET PSOC_P2_1 LOC = F1 | IOSTANDARD = LVCMOS33 ; # PSOC_P2_1
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NET PSOC_P2_3 LOC = G2 | IOSTANDARD = LVCMOS33 ; # PSOC_P2_3
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NET PSOC_P2_5 LOC = H3 | IOSTANDARD = LVCMOS33 ; # PSOC_P2_5
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NET PSOC_P2_7 LOC = H1 | IOSTANDARD = LVCMOS33 ; # PSOC_P2_7
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NET PSOC_P4_6 LOC = J2 | IOSTANDARD = LVCMOS33 ; # PSOC_P4_6
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NET PSOC_P5_3 LOC = L2 | IOSTANDARD = LVCMOS33 ; # PSOC_P5_3
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NET PSOC_P5_4 LOC = M3 | IOSTANDARD = LVCMOS33 ; # PSOC_P5_4
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NET PSOC_P5_6 LOC = M4 | IOSTANDARD = LVCMOS33 ; # PSOC_P5_6
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NET PSOC_P5_7 LOC = L1 | IOSTANDARD = LVCMOS33 ; # PSOC_P5_7
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NET PSOC_P7_0 LOC = N3 | IOSTANDARD = LVCMOS33 ; # PSOC_P7_0
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NET PSOC_P7_7 LOC = K16 | IOSTANDARD = LVCMOS33 ; # PSOC_P7_7
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# UART
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# Net names UART_RXD and UART_TXD on the schematic are named in terms of the PSoC connection.
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# Net UART_RXD is an output from the FPGA and an input to the PSoC. Connect to FPGA Tx.
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# Net UART_TXD is an input to the FPGA and an output from the PSoC. Connect to FPGA Rxx.
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NET UART_RXD LOC = B3 | IOSTANDARD = LVCMOS33 ; # UART_RXD
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NET UART_TXD LOC = A3 | IOSTANDARD = LVCMOS33 ; # UART_TXD
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# GPIO
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#NET BANK0_IO01 LOC = A14 | IOSTANDARD = LVCMOS33 ; # BANK0_IO1
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#NET BANK0_IO02 LOC = C4 | IOSTANDARD = LVCMOS33 ; # BANK0_IO2
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#NET BANK0_IO03 LOC = A13 | IOSTANDARD = LVCMOS33 ; # BANK0_IO3
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#NET BANK0_IO04 LOC = B14 | IOSTANDARD = LVCMOS33 ; # BANK0_IO4
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#NET BANK0_IO05 LOC = C13 | IOSTANDARD = LVCMOS33 ; # BANK0_IO5
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#NET BANK0_IO06 LOC = D13 | IOSTANDARD = LVCMOS33 ; # BANK0_IO6
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#NET BANK0_IO07 LOC = A12 | IOSTANDARD = LVCMOS33 ; # BANK0_IO7
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#NET BANK0_IO08 LOC = C12 | IOSTANDARD = LVCMOS33 ; # BANK0_IO8
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#NET BANK0_IO09 LOC = B12 | IOSTANDARD = LVCMOS33 ; # BANK0_IO9
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#NET BANK0_IO10 LOC = D11 | IOSTANDARD = LVCMOS33 ; # BANK0_IO10
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#NET BANK0_IO11 LOC = A11 | IOSTANDARD = LVCMOS33 ; # BANK0_IO11
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#NET BANK0_IO12 LOC = C11 | IOSTANDARD = LVCMOS33 ; # BANK0_IO12
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#NET BANK0_IO13 LOC = A10 | IOSTANDARD = LVCMOS33 ; # BANK0_IO13
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#NET BANK0_IO14 LOC = D10 | IOSTANDARD = LVCMOS33 ; # BANK0_IO14
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#NET BANK0_IO15 LOC = A9 | IOSTANDARD = LVCMOS33 ; # BANK0_IO15
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#NET BANK0_IO16 LOC = E10 | IOSTANDARD = LVCMOS33 ; # BANK0_IO16
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#NET BANK0_IO17 LOC = C9 | IOSTANDARD = LVCMOS33 ; # BANK0_IO17
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#NET BANK0_IO18 LOC = D9 | IOSTANDARD = LVCMOS33 ; # BANK0_IO18
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#NET BANK0_IO19 LOC = A8 | IOSTANDARD = LVCMOS33 ; # BANK0_IO19
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#NET BANK0_IO20 LOC = C8 | IOSTANDARD = LVCMOS33 ; # BANK0_IO20
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#NET BANK0_IO21 LOC = B8 | IOSTANDARD = LVCMOS33 ; # BANK0_IO21
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#NET BANK0_IO22 LOC = E7 | IOSTANDARD = LVCMOS33 ; # BANK0_IO22
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#NET BANK0_IO23 LOC = A7 | IOSTANDARD = LVCMOS33 ; # BANK0_IO23
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#NET BANK0_IO24 LOC = D8 | IOSTANDARD = LVCMOS33 ; # BANK0_IO24
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#NET BANK0_IO25 LOC = C7 | IOSTANDARD = LVCMOS33 ; # BANK0_IO25
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#NET BANK0_IO26 LOC = D7 | IOSTANDARD = LVCMOS33 ; # BANK0_IO26
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#NET BANK0_IO27 LOC = A6 | IOSTANDARD = LVCMOS33 ; # BANK0_IO27
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#NET BANK0_IO28 LOC = C6 | IOSTANDARD = LVCMOS33 ; # BANK0_IO28
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#NET BANK0_IO29 LOC = B6 | IOSTANDARD = LVCMOS33 ; # BANK0_IO29
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#NET BANK0_IO30 LOC = C5 | IOSTANDARD = LVCMOS33 ; # BANK0_IO30
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#NET BANK0_IO31 LOC = A5 | IOSTANDARD = LVCMOS33 ; # BANK0_IO31
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#NET BANK0_IO32 LOC = B4 | IOSTANDARD = LVCMOS33 ; # BANK0_IO32
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#NET BANK1_IO01 LOC = E13 | IOSTANDARD = LVCMOS33 ; # BANK1_IO1
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#NET BANK3_IO01 LOC = D3 | IOSTANDARD = LVCMOS33 ; # BANK3_IO1
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#NET BANK3_IO02 LOC = D4 | IOSTANDARD = LVCMOS33 ; # BANK3_IO2
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# Digi Headers
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NET DIGI1[0] LOC = R1 | IOSTANDARD = LVCMOS33 ; # DIGI1_0
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NET DIGI1[1] LOC = P2 | IOSTANDARD = LVCMOS33 ; # DIGI1_1
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NET DIGI1[2] LOC = P1 | IOSTANDARD = LVCMOS33 ; # DIGI1_2
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NET DIGI1[3] LOC = N2 | IOSTANDARD = LVCMOS33 ; # DIGI1_3
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NET DIGI2[0] LOC = N1 | IOSTANDARD = LVCMOS33 ; # DIGI2_0
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NET DIGI2[1] LOC = M1 | IOSTANDARD = LVCMOS33 ; # DIGI2_1
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NET DIGI2[2] LOC = K1 | IOSTANDARD = LVCMOS33 ; # DIGI2_2
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NET DIGI2[3] LOC = G1 | IOSTANDARD = LVCMOS33 ; # DIGI2_3
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# Miscellaneous
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#NET AWAKE LOC = T11 | IOSTANDARD = LVCMOS33 ; # AWAKE
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#NET DOUT LOC = R11 | IOSTANDARD = LVCMOS33 ; # DOUT
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#NET FPGA_VS0 LOC = P5 | IOSTANDARD = LVCMOS33 ; # FPGA_VS0
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#NET FPGA_VS1 LOC = N6 | IOSTANDARD = LVCMOS33 ; # FPGA_VS1
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#NET FPGA_VS2 LOC = T3 | IOSTANDARD = LVCMOS33 ; # FPGA_VS2
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# Prohibit Special Pins
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# CONFIG PROHIBIT = [pin]; # Reserved for [signal]
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CONFIG PROHIBIT = T12 ; # FPGA_INIT_B
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CONFIG PROHIBIT = D5 ; # FPGA_PUDC
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CONFIG PROHIBIT = P4 ; # PSOC_FPGA_M0
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CONFIG PROHIBIT = N4 ; # PSOC_FPGA_M1
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CONFIG PROHIBIT = R2 ; # PSOC_FPGA_M2
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