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[/] [light52/] [trunk/] [sim/] [light52_tb.do] - Blame information for rev 2

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1 2 ja_rd
# Run main test bench: opcode test assembled for 'default' CPU -- the CPU with
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# BCD instructions NOT implemented.
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# assumed to run from //sim
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vlib work
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vcom -reportprogress 300 -work work ../vhdl/light52_pkg.vhdl
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vcom -reportprogress 300 -work work ../vhdl/light52_ucode_pkg.vhdl
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# Use object code package from 'default' opcode tester.
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vcom -reportprogress 300 -work work ../test/cpu_test/obj_code_pkg.vhdl
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vcom -reportprogress 300 -work work ../vhdl/light52_muldiv.vhdl
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vcom -reportprogress 300 -work work ../vhdl/light52_alu.vhdl
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vcom -reportprogress 300 -work work ../vhdl/light52_cpu.vhdl
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vcom -reportprogress 300 -work work ../vhdl/light52_timer.vhdl
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vcom -reportprogress 300 -work work ../vhdl/light52_uart.vhdl
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vcom -reportprogress 300 -work work ../vhdl/light52_mcu.vhdl
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vcom -reportprogress 300 -work work ../vhdl/tb/txt_util.vhdl
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vcom -reportprogress 300 -work work ../vhdl/tb/light52_tb_pkg.vhdl
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vcom -reportprogress 300 -work work ../vhdl/tb/light52_tb.vhdl
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# Simulate default system: all generics have default values.
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vsim -t ps -gBCD=false work.light52_tb(testbench)
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do ./light52_tb_wave.do
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set PrefMain(font) {Courier 9 roman normal}

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