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ja_rd |
/**
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@file b51_cpu.h
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@brief CPU model.
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This file includes the CPU simulation model. Excludes the behavior of the
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CPU peripherals, which is done in b51_mcu.c.
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When implementing different CPU core models, you should modify this file
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by adding conditional code and new functions. Differences between CPU
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cores are going to be small enough -- cycle counts, implementation of
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certain instructions, etc.
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Different cores will have a different set of peripherals, though. That must
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be modelled with a function pointer table against different b51_mcu
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implementations -- meaning one different source file per different core.
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TODO CPU & MCU polymorphism to be done.
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*/
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#ifndef S51_H_INCLUDED
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#define S51_H_INCLUDED
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#include <stdint.h>
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#include <stdbool.h>
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#include "b51_mcu.h"
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#include "b51_log.h"
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/*-- Configuration macros ----------------------------------------------------*/
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/** Size of IRAM in bytes */
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#define MAX_IDATA_SIZE (256)
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/*-- Public data types & macros ----------------------------------------------*/
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/**
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MCS51 CPU SFRs.
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FIXME should only include the CPU SFRs and not the peripherals.
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Note that ACC, while accessible as an SFR, is not in this struct and is
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handled separately.
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*/
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typedef struct cpu51_sfr_s {
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uint8_t b;
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uint8_t dph;
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uint8_t dpl;
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uint8_t ie;
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uint8_t ip;
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uint8_t p0;
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uint8_t p1;
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uint8_t p2;
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uint8_t p3;
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uint8_t pcon;
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uint8_t psw;
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uint8_t sbuf;
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uint8_t scon;
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uint8_t sp;
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uint8_t tcon;
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uint8_t th0;
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uint8_t th1;
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uint8_t tl0;
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uint8_t tl1;
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uint8_t tmod;
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} cpu51_sfr_t;
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typedef struct cpu51_options_s {
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bool bcd;
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} cpu51_options_t;
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/**
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CPU object. This is the CPU model, which includes the peripherals block
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and the XDATA and XCODE memory blocks as a member object (struct field).
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*/
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typedef struct cpu51_s {
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uint8_t idata[MAX_IDATA_SIZE]; /**< IDATA RAM */
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uint16_t pc; /**< PC -- addr of instruction being run */
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uint8_t a; /**< ACC */
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cpu51_sfr_t sfr; /**< CPU core (non-peripheral) SFRs */
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mcu51_t mcu; /**< MCU peripherals model */
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uint32_t cycles; /**< Clock cycles since last reset */
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bool max_cycle_count; /**< Last instr. used the max # of cycles */
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bool implemented_as_nop; /**< Last instr. was decoded as NOP */
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log51_t log; /**< Logger data */
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uint16_t breakpoint; /**< Address of breakpoint */
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cpu51_options_t options; /**< Core implementation options */
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} cpu51_t;
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/*-- Public functions --------------------------------------------------------*/
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/**
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Initialize CPU model, including peripheral models.
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This does not reset the CPU or the peripherals.
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Use at least once before calling any other function in this API.
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@arg cpu CPU model.
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*/
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extern void cpu_init(cpu51_t *cpu);
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/**
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Simulate a CPU reset, which includes the peripherals too.
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@arg cpu CPU model.
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*/
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extern void cpu_reset(cpu51_t *cpu);
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/**
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Run a number of CPU instructions.
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Execution will stop after running num_inst instructions, or if a
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single-instruction infinite loop is detected, or if a breakpoint is hit.
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@arg cpu CPU model.
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@arg num_inst Number of instructions to be run.
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@return 0 if execution timed out,
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1 if it was interrupted,
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2 for breakpoints.
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*/
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extern uint32_t cpu_exec(cpu51_t *cpu, uint32_t num_inst);
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/**
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Load object code onto XCODE memory.
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Every object byte that fits the XCODE memory will be loaded onto it.
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Note that bytes out of memory bounds will be dropped silently.
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@arg cpu CPU model.
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@arg hex_filename Nam of Intel-HEX file to be loaded.
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@return Number of bytes read from HEX file -- some may have been dropped!.
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*/
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extern uint16_t cpu_load_code(cpu51_t *cpu, const char *hex_filename);
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/**
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Add a new breakpoint at given address.
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The only reasons this function might fail (returning false) are:
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-# Breakpoint address out of XCODE bounds.
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-# Too many breakpoints.
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There's no way to delete breakpoints, and the logic is still weak so this
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must be considered a stub.
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@arg cpu CPU model.
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@arg address Breakpoint address.
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@return True if the breakpoint could be added.
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*/
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extern bool cpu_add_breakpoint(cpu51_t *cpu, uint16_t address);
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#endif // S51_H_INCLUDED
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