Subversion Repositories light52

--------------------------------------------------------------------------------

-- light52_cpu.vhdl -- light52 MCS51-compatible CPU core.

--------------------------------------------------------------------------------

-- This is a 'naive' implementation of the MCS51 architecture that trades area 

-- for speed. 

-- 

-- At the bottom of the file there are some design notes referenced throughout

-- the code ('@note1' etc.).

--------------------------------------------------------------------------------

-- GENERICS:

--

--

-- IMPLEMENT_BCD_INSTRUCTIONS   -- Whether or not to implement BCD instructions.

--  When true, instructions DA and XCHD will work as in the original MCS51.

--  When false, those instructions will work as NOP, saving some logic.

--

-- SEQUENTIAL_MULTIPLIER        -- Sequential vs. combinational multiplier.

--  When true, a sequential implementation will be used for the multiplier, 

--  which will usually save a lot of logic or a dedicated multiplier.

--  When false, a combinational registered multiplier will be used.

--  (NOT IMPLEMENTED -- setting it to true will raise an assertion failure).

--

-- USE_BRAM_FOR_XRAM            -- Use extra space in IRAM/uCode RAM as XRAM.

--  When true, extra logic will be generated so that the extra space in the 

--  RAM block used for IRAM/uCode can be used as XRAM.

--  This prevents RAM waste at some cost in area and clock rate.

--  When false, any extra space in the IRAM physical block will be wasted.

--

--------------------------------------------------------------------------------

-- INTERFACE SIGNALS:

--

-- clk :                Clock, active rising edge.

-- reset :              Synchronous reset, hold for at least 1 cycle.

--

--                      XCODE is assumed to be a synchronous ROM:

--

-- code_addr :          XCODE space address. 

-- code_rd :            XCODE read data. Must be valid at all times with 1 

--                      cycle of latency (synchronous memory):

--                      code_rd[n] := XCODE(code_addr[n-1])

--

--                      Interrupts are   

--

-- irq_source :         Interrupt inputs. 

--                      0 is for vector 03h, 4 is for vector 23h.

--                      Not registsred; must be synchronous and remain high 

--                      through a fetch_1 state in order to be acknowledged.

--                      Priorities are fixed: 0 highest, 4 lowest.

--

--                      XDATA is expected to be a synchronous 1-port RAM:

--

-- xdata_addr :         XDATA space address, valid when xdata_vma is '1'.

-- xdata_vma :          Asserted high when an XDATA rd/wr cycle is being done.

-- xdata_rd :           Read data. Must be valid the cycle after xdata_vma is

--                      asserted with xdata_we='0'.

-- xdata_wr :           Write data. Valid when xdata_vma is asserted with 

--                      xdata_we='1';

-- xdata_we :           '1' for XDATA write cycles, '0' for read cycles.

--

--                      SFRs external to the CPU are accessed as synchonous RAM:

--

-- sfr_addr :           SFR space address, valid when sfr_vma='1'.

-- sfr_vma :            Asserted high when an SFR rd/wr cycle is being done. 

-- sfr_rd :             Read data. Must be valid the cycle after sfr_vma is

--                      asserted with sfr_we='0'.

-- sfr_wr :             Write data. Valid when sfr_vma is asserted with 

--                      sfr_we='1';

-- sfr_we :             '1' for SFR write cycles, '0' for read cycles.

--

--  Note there's no code_vma. Even if there was one, see limitation #1 below. 

--------------------------------------------------------------------------------

-- MAJOR LIMITATIONS:

--

-- 1.-  Harvard architecture only.

--      The core does not support non-Harvard, unified memory space (i.e. XCODE 

--      and XDATA on the same blocks). Signal sfr_vma is asserted the cycle 

--      before a fetch_1 state, when a code byte needs to be present at code_rd.

--      In other words, XCODE and XDATA accesses are always simultaneous.

--      Until the core supports wait states it only supports Harvard memory

--      or a dual-port XCODE/XDATA memory.

--

-- 2.-  No support yet for sequential multiplier, only combinational.

--      Setting SEQUENTIAL_MULTIPLIER to true will result in a synthesis

--      or simulation failure. 

--      The core will use a dedicated multiplier block if the architecture & 

--      synthesis options allow for it (e.d. DSP48).

-- 

-- 3.-  Wasted space in RAM block used for IRAM.

--      Setting USE_BRAM_FOR_XRAM to true will result in a synthesis

--      or simulation failure.

--      Architectures with BRAM blocks larger than 512 bytes (e.g. Xilinx 

--      Spartan) will have a lot of wasted space in the IRAM/uCode RAM block.

--------------------------------------------------------------------------------

-- FIXMES:

-- 

-- 1.-  States fetch_1 and decode_0 might be overlapped with some other states

--      for a noticeable gain in performance.

-- 2.-  Brief description of architecture is missing.

-- 3.-  Add optional 2nd DPTR register and implicit INC DPTR feature.

-- 4.-  Everything coming straight from a _reg should be named _reg too.

--------------------------------------------------------------------------------

-- REFERENCES:

-- [1] Tips for vendor-agnostic BRAM inference:

--     http://www.danstrother.com/2010/09/11/inferring-rams-in-fpgas/

--------------------------------------------------------------------------------

-- Copyright (C) 2012 Jose A. Ruiz

--                                                              

-- This source file may be used and distributed without         

-- restriction provided that this copyright statement is not    

-- removed from the file and that any derivative work contains  

-- the original copyright notice and the associated disclaimer. 

--                                                              

-- This source file is free software; you can redistribute it   

-- and/or modify it under the terms of the GNU Lesser General   

-- Public License as published by the Free Software Foundation; 

-- either version 2.1 of the License, or (at your option) any   

-- later version.                                               

--                                                              

-- This source is distributed in the hope that it will be       

-- useful, but WITHOUT ANY WARRANTY; without even the implied   

-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      

-- PURPOSE.  See the GNU Lesser General Public License for more 

-- details.                                                     

--                                                              

-- You should have received a copy of the GNU Lesser General    

-- Public License along with this source; if not, download it   

-- from http://www.opencores.org/lgpl.shtml

--------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.light52_pkg.all;

use work.light52_ucode_pkg.all;

entity light52_cpu is

    generic (

        USE_BRAM_FOR_XRAM : boolean := false;

        IMPLEMENT_BCD_INSTRUCTIONS : boolean := false;

        SEQUENTIAL_MULTIPLIER : boolean := false

    );

    port(

        clk             : in std_logic;

        reset           : in std_logic;

        code_addr       : out std_logic_vector(15 downto 0);

        code_rd         : in std_logic_vector(7 downto 0);

        irq_source      : in std_logic_vector(4 downto 0);

        xdata_addr      : out std_logic_vector(15 downto 0);

        xdata_rd        : in std_logic_vector(7 downto 0);

        xdata_wr        : out std_logic_vector(7 downto 0);

        xdata_vma       : out std_logic;

        xdata_we        : out std_logic;

        sfr_addr        : out std_logic_vector(7 downto 0);

        sfr_rd          : in std_logic_vector(7 downto 0);

        sfr_wr          : out std_logic_vector(7 downto 0);

        sfr_vma         : out std_logic;

        sfr_we          : out std_logic

    );

end entity light52_cpu;

architecture microcoded of light52_cpu is

---- Microcode table & instruction decoding ------------------------------------

signal ucode :              unsigned(15 downto 0);  -- uC word

signal ucode_1st_half :     unsigned(15 downto 0);  -- uC if 1st-half opcode

signal ucode_2nd_half :     unsigned(15 downto 0);  -- uC if 2nd-half opcode 

signal ucode_2nd_half_reg : unsigned(15 downto 0);  --

signal ucode_is_2nd_half :  std_logic;              -- opcode is 2-nd half

signal ucode_pattern :      unsigned(2 downto 0);   -- table row to replicate

signal ucode_index :        unsigned(6 downto 0);   -- index into uC table

signal do_fetch :           std_logic;              -- opcode is in code_rd

-- uC class (t_class), only valid in state decode_0

signal uc_class_decode_0 :  t_class;

-- ALU instruction class (t_alu_class), only valid in state decode_0

signal uc_alu_class_decode_0 : t_alu_class;

-- registered uc_alu_class_decode_0, used in state machine

signal uc_alu_class_reg :   t_alu_class;

-- ALU control, valid only in state decode_0

signal uc_alu_fn_decode_0 : t_alu_fns;

-- uc_alu_fn_decode_0 registered

signal alu_fn_reg :         t_alu_fns;

-- Controls ALU/bitfield mux in the datapath.

signal dpath_mux0_reg :     std_logic;

-- Flag mask for ALU instructions

signal uc_alu_flag_mask :   t_flag_mask;

-- Flag mask for all instructions; valid in state decode_0 only

signal flag_mask_decode_0 : t_flag_mask;

-- Flag mask register for ALL instructions

signal flag_mask_reg :      t_flag_mask;

-- Index of Rn register, valid for Rn addressing instructions only

signal rn_index :           unsigned(2 downto 0);

---- Datapath ------------------------------------------------------------------

-- Operand selection for ALU class instructions

signal alu_class_op_sel_reg: t_alu_op_sel;

signal alu_class_op_sel :   t_alu_op_sel;

-- ALU result valid for non-bit operations -- faster as it skips one mux

signal nobit_alu_result :   t_byte;

-- ALU result

signal alu_result :         t_byte;

signal alu_result_is_zero : std_logic;  -- ALU result is zero

signal acc_is_zero :        std_logic;  -- ACC is zero

signal alu_cy :             std_logic;  -- ALU CY output

signal alu_ov :             std_logic;  -- ALU OV output

signal alu_ac :             std_logic;  -- ALU AC (aux cy) output

signal bit_input :          std_logic;  -- Value of ALU bit operand

signal load_b_sfr :         std_logic;  -- B register load enable

signal mul_ready :          std_logic;  -- Multiplier is finished

signal div_ready :          std_logic;  -- Divider is finished

signal div_ov :             std_logic;  -- OV flag from divider

---- State machine -------------------------------------------------------------

-- Present state register and Next state

signal ps, ns :             t_cpu_state;

---- Interrupt handling --------------------------------------------------------

-- IRQ inputs ANDed to IE mask bits

signal irq_masked_inputs :  std_logic_vector(4 downto 0);

-- Level of highest-level active IRQ input. 0 is highest, 4 lowest, 7 is none.

signal irq_level_inputs :   unsigned(2 downto 0);

-- Level of IRQ being serviced. 7 if none. Set by IRQ, reset to 7 by RETI.

signal irq_level_current :  unsigned(2 downto 0);

-- Low 6 bits of IRQ service address.

signal irq_vector :         unsigned(5 downto 0);

signal irq_active :         std_logic;  -- IRQ pending service

signal load_ie :            std_logic;  -- IE register load enable

signal irq_restore_level :  std_logic;  -- Restore irq_level_current to 7 (RETI)

---- CPU programmer's model registers ------------------------------------------

signal PC_reg :             t_address;      -- PC

signal pc_incremented :     t_address;      -- PC + 1 | PC, controlled by...

signal increment_pc :       std_logic;      -- ...PC increment enable 

signal A_reg :              t_byte;         -- ACC    

signal B_reg :              t_byte;         -- B

signal PSW_reg :            unsigned(7 downto 1); -- PSW excluding P flag

signal PSW :                t_byte;         -- PSW, full (P is combinational)

signal SP_reg :             t_byte;         -- SP

signal SP_next :            t_byte;         -- Next value for SP

signal IE_reg :             t_byte;         -- IE

signal alu_p :              std_logic;      -- P flag (from ALU)

signal DPTR_reg :           t_address;      -- DPTR

signal next_pc :            t_address;      -- Next value for PC

signal jump_target :        t_address;      -- Addr to jump to

signal jump_is_ljmp :       std_logic;      -- When doing jump, long jump

signal instr_jump_is_ljmp : std_logic;      -- For jump opcodes, long jump

signal rel_jump_target :    t_address;      -- Address of a short jump

signal rel_jump_delta :     t_address;      -- Offset of short jump

-- 2K block index for AJMP/ACALL. Straight from the opcode.

signal block_reg :          unsigned(2 downto 0);

signal code_byte :          t_byte;     -- Byte from XCODE (transient)

signal ri_addr :            t_byte;     -- IRAM address of Ri register

signal rn_addr :            t_byte;     -- IRAM address of Rn register

-- The current ALU instruction CLASS uses Ri, not Rn

signal alu_use_ri_by_class : std_logic;

-- The current ALU instruction uses Ri and not Rn.

signal alu_use_ri :         std_logic;

-- The current instruction is not an ALU instruction and uses Ri, not Rn

signal non_alu_use_ri :     std_logic;

-- The current instruction uses Ri and not Rn

signal use_ri :             std_logic;

-- Registered use_ri, controls the Ri/Rn mux.

signal use_ri_reg :         std_logic;

signal rx_addr :            t_byte;     -- Output of Ri/Rx address selection mux

signal bit_addr :           t_byte;     -- Byte address of bit operand

-- Index of bit operand within its byte.

signal bit_index :          unsigned(2 downto 0);

-- bit_index_registered in state decode_0

signal bit_index_reg :      unsigned(2 downto 0);

signal addr0_reg :          t_byte;     -- Aux address register 0...

signal addr0_reg_input :    t_byte;     -- ...and its input mux

signal addr1_reg :          t_byte;     -- Aux addr reg 1

-- Asserted when the PSW flags are implicitly updated by any instruction

signal update_psw_flags :   std_logic;

signal load_psw :           std_logic;  -- PSW explicit (SFR) load enable

signal load_acc_sfr :       std_logic;  -- ACC explicit (SFR) load enable

signal load_addr0 :         std_logic;  -- Addr0 load enable

signal load_sp :            std_logic;  -- SP explicit (SFR) load enable

signal load_sp_implicit :   std_logic;  -- SP implicit load enable

signal update_sp :          std_logic;  -- SP combined load enable

---- SFR interface -------------------------------------------------------------

signal sfr_addr_internal :  unsigned(7 downto 0);   -- SFR address

signal sfr_vma_internal :   std_logic;              -- SFR access enable 

signal sfr_we_internal :    std_logic;              -- SFR write enable

signal sfr_wr_internal :    t_byte;                 -- SFR write data bus

signal sfr_rd_internal :    t_byte;                 -- SFR read data bus

signal sfr_rd_internal_reg :t_byte;                 -- Registered SFR read data

---- Conditional jumps ---------------------------------------------------------

signal jump_cond_sel_decode_0 : t_cc;       -- Jump condition code...

signal jump_cond_sel_reg :  t_cc;           -- ...registered to control mux

signal jump_condition :     std_logic;      -- Value of jump condition

signal cjne_condition :     std_logic;      -- Value of CJNE jump condition

---- BRAM used for IRAM and uCode table ----------------------------------------

-- The BRAM is a 512 byte table: 256 bytes for the decoding table and 256 bytes

-- for the 8052 IRAM. 

-- FIXME handle Xilinx and arbitrary size FPGA BRAMs.

constant BRAM_ADDR_LEN : integer := log2(BRAM_SIZE);

subtype t_bram_addr is unsigned(BRAM_ADDR_LEN-1 downto 0);

signal bram_addr_p0 :       t_bram_addr;

signal bram_addr_p1 :       t_bram_addr;

signal bram_data_p0 :       t_byte;

signal bram_data_p1 :       t_byte;

signal bram_we :            std_logic;

signal bram_wr_data_p0 :    t_byte;

-- Part of the BRAM inference template -- see [1]

-- The BRAM is initializzed with the decoding table.

shared variable bram :      t_ucode_bram :=

                ucode_to_bram(build_decoding_table(IMPLEMENT_BCD_INSTRUCTIONS));

-- IRAM/SFR address; lowest 8 bits of actual BRAM address.

signal iram_sfr_addr :      t_byte;

-- IRAM/SFR read data

signal iram_sfr_rd :        t_byte;

-- '1' when using direct addressing mode, '0' otherwise.

signal direct_addressing :  std_logic;

-- '1' when using direct addressing to address range 80h..ffh, '0' otherwise.

signal sfr_addressing :     std_logic;

signal sfr_addressing_reg : std_logic;

-- Kind of addressing the current instruction is using

signal direct_addressing_alu_reg : std_logic;

signal alu_using_direct_addressing : std_logic;

signal alu_using_indirect_addressing : std_logic;

-- XRAM/MOVC interface and DPTR control logic ----------------------------------

signal load_dph :           std_logic;  -- DPTR(h) load enable

signal load_dpl :           std_logic;  -- DPTR(l) load enable

signal inc_dptr :           std_logic;  -- DPTR increment enable

signal acc_ext16 :          t_address;  -- Accumulator zero-extended to 16 bits

signal movc_base :          t_address;  -- Base for MOVC address

signal movc_addr :          t_address;  -- MOVC address

signal dptr_plus_a_reg :    t_address;  -- Registered DPTR+ACC adder

begin

--## 1.- State machine #########################################################

cpu_state_machine_reg:

process(clk)

begin

   if clk'event and clk='1' then

        if reset='1' then

            ps <= reset_0;

        else

            ps <= ns;

        end if;

    end if;

end process cpu_state_machine_reg;

cpu_state_machine_transitions:

process(ps, uc_class_decode_0, uc_alu_class_decode_0,

        uc_alu_class_reg, jump_condition, alu_fn_reg,

        mul_ready,div_ready,

        irq_active)

begin

    case ps is

    when reset_0 =>

        ns <= fetch_1;

    when fetch_0 =>

        ns <= fetch_1;

    when fetch_1 =>

        -- Here's where we sample the pending interrupt flags... 

        if irq_active='1' then

            -- ...and trigger interrupt response if necessary.

            ns <= irq_1;

        else

            ns <= decode_0;

        end if;

    when decode_0 =>

        if uc_class_decode_0(5 downto 4) = "00" then

            case uc_alu_class_decode_0 is

                when AC_RI_to_A => ns <= alu_rx_to_ab;

                when AC_A_RI_to_A => ns <= alu_rx_to_ab;

                when AC_RI_to_RI => ns <= alu_rx_to_ab;

                when AC_RI_to_D => ns <= alu_rx_to_ab;

                when AC_D_to_A => ns <= alu_code_to_ab;

                when AC_D1_to_D => ns <= alu_code_to_ab;

                when AC_D_to_RI => ns <= alu_code_to_ab;

                when AC_D_to_D => ns <= alu_code_to_ab;

                when AC_A_RN_to_A => ns <= alu_rx_to_ab;

                when AC_RN_to_RN => ns <= alu_rx_to_ab;

                when AC_RN_to_A => ns <= alu_rx_to_ab;

                when AC_D_to_RN => ns <= alu_code_to_ab;

                when AC_RN_to_D => ns <= alu_rx_to_ab;

                when AC_I_to_D => ns <= alu_code_to_ab;

                when AC_I_D_to_D => ns <= alu_code_to_ab;

                when AC_I_to_RI => ns <= alu_code_to_t_rx_to_ab;

                when AC_I_to_RN => ns <= alu_code_to_t_rx_to_ab;

                when AC_I_to_A => ns <= alu_code_to_t;

                when AC_A_to_RI => ns <= alu_rx_to_ab;

                when AC_A_to_D => ns <= alu_code_to_ab;

                when AC_A_D_to_A => ns <= alu_code_to_ab;

                when AC_A_D_to_D => ns <= alu_code_to_ab;

                when AC_A_to_RN => ns <= alu_rx_to_ab;

                when AC_A_I_to_A => ns <= alu_code_to_t;

                when AC_A_to_A => ns <= alu_res_to_a;

                when AC_DIV => ns <= alu_div_0;

                when AC_MUL => ns <= alu_mul_0;

                when AC_DA => ns <= alu_daa_0;

                when others => ns <= bug_bad_opcode_class;

            end case;

        else

            case uc_class_decode_0 is

            when F_JRB =>

                ns <= jrb_bit_0;

            when F_LJMP =>

                ns <= fetch_addr_1;

            when F_AJMP =>

                ns <= fetch_addr_0_ajmp;

            when F_LCALL =>

                ns <= lcall_0;

            when F_ACALL =>

                ns <= acall_0;

            when F_JR =>

                ns <= load_rel;

            when F_CJNE_A_IMM =>

                ns <= cjne_a_imm_0;

            when F_CJNE_A_DIR =>

                ns <= cjne_a_dir_0;

            when F_CJNE_RI_IMM =>

                ns <= cjne_ri_imm_0;

            when F_CJNE_RN_IMM =>

                ns <= cjne_rn_imm_0;

            when F_DJNZ_DIR =>

                ns <= djnz_dir_0;

            when F_DJNZ_RN =>

                ns <= djnz_rn_0;

            when F_OPC =>

                ns <= bit_res_to_c;

            when F_BIT =>

                ns <= bit_op_0;

            when F_SPECIAL =>

                ns <= special_0;

            when F_PUSH =>

                ns <= push_0;

            when F_POP =>

                ns <= pop_0;

            when F_MOV_DPTR =>

                ns <= mov_dptr_0;

            when F_MOVX_DPTR_A =>

                ns <= movx_dptr_a_0;

            when F_MOVX_A_DPTR =>

                ns <= movx_a_dptr_0;

            when F_MOVX_A_RI =>

                ns <= movx_a_ri_0;

            when F_MOVX_RI_A =>

                ns <= movx_ri_a_0;

            when F_MOVC_PC =>

                ns <= movc_pc_0;

            when F_MOVC_DPTR =>

                ns <= movc_dptr_0;

            when F_XCH_DIR =>

                ns <= xch_dir_0;

            when F_XCH_RI =>

                ns <= xch_rx_0;

            when F_XCH_RN =>

                ns <= xch_rn_0;

            when F_XCHD =>

                ns <= alu_xchd_0;

            when F_JMP_ADPTR =>

                ns <= jmp_adptr_0;

            when F_RET =>

                ns <= ret_0;

            when F_NOP =>

                ns <= fetch_1;

            when others =>

                ns <= bug_bad_opcode_class;

            end case;

        end if;

    -- Interrupt processing ------------------------------------------

    when irq_1 =>

        ns <= irq_2;

    when irq_2 =>

        ns <= irq_3;

    when irq_3 =>

        ns <= irq_4;

    when irq_4 =>

        ns <= fetch_0;

    -- Call/Ret instructions -----------------------------------------

    when acall_0 =>

        ns <= acall_1;

    when acall_1 =>

        ns <= acall_2;

    when acall_2 =>

        ns <= long_jump;

    when lcall_0 =>

        ns <= lcall_1;

    when lcall_1 =>

        ns <= lcall_2;

    when lcall_2 =>

        ns <= lcall_3;

    when lcall_3 =>

        ns <= lcall_4;

    when lcall_4 =>

        ns <= fetch_0;

    when ret_0 =>

        ns <= ret_1;

    when ret_1 =>

        ns <= ret_2;

    when ret_2 =>

        ns <= ret_3;

    when ret_3 =>

        ns <= fetch_0;

    -- Special instructions ------------------------------------------

    when special_0 =>

        ns <= fetch_1;

    when push_0 =>

        ns <= push_1;

    when push_1 =>

        ns <= push_2;

    when push_2 =>

        ns <= fetch_1;

    when pop_0 =>

        ns <= pop_1;

    when pop_1 =>

        ns <= pop_2;

    when pop_2 =>

        ns <= fetch_1;

    when mov_dptr_0 =>

        ns <= mov_dptr_1;

    when mov_dptr_1 =>

        ns <= mov_dptr_2;

    when mov_dptr_2 =>

        ns <= fetch_1;

    -- MOVC instructions ---------------------------------------------

    when movc_pc_0 =>

        ns <= movc_1;

    when movc_dptr_0 =>

        ns <= movc_1;

    when movc_1 =>

        ns <= fetch_1;

    -- MOVX instructions ---------------------------------------------

    when movx_a_dptr_0 =>

        ns <= fetch_1;

    when movx_dptr_a_0 =>

        ns <= fetch_1;

    when movx_a_ri_0 =>

        ns <= movx_a_ri_1;

    when movx_a_ri_1 =>

        ns <= movx_a_ri_2;

    when movx_a_ri_2 =>

        ns <= movx_a_ri_3;

    when movx_a_ri_3 =>

        ns <= fetch_1;

    when movx_ri_a_0 =>

        ns <= movx_ri_a_1;

    when movx_ri_a_1 =>

        ns <= movx_ri_a_2;

    when movx_ri_a_2 =>

        ns <= fetch_1;

    -- XCH instructions ----------------------------------------------

    when xch_dir_0 =>

        ns <= xch_1;

    when xch_rn_0 =>

        ns <= xch_1;

    when xch_rx_0 =>

        ns <= xch_rx_1;

    when xch_rx_1 =>

        ns <= xch_1;

    when xch_1 =>

        ns <= xch_2;

    when xch_2 =>

        ns <= xch_3;

    when xch_3 =>

        ns <= fetch_1;

    -- BIT instructions ----------------------------------------------

    when bit_res_to_c =>    -- SETB C, CPL C and CLR C only

        ns <= fetch_1;

    when bit_op_0 =>

        ns <= bit_op_1;

    when bit_op_1 =>

        if uc_alu_class_reg(0)='0' then

            ns <= bit_op_2;

        else

            ns <= bit_res_to_c;

        end if;

    when bit_op_2 =>

        ns <= fetch_1;

    -- BIT-testing relative jumps ------------------------------------

    when jrb_bit_0 =>

        ns <= jrb_bit_1;

    when jrb_bit_1 =>

        if alu_fn_reg(1 downto 0)="11" then

            -- This is JBC; state jrb_bit_2 is where the bit is clear.

            ns <= jrb_bit_2;

        else

            ns <= jrb_bit_3;

        end if;

    when jrb_bit_2 =>

        ns <= jrb_bit_3;

    when jrb_bit_3 =>

        if jump_condition='1' then

            ns <= jrb_bit_4;

        else

            ns <= fetch_0;

        end if;

    when jrb_bit_4 =>

        ns <= fetch_0;

    -- MUL/DIV instructions ------------------------------------------

    when alu_div_0 =>

        if div_ready='1' then

            ns <= fetch_1;

        else

            ns <= ps;

        end if;

    when alu_mul_0 =>

        if mul_ready='1' then

            ns <= fetch_1;

        else

            ns <= ps;

        end if;

    -- BCD instructions ----------------------------------------------

    when alu_daa_0 =>

        ns <= alu_daa_1;

    when alu_daa_1 =>

        ns <= fetch_1;

    when alu_xchd_0 =>

        ns <= alu_xchd_1;

    when alu_xchd_1 =>

        ns <= alu_xchd_2;

    when alu_xchd_2 =>

        ns <= alu_xchd_3;

    when alu_xchd_3 =>

        ns <= alu_xchd_4;

    when alu_xchd_4 =>

        ns <= alu_xchd_5;

    when alu_xchd_5 =>

        ns <= fetch_1;

    -- ALU instructions (other than MUL/DIV) -------------------------

    when alu_rx_to_ab =>

        case uc_alu_class_reg is

            when AC_RI_to_A | AC_A_RI_to_A | AC_RI_to_D | AC_RI_to_RI =>

                ns <= alu_ram_to_ar;