1 |
2 |
ja_rd |
|
2 |
29 |
ja_rd |
The test programs have been assembled with TASM (Telemark Cross Assembler),
|
3 |
|
|
a free assembler available for DOS and Linux.
|
4 |
15 |
ja_rd |
|
5 |
47 |
ja_rd |
A few Modelsim simulation scripts are included to assist in running the test
|
6 |
|
|
benches with that simulator. They are in the synthesis directory.
|
7 |
|
|
The scripts expect that Modelsim's current directory is the synthesis directory.
|
8 |
|
|
(you can change the working directory with 'File'->'change directory').
|
9 |
|
|
If you don't use Modelsim standalone but from within an IDE, there's a couple
|
10 |
|
|
of independent scripts to help you organize the test signals.
|
11 |
2 |
ja_rd |
|
12 |
47 |
ja_rd |
A CP/M port for a Cyclone 2 starter board will eventually be included as a demo.
|
13 |
|
|
It is still incomplete (a lot of necessary files haven't yet been uploaded to
|
14 |
|
|
SVN) and unfinished.
|
15 |
|
|
|
16 |
|
|
|
17 |
2 |
ja_rd |
FILE LIST
|
18 |
|
|
==========
|
19 |
|
|
|
20 |
|
|
vhdl\light8080.vhdl Core source (single file)
|
21 |
|
|
|
22 |
|
|
vhdl\test\light8080_tb0.vhdl Test bench 0 (Kelly test)
|
23 |
|
|
vhdl\test\light8080_tb1.vhdl Test bench 1 (Interrupts)
|
24 |
|
|
|
25 |
56 |
ja_rd |
vhdl\demo\cs2b_4kbasic_cpu.vhdl altair 4K Basic demo on DE-1 board
|
26 |
|
|
vhdl\demo\cs2b_4kbasic_rom.vhdl ROM/RAM for 4K Basic demo
|
27 |
2 |
ja_rd |
vhdl\demo\rs232_tx.vhdl Serial tx code for demo
|
28 |
|
|
vhdl\demo\rs232_rx.vhdl Serial rx code for demo
|
29 |
56 |
ja_rd |
vhdl\demo\c2sb_4kbasic.csv Pin assignment file for Quartus II
|
30 |
2 |
ja_rd |
|
31 |
|
|
util\uasm.pl Microcode assembler
|
32 |
|
|
util\microrom.bat Sample DOS bat file for assembler
|
33 |
|
|
|
34 |
|
|
ucode\light8080.m80 Microcode source file
|
35 |
|
|
|
36 |
47 |
ja_rd |
synthesis\sim_tb0.do Modelsim script for test bench 0
|
37 |
|
|
synthesis\sim_tb1.do Modelsim script for test bench 1
|
38 |
|
|
synthesis\tb0_modelsim_wave.do Script with wave format and colors, tb0
|
39 |
|
|
synthesis\tb1_modelsim_wave.do Script with wave format and colors, tb1
|
40 |
2 |
ja_rd |
|
41 |
15 |
ja_rd |
doc\designNotes.tex Core documentation in LaTeX format
|
42 |
2 |
ja_rd |
doc\designNotes.pdf Core documentation in PDF format
|
43 |
|
|
|
44 |
|
|
asm\tb0.asm Test bench 0 program assembler source
|
45 |
|
|
asm\tb1.asm Test bench 1 program assembler source
|
46 |
29 |
ja_rd |
asm\hexconv.pl Intel HEX to VHDL converter
|
47 |
|
|
asm\tasmtb.bat BATCH script to build the test benches
|
48 |
47 |
ja_rd |
asm\readme.txt How to assemble the sources
|
49 |
65 |
motilito |
|
50 |
|
|
verilog\rtl\ contains the Verilog files of the light8080 CPU and SOC
|
51 |
|
|
verilog\bench\ Verilog light8080 SOC testbench
|
52 |
|
|
verilog\sim\icarus files used for Verilog simulation using Icaru Verilog
|
53 |
|
|
verilog\syn\altera_c2 Altera Quartus project file ucing Cyclone II FPGA
|
54 |
|
|
verilog\syn\xilinx_s3 Xilinx ISE project file ucing Spartan 3 FPGA
|
55 |
|
|
|
56 |
|
|
c\ Hello World Small-C light8080 SOC sample
|
57 |
|
|
|
58 |
|
|
tools\c80\ C80 compiler and AS80 assembler tools used to compile
|
59 |
|
|
the C example program. The c80.exe executable was compiled
|
60 |
|
|
using tcc (Tiny C Compiler).
|
61 |
|
|
|
62 |
|
|
tools\ihex2vlog\ Intel HEX to Verilog tool used to generate the Verilog
|
63 |
|
|
program & RAM memory file used by the verilog SOC.
|
64 |
|
|
The ihex2vlog.exe executable was compiled using tcc
|
65 |
|
|
(Tiny C Compiler).
|