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ja_rd |
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8080EXER is an instruction exerciser that runs all the 8080 opcodes with a large
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number of parameter combinations. The program computes a CRC value for the CPU
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state after testing each block of CPU opcodes. that CRC value is then compared
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against the CRC value produced by an original, silicon i8080.
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If the CRC values match, it can safely be assumed that the core and the original
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8080 behavior is identical.
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The program was taken from this web:
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http://www.idb.me.uk/sunhillow/8080.html
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Here you can find a more detailed explaination.
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I have made the following modifications to the original 8080EXEC:
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- Added code that emulates a few CP/M BDOS functions needed to output text.
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- Adapted the code to work on the C2SB demo board within the l80soc module.
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- Added the original Intel CRC values for comparison.
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The source code is in a format compatible to CP/M M80 assembler and incompatible
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to TASM, AS80 and all other Windows and Linux 8080-compatible assemblers that
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I know about. Therefore it can only be compiled from within CP/M. You can use
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SIMH for that. I will not include instructions but you can find plenty in SIMH
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web site.
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File 'MAC.SUB' is a CP/M 'batch' file that you can use to assemble the source
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with:
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DO MAC 8080EXER
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I hope this saves you the trouble to find and read M80 documentation...
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At any rate, i have included the compiled HEX file so all you have to do is
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run the build.bat script. Or just use the pre-built obj_code_pkg.vhdl included.
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Synthesis instructions:
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=======================
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Assuming you are using Quartus-2 and targetting a Terasic DE-1 dev board (for
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which the demo is tailored), you need to follow these steps:
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1.- Create a new project for the DE-1 board, (device EP2C20F484C7, etc.).
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2.- Add the following vhdl files to the project:
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-# /vhdl/light8080.vhdl
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-# /vhdl/demos/c2sb/c2sb_soc.vhdl
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-# /vhdl/soc/*.vhdl
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3.- Select file c2sb_soc.vhdl as 'top' entity.
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4.- Configure dual-purpose pin nCEO as regular i/o (Device settings->Device and
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pin options->Dual-purpose pins)
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5.- Import pin location constraints from file /vhdl/demos/c2sb/c2sb_pins.csv.
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That's all. Synthesize and have a terminal (19200/8/N/1) connected to the UART
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connector. Reset pin is button 1 (rightmost).
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Execution instructions:
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=======================
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You need to run this with a terminal connected to the SoC UART (19200/8/N/1).
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The tests will take quite a long time to run at 50MHz (about 11 minutes).
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All you have to do is watch the messages.
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In the present version of the core, all tests should succeed except for the
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special opcode block (): one of those instructions is
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incompatible to the original intel silicon.
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Note that ALL instructions have been tested for compatibility to the
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DOCUMENTATION. We're talking about replicating undocumented behavior here.
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