| 1 |
74 |
ja_rd |
0001 0000 ;*******************************************************************************
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| 2 |
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0002 0000 ; soc_tb.asm -- light8080 SoC basic test bench.
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| 3 |
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0003 0000 ;*******************************************************************************
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| 4 |
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0004 0000 ; Should be used with SoC core test bench entity vhdl\test\l80soc_tb.vhdl.
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| 5 |
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0005 0000 ; Assembler format compatible with TASM for DOS and Linux.
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| 6 |
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0006 0000 ;*******************************************************************************
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| 7 |
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0007 0000 ; This program will send a few bytes over a looped-back UART, using the UART
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| 8 |
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0008 0000 ; interrupt capability and verifying that received and transmitted data match.
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| 9 |
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0009 0000 ; It will then try one of the external interrupts, connected to one of the
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| 10 |
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0010 0000 ; general purpose outputs.
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| 11 |
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0011 0000 ; This minimal test bench relies on an already tested CPU core to do a
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| 12 |
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0012 0000 ; This program does not deserve to even be called a 'test' but if if works it
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| 13 |
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0013 0000 ; will at least rule out many obvious bug in the SoC core.
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| 14 |
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0014 0000 ;*******************************************************************************
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| 15 |
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0015 0000
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| 16 |
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0016 0000 ; DS pseudo-directive; reserve space in bytes, without initializing it
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| 17 |
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0017 0000 #define ds(n) \.org $+n
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| 18 |
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0018 0000
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| 19 |
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0019 0000 MASK_RX_IRQ: .equ 20h
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| 20 |
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0020 0000 MASK_TX_IRQ: .equ 10h
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| 21 |
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0021 0000 MASK_RX_RDY: .equ 02h
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| 22 |
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0022 0000 MASK_TX_RDY: .equ 01h
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| 23 |
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0023 0000
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| 24 |
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0024 0000 UART_DATA: .equ 80h
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| 25 |
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0025 0000 UART_STATUS: .equ 81h
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| 26 |
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0026 0000 UART_BAUDL: .equ 82h
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| 27 |
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0027 0000 UART_BAUDH: .equ 83h
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| 28 |
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0028 0000 IRQ_ENABLE: .equ 88h
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| 29 |
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0029 0000
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| 30 |
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0030 0000 P1IN: .equ 84h
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| 31 |
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0031 0000 P2OUT: .equ 86h
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| 32 |
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0032 0000
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| 33 |
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0033 0000
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| 34 |
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0034 0000 ;*******************************************************************************
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| 35 |
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0035 0000
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| 36 |
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0036 0000 .org 0H ; Reset entry point
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| 37 |
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0037 0000 C3 60 00 jmp start ; Skip the rst address area
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| 38 |
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0038 0003
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| 39 |
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0039 0003 ;***** Interrupt vectors in area 0008h-0038h *****************
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| 40 |
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0040 0003
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| 41 |
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0041 0008 .org 0h+(1*8) ; interrupt vector 1 (IRQ0)
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| 42 |
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0042 0008 C3 12 01 jmp isr0
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| 43 |
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0043 0010 .org 0h+(2*8) ; interrupt vector 2
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| 44 |
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0044 0010 FB ei
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| 45 |
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0045 0011 C9 ret
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| 46 |
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0046 0018 .org 0h+(3*8) ; interrupt vector 3 (IRQ1)
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| 47 |
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0047 0018 C3 1E 01 jmp isr1
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| 48 |
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0048 0020 .org 0h+(4*8) ; interrupt vector 4
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| 49 |
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0049 0020 FB ei
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| 50 |
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0050 0021 C9 ret
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| 51 |
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0051 0028 .org 0h+(5*8) ; interrupt vector 5 (IRQ2)
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| 52 |
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0052 0028 FB ei
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| 53 |
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0053 0029 C9 ret
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| 54 |
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0054 0030 .org 0h+(6*8) ; interrupt vector 6
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| 55 |
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0055 0030 FB ei
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| 56 |
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0056 0031 C9 ret
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| 57 |
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0057 0032
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| 58 |
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0058 0038 .org 0h+(7*8) ; interrupt vector 7 (IRQ3, UART)
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| 59 |
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0059 0038 C3 2A 01 int38h: jmp irq_uart ; UART interrupt
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| 60 |
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0060 003B
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| 61 |
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0061 003B ;***** program entry point *******************************************
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| 62 |
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0062 003B
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| 63 |
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0063 0060 start: .org 60H
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| 64 |
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0064 0060 31 DA 01 lxi sp,stack
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| 65 |
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0065 0063
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| 66 |
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0066 0063 ; Initialize UART RX and TX buffers
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| 67 |
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0067 0063 21 74 01 lxi h,void_buffer
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| 68 |
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0068 0066 22 75 01 shld ptr_tx
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| 69 |
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0069 0069 21 7A 01 lxi h,rx_buffer
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| 70 |
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0070 006C 22 77 01 shld ptr_rx
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| 71 |
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0071 006F 3E 00 mvi a,00h
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| 72 |
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0072 0071 32 79 01 sta len_rx
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| 73 |
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0073 0074
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| 74 |
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0074 0074 ; Clear all P2 output lines (used to simulate external interrupts)
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| 75 |
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0075 0074 3E 00 mvi a,00h
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| 76 |
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0076 0076 D3 86 out P2OUT
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| 77 |
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0077 0078
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| 78 |
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0078 0078 ; Set up interrupts
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| 79 |
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0079 0078 3E 0B mvi a,0bh ; Enable UART irq plus IRQ0 and IRQ1...
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| 80 |
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0080 007A D3 88 out IRQ_ENABLE
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| 81 |
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0081 007C FB ei ; ...and enable interrupts in the CPU
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| 82 |
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0082 007D
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| 83 |
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0083 007D ; print hello message to console
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| 84 |
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0084 007D 21 02 01 lxi h,msg_hello
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| 85 |
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0085 0080 CD 66 01 call print_string
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| 86 |
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0086 0083 ; Ok, now the message is being transferred through the looped back
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| 87 |
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0087 0083 ; UART, using the UART interrupts, which have the lowest priority.
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| 88 |
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0088 0083 ; We have plenty of time to make a few tests on the external interrupt
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| 89 |
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0089 0083 ; lines before the message transmission is finished.
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| 90 |
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0090 0083
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| 91 |
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0091 0083 ; The irq routines will leave some data at 'irq_data, each routine a
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| 92 |
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0092 0083 ; different value and all non-zero. This is how we know what irq
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| 93 |
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0093 0083 ; routines have executed and in which order.
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| 94 |
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0094 0083
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| 95 |
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0095 0083 ; Test IRQ0 alone
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| 96 |
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0096 0083 3E 01 mvi a,01h ; Initialize irq data
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| 97 |
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0097 0085 32 73 01 sta irq_data
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| 98 |
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0098 0088 3E 01 mvi a,01h ; Trigger IRQ0
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| 99 |
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0099 008A D3 86 out P2OUT
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| 100 |
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0100 008C test_irq0:
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| 101 |
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0101 008C 3A 73 01 lda irq_data
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| 102 |
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0102 008F FE 04 cpi 004h ; Do we see the IRQ test data?
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| 103 |
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0103 0091 CA 9C 00 jz done_irq0 ; If we do, proceed to next test
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| 104 |
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0104 0094 FE 01 cpi 001h ; Do we see some other IRQ test data instead?
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| 105 |
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0105 0096 C2 FB 00 jnz test_fail ; If we do, there's trouble with the irqs
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| 106 |
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0106 0099 C3 8C 00 jmp test_irq0 ; Keep waiting for some IRQ test data
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| 107 |
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0107 009C done_irq0:
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| 108 |
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0108 009C 3E 00 mvi a,00h ; Deassert all interrupt lines
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| 109 |
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0109 009E D3 86 out P2OUT
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| 110 |
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0110 00A0
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| 111 |
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0111 00A0 ; Test IRQ1 alone
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| 112 |
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0112 00A0 3E 01 mvi a,01h ; Initialize irq data
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| 113 |
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0113 00A2 32 73 01 sta irq_data
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| 114 |
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0114 00A5 3E 02 mvi a,02h ; Trigger IRQ1
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| 115 |
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0115 00A7 D3 86 out P2OUT
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| 116 |
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0116 00A9 test_irq1:
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| 117 |
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0117 00A9 3A 73 01 lda irq_data
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| 118 |
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0118 00AC FE 02 cpi 002h ; Do we see the IRQ test data?
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| 119 |
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0119 00AE CA B9 00 jz done_irq1 ; If we do, proceed to next test
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| 120 |
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0120 00B1 FE 01 cpi 001h ; Do we see some other IRQ test data instead?
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| 121 |
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0121 00B3 C2 FB 00 jnz test_fail ; If we do, there's trouble with the irqs
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| 122 |
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0122 00B6 C3 A9 00 jmp test_irq1 ; Keep waiting for some IRQ test data
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| 123 |
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0123 00B9 done_irq1:
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| 124 |
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0124 00B9 AF xra a ; Deassert all interrupt lines
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| 125 |
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0125 00BA D3 86 out P2OUT
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| 126 |
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0126 00BC
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| 127 |
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0127 00BC ; Test IRQ0 and IRQ1 simultaneously
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| 128 |
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0128 00BC 3E 01 mvi a,01h ; Initialize irq data
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| 129 |
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0129 00BE 32 73 01 sta irq_data
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| 130 |
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0130 00C1 3E 03 mvi a,03h ; Trigger IRQ0 and IRQ1
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| 131 |
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0131 00C3 D3 86 out P2OUT
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| 132 |
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0132 00C5
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| 133 |
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0133 00C5 ; Sequence IRQ0->IRQ1 will result in (1 << 2) + 1 = 5
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| 134 |
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0134 00C5 ; Sequence IRQ1->IRQ0 would result in (1 + 1) << 2 = 6
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| 135 |
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0135 00C5 ; We expect IRQ0->IRQ1, since IRQ0 has higher priority
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| 136 |
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0136 00C5 test_irq01:
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| 137 |
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0137 00C5 3A 73 01 lda irq_data
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| 138 |
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0138 00C8 FE 05 cpi 005h ; Do we see the IRQ0->IRQ1 test data?
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| 139 |
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0139 00CA CA D5 00 jz done_irq01 ; If we do, proceed to next test
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| 140 |
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0140 00CD FE 01 cpi 001h ; Do we see some other IRQ test data instead?
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| 141 |
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0141 00CF C2 FB 00 jnz test_fail ; If we do, there's trouble with the irqs
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| 142 |
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0142 00D2 C3 C5 00 jmp test_irq01 ; Keep waiting for some IRQ test data
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| 143 |
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0143 00D5 done_irq01:
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| 144 |
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0144 00D5 AF xra a ; Deassert all interrupt lines
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| 145 |
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0145 00D6 D3 86 out P2OUT
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| 146 |
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0146 00D8
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| 147 |
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0147 00D8 ; Ok, the external interrupts have been tested (well, 'tested'). Now
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| 148 |
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0148 00D8 ; wait for the UART looped-back transmission to end and compare
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| 149 |
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0149 00D8 ; the data.
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| 150 |
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0150 00D8
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| 151 |
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0151 00D8 ; Wait until the number of UART received characters equals the length
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| 152 |
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0152 00D8 ; of the test message.
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| 153 |
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0153 00D8 wait_for_message:
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| 154 |
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0154 00D8 3A 79 01 lda len_rx
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| 155 |
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0155 00DB FE 0F cpi msg_len
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| 156 |
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0156 00DD C2 D8 00 jnz wait_for_message
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| 157 |
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0157 00E0
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| 158 |
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0158 00E0 ; Compare the TX and RX strings
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| 159 |
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0159 00E0 21 7A 01 lxi h,rx_buffer
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| 160 |
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0160 00E3 11 02 01 lxi d,msg_hello
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| 161 |
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0161 00E6 compare_loop:
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| 162 |
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0162 00E6 1A ldax d
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| 163 |
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0163 00E7 FE 24 cpi '$'
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| 164 |
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0164 00E9 CA F5 00 jz test_ok
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| 165 |
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0165 00EC BE cmp m
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| 166 |
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0166 00ED C2 FB 00 jnz test_fail
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| 167 |
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0167 00F0 23 inx h
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| 168 |
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0168 00F1 13 inx d
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| 169 |
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0169 00F2 C3 E6 00 jmp compare_loop
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| 170 |
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0170 00F5
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| 171 |
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0171 00F5
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| 172 |
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0172 00F5
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| 173 |
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0173 00F5
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| 174 |
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0174 00F5
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| 175 |
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0175 00F5 test_ok:
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| 176 |
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0176 00F5 3E 80 mvi a,80h ; Raise 'success' output flag...
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| 177 |
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0177 00F7 D3 86 out P2OUT
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| 178 |
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0178 00F9 F3 done: di ; ...and block here.
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| 179 |
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0179 00FA 76 hlt
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| 180 |
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0180 00FB
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| 181 |
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0181 00FB test_fail:
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| 182 |
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0182 00FB 3E 40 mvi a,40h ; Raise 'failure' flag...
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| 183 |
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0183 00FD D3 86 out P2OUT
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| 184 |
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0184 00FF C3 F9 00 jmp done ; ...and block.
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| 185 |
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0185 0102
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| 186 |
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0186 0102
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| 187 |
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0187 0102
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| 188 |
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0188 0102 0A 0D 0A 48 msg_hello: .text "\n\r\nHello World!$"
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| 189 |
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0188 0106 65 6C 6C 6F
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| 190 |
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0188 010A 20 57 6F 72
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| 191 |
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0188 010E 6C 64 21 24
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| 192 |
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0189 0112 msg_end: .equ $
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| 193 |
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0190 0112 msg_len: .equ msg_end - msg_hello - 1
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| 194 |
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0191 0112
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| 195 |
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0192 0112 F5 isr0: push psw
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| 196 |
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0193 0113 3A 73 01 lda irq_data
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| 197 |
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0194 0116 07 rlc
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| 198 |
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0195 0117 07 rlc
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| 199 |
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0196 0118 32 73 01 sta irq_data
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| 200 |
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0197 011B F1 pop psw
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| 201 |
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0198 011C FB ei
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| 202 |
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0199 011D C9 ret
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| 203 |
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0200 011E
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| 204 |
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0201 011E F5 isr1: push psw
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| 205 |
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0202 011F 3A 73 01 lda irq_data
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| 206 |
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0203 0122 C6 01 adi 1
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| 207 |
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0204 0124 32 73 01 sta irq_data
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| 208 |
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0205 0127 F1 pop psw
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| 209 |
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0206 0128 FB ei
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| 210 |
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0207 0129 C9 ret
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| 211 |
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0208 012A
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| 212 |
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0209 012A ;irq_uart: UART interrupt processing
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| 213 |
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0210 012A irq_uart:
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| 214 |
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0211 012A E5 push h
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| 215 |
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0212 012B F5 push psw
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| 216 |
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0213 012C
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| 217 |
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0214 012C ; Deal with RX interrupt (if any) first and then the TX interrupt.
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| 218 |
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0215 012C DB 81 in UART_STATUS ; Is there new data in the RX register?
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| 219 |
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0216 012E E6 20 ani MASK_RX_IRQ
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| 220 |
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0217 0130 CA 48 01 jz irq_uart_rx_done ; If there isn't, process TX interrupt.
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| 221 |
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0218 0133
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| 222 |
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0219 0133 ; Process UART RX interrupt
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| 223 |
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0220 0133 irq_uart_rx:
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| 224 |
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0221 0133 3E 20 mvi a,MASK_RX_IRQ ; Clear IRQ flag.
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| 225 |
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0222 0135 D3 81 out UART_STATUS
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| 226 |
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0223 0137 DB 80 in UART_DATA ; Get RX byte...
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| 227 |
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0224 0139 2A 77 01 lhld ptr_rx ; ...and store it in the rx buffer.
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| 228 |
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0225 013C 77 mov m,a
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| 229 |
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0226 013D 23 inx h
|
| 230 |
|
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0227 013E 22 77 01 shld ptr_rx ; Update the rx buffer pointer.
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| 231 |
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0228 0141 3A 79 01 lda len_rx ; Update RX buffer length
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| 232 |
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0229 0144 3C inr a
|
| 233 |
|
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0230 0145 32 79 01 sta len_rx
|
| 234 |
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0231 0148
|
| 235 |
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0232 0148 ; Note there's no check for RX buffer overrun! we shouldn't need it
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| 236 |
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0233 0148 ; here, a runaway condition would be readily apparent in the
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| 237 |
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0234 0148 ; simulation, anyway.
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| 238 |
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0235 0148
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| 239 |
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0236 0148 irq_uart_rx_done:
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| 240 |
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0237 0148 ; Ok, RX is done. Now deal with TX irq, if any
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| 241 |
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0238 0148 DB 81 in UART_STATUS ; Is the TX buffer re new data in the RX register?
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| 242 |
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0239 014A E6 10 ani MASK_TX_IRQ
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| 243 |
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0240 014C CA 62 01 jz irq_uart_end ; If there isn't, we're done.
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| 244 |
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0241 014F
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| 245 |
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0242 014F ; process UART TX interrupt
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| 246 |
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0243 014F irq_uart_tx:
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| 247 |
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0244 014F 3E 10 mvi a,MASK_TX_IRQ ; Clear IRQ flag.
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| 248 |
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0245 0151 D3 81 out UART_STATUS
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| 249 |
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0246 0153 2A 75 01 lhld ptr_tx ; Get next byte from the TX buffer
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| 250 |
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0247 0156 7E mov a,m
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| 251 |
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0248 0157 FE 24 cpi '$' ; Did we reach the end of the buffer?
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| 252 |
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0249 0159 CA 62 01 jz irq_uart_tx_done ; If we did, we're done here...
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| 253 |
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0250 015C 23 inx h ; ...otherwise increment the TX pointer...
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| 254 |
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0251 015D 22 75 01 shld ptr_tx
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| 255 |
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0252 0160 D3 80 out UART_DATA ; ...and transmit the data byte.
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| 256 |
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0253 0162
|
| 257 |
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0254 0162 irq_uart_tx_done:
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| 258 |
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0255 0162
|
| 259 |
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0256 0162 irq_uart_end:
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| 260 |
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0257 0162 F1 pop psw ; Done, quit.
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| 261 |
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0258 0163 E1 pop h
|
| 262 |
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0259 0164 FB ei
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| 263 |
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0260 0165 C9 ret
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| 264 |
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0261 0166
|
| 265 |
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0262 0166 ;print_string: print $-terminated string at HL
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| 266 |
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0263 0166 print_string:
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| 267 |
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0264 0166 ; We don't check if there's a transmission going on
|
| 268 |
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0265 0166 7E mov a,m ; Get first character from string...
|
| 269 |
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0266 0167 23 inx h ; ...and move updated string pointer to TX
|
| 270 |
|
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0267 0168 22 75 01 shld ptr_tx ; buffer pointer.
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| 271 |
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0268 016B FE 24 cpi '$' ; Kickstart transmission by sending 1st byte...
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| 272 |
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0269 016D CA 72 01 jz print_string_end; ...unless its the end of string marker.
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| 273 |
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0270 0170 D3 80 out UART_DATA ;
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| 274 |
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0271 0172 print_string_end:
|
| 275 |
|
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0272 0172 C9 ret
|
| 276 |
|
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0273 0173
|
| 277 |
|
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0274 0173
|
| 278 |
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0275 0173 ; data space, placed immediately after object code in memory
|
| 279 |
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0276 0173 irq_data: ds(1)
|
| 280 |
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0276 0174
|
| 281 |
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0277 0174 24 void_buffer: .text "$"
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| 282 |
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0278 0175 ptr_tx: ds(2)
|
| 283 |
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0278 0177
|
| 284 |
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0279 0177 ptr_rx: ds(2)
|
| 285 |
|
|
0279 0179
|
| 286 |
|
|
0280 0179 len_rx: ds(1)
|
| 287 |
|
|
0280 017A
|
| 288 |
|
|
0281 017A rx_buffer: ds(32)
|
| 289 |
|
|
0281 019A
|
| 290 |
|
|
0282 019A ds(64)
|
| 291 |
|
|
0282 01DA
|
| 292 |
|
|
0283 01DA stack: ds(2)
|
| 293 |
|
|
0283 01DC
|
| 294 |
|
|
0284 01DC .end
|
| 295 |
|
|
0285 01DC tasm: Number of errors = 0
|
