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[/] [light8080/] [trunk/] [sw/] [tb/] [tb1/] [tb1.asm] - Blame information for rev 80

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;*******************************************************************************
; tb1.asm -- light8080 core test bench 1: interrupt & halt test
;*******************************************************************************
; Should be used with test bench template vhdl\test\tb_template.vhdl
; Assembler format compatible with TASM for DOS and Linux.
;*******************************************************************************
; This program will test a few different interrupt vectors and the interrupt
; enable/disable flag, but not exhaustively.
; Besides, it will not test long intr assertions (more than 1 cycle).
;*******************************************************************************
 
; DS pseudo-directive; reserve space in bytes, without initializing it
#define ds(n)    \.org $+n
 
; OUTing some value here will trigger intr in the n-th cycle from the end of
; the 'out' instruction. For example, writing a 0 will trigger intr in the 1st
; cycle of the following instruction, and so on.
intr_trigger: .equ 11h
; The value OUTput to this address will be used as the 'interrupt source' when
; the intr line is asserted. In the inta acknowledge cycle, the simulated
; interrupt logic will feed the CPU the instruction at memory address
; 40h+source*4. See vhdl\test\tb_template.vhdl for details.
intr_source:  .equ 10h
; The value OUTput to this port is the number of cycles the intr signal will
; remain high after being asserted. By default this is 1 cycle.
intr_width:   .equ 12h
; OUTing something here will stop the simulation. A 0x055 will signal a
; success, a 0x0aa a failure.
test_outcome: .equ 20h
 
;*******************************************************************************
 
        .org    0H
        jmp     start           ; skip the rst address area
 
        ; used to test that RST works
        .org    20H
        adi     1H
        ei
        ret
 
        ; used to test the RST instruction as intr vector
        .org    28H
        inr     a
        ei
        ret
 
        ;***** simulated interrupt vectors in area 0040h-005fh *****************
 
        .org    40h+(0*4)       ; simulated interrupt vector 0
        inr     a
        .org    40h+(1*4)       ; simulated interrupt vector 1
        rst     5
        .org    40h+(2*4)       ; simulated interrupt vector 2
        inx     h
        .org    40h+(3*4)       ; simulated interrupt vector 3
        mvi     a,42h
        .org    40h+(4*4)       ; simulated interrupt vector 4
        lxi     h,1234h
        .org    40h+(5*4)       ; simulated interrupt vector 5
        jmp     test_jump
        .org    40h+(6*4)       ; simulated interrupt vector 6
        call    test_call
        .org    40h+(7*4)       ; simulated interrupt vector 7
        call    shouldnt_trigger
 
 
        ;***** program entry point *********************************************
 
start:  .org    60H
        lxi     sp,stack
 
        ; first of all, make sure the RST instruction works, we have a valid
        ; simulated stack, etc.
        mvi     a,13h
        rst     4               ; this should add 1 to ACC
        cpi     14h
        jnz     fail
 
        ; now we'll try a few different interrupt vectors (single byte and
        ; multi-byte). Since interrupts are disabled upon acknowledge, we have
        ; to reenable them after every test.
 
        ; try single-byte interrupt vector: INR A
        mvi     a,0
        out     intr_source
        ei
        mvi     a,014h
        out     intr_trigger
        mvi     a,027h
        nop                       ; the interrupt will hit in this nop area
        nop
        nop
        nop
        cpi     028h
        jnz     fail
 
        ; another single-byte vector: RST 5
        mvi     a,1
        out     intr_source
        ei
        mvi     a,014h
        out     intr_trigger      ; the interrupt vector will do a rst 5, and
        mvi     a,020h            ; the rst routine will add 1 to the ACC
        nop                       ; and reenable interrupts
        nop
        nop
        nop
        cpi     021h
        jnz     fail
 
        ; another single-byte code: INX H
        lxi     h,13ffh
        mvi     a,2
        out     intr_source
        ei
        mvi     a,4
        out     intr_trigger
        nop
        nop
        mov     a,l
        cpi     0H
        jnz     fail
        mov     a,h
        cpi     14h
        jnz     fail
 
        ; a two-byte instruction: mvi a, 42h
        mvi     a,3
        out     intr_source
        ei
        mvi     a,4
        out     intr_trigger
        nop
        nop
        cpi     42h
        jnz     fail
 
        ; a three-byte instruction: lxi h,1234h
        mvi     a,4
        out     intr_source
        ei
        mvi     a,4
        out     intr_trigger
        nop
        nop
        mov     a,h
        cpi     12h
        jnz     fail
        mov     a,l
        cpi     34h
        jnz     fail
 
        ; a 3-byte jump: jmp test_jump
        ; if this fails, the test will probably derail
        mvi     a,5
        out     intr_source
        ei
        mvi     a,4
        out     intr_trigger
        nop
        nop
comeback:
        cpi     79h
        jnz     fail
 
        ; a 3-byte call: call test_call
        ; if this fails, the test will probably derail
        mvi     a,6
        out     intr_source
        ei
        mvi     a,4
        out     intr_trigger
        inr     a
        ; the interrupt will come back here, hopefully
        nop
        cpi     05h
        jnz     fail
        mov     a,b
        cpi     19h
        jnz     fail
 
        ; now, with interrupts disabled, make sure interrupts are ignored
        di
        mvi     a,07h           ; source 7 catches any unwanted interrupts
        out     intr_source
        mvi     a,04h
        out     intr_trigger
        nop
        nop
        nop
 
        ; Ok. So far we have tested only 1-cycle intr assertions. Now we'll
        ; see what happens when we leave intr asserted for a long time (as would
        ; happen intr was used for single-step debugging, for instance)
 
        ; try single-byte interrupt vector (INR A)
        mvi     a, 80
        out     intr_width
        mvi     a,1
        out     intr_source
        ei
        mvi     a,014h
        out     intr_trigger
        mvi     a,027h
        nop                       ; the interrupts will hit in this nop area
        nop
        inr     a
        nop
        nop
        inr     a
        nop
        nop
        nop
        nop
        nop
        cpi     02bh
        jnz     fail
 
 
        ; finished, run into the success outcome code
 
success:
        mvi     a,55h
        out     test_outcome
        hlt
fail:   mvi     a,0aah
        out     test_outcome
        hlt
 
test_jump:
        mvi     a,79h
        jmp     comeback
 
test_call:
        mvi     b,19h
        ret
 
; called when an interrupt has been acknowledged that shouldn't have
shouldnt_trigger:
        jmp     fail
 
        ; data space
        ds(64)
stack:  ds(2)
        .end
 

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[/] [light8080/] [trunk/] [sw/] [tb/] [tb1/] [tb1.asm] - Blame information for rev 80

Line No.	Rev	Author	Line
1	74	ja_rd	`;*******************************************************************************`
2			`; tb1.asm -- light8080 core test bench 1: interrupt & halt test`
3			`;*******************************************************************************`
4			`; Should be used with test bench template vhdl\test\tb_template.vhdl`
5			`; Assembler format compatible with TASM for DOS and Linux.`
6			`;*******************************************************************************`
7			`; This program will test a few different interrupt vectors and the interrupt`
8			`; enable/disable flag, but not exhaustively.`
9			`; Besides, it will not test long intr assertions (more than 1 cycle).`
10			`;*******************************************************************************`
11
12			`; DS pseudo-directive; reserve space in bytes, without initializing it`
13			`#define ds(n) \.org $+n`
14
15			`; OUTing some value here will trigger intr in the n-th cycle from the end of`
16			`; the 'out' instruction. For example, writing a 0 will trigger intr in the 1st`
17			`; cycle of the following instruction, and so on.`
18			`intr_trigger: .equ 11h`
19			`; The value OUTput to this address will be used as the 'interrupt source' when`
20			`; the intr line is asserted. In the inta acknowledge cycle, the simulated`
21			`; interrupt logic will feed the CPU the instruction at memory address`
22			`; 40h+source*4. See vhdl\test\tb_template.vhdl for details.`
23			`intr_source: .equ 10h`
24			`; The value OUTput to this port is the number of cycles the intr signal will`
25			`; remain high after being asserted. By default this is 1 cycle.`
26			`intr_width: .equ 12h`
27			`; OUTing something here will stop the simulation. A 0x055 will signal a`
28			`; success, a 0x0aa a failure.`
29			`test_outcome: .equ 20h`
30
31			`;*******************************************************************************`
32
33			`.org 0H`
34			`jmp start ; skip the rst address area`
35
36			`; used to test that RST works`
37			`.org 20H`
38			`adi 1H`
39			`ei`
40			`ret`
41
42			`; used to test the RST instruction as intr vector`
43			`.org 28H`
44			`inr a`
45			`ei`
46			`ret`
47
48			`;*** simulated interrupt vectors in area 0040h-005fh ***************`
49
50			`.org 40h+(0*4) ; simulated interrupt vector 0`
51			`inr a`
52			`.org 40h+(1*4) ; simulated interrupt vector 1`
53			`rst 5`
54			`.org 40h+(2*4) ; simulated interrupt vector 2`
55			`inx h`
56			`.org 40h+(3*4) ; simulated interrupt vector 3`
57			`mvi a,42h`
58			`.org 40h+(4*4) ; simulated interrupt vector 4`
59			`lxi h,1234h`
60			`.org 40h+(5*4) ; simulated interrupt vector 5`
61			`jmp test_jump`
62			`.org 40h+(6*4) ; simulated interrupt vector 6`
63			`call test_call`
64			`.org 40h+(7*4) ; simulated interrupt vector 7`
65			`call shouldnt_trigger`
66
67
68			`;*** program entry point *******************************************`
69
70			`start: .org 60H`
71			`lxi sp,stack`
72
73			`; first of all, make sure the RST instruction works, we have a valid`
74			`; simulated stack, etc.`
75			`mvi a,13h`
76			`rst 4 ; this should add 1 to ACC`
77			`cpi 14h`
78			`jnz fail`
79
80			`; now we'll try a few different interrupt vectors (single byte and`
81			`; multi-byte). Since interrupts are disabled upon acknowledge, we have`
82			`; to reenable them after every test.`
83
84			`; try single-byte interrupt vector: INR A`
85			`mvi a,0`
86			`out intr_source`
87			`ei`
88			`mvi a,014h`
89			`out intr_trigger`
90			`mvi a,027h`
91			`nop ; the interrupt will hit in this nop area`
92			`nop`
93			`nop`
94			`nop`
95			`cpi 028h`
96			`jnz fail`
97
98			`; another single-byte vector: RST 5`
99			`mvi a,1`
100			`out intr_source`
101			`ei`
102			`mvi a,014h`
103			`out intr_trigger ; the interrupt vector will do a rst 5, and`
104			`mvi a,020h ; the rst routine will add 1 to the ACC`
105			`nop ; and reenable interrupts`
106			`nop`
107			`nop`
108			`nop`
109			`cpi 021h`
110			`jnz fail`
111
112			`; another single-byte code: INX H`
113			`lxi h,13ffh`
114			`mvi a,2`
115			`out intr_source`
116			`ei`
117			`mvi a,4`
118			`out intr_trigger`
119			`nop`
120			`nop`
121			`mov a,l`
122			`cpi 0H`
123			`jnz fail`
124			`mov a,h`
125			`cpi 14h`
126			`jnz fail`
127
128			`; a two-byte instruction: mvi a, 42h`
129			`mvi a,3`
130			`out intr_source`
131			`ei`
132			`mvi a,4`
133			`out intr_trigger`
134			`nop`
135			`nop`
136			`cpi 42h`
137			`jnz fail`
138
139			`; a three-byte instruction: lxi h,1234h`
140			`mvi a,4`
141			`out intr_source`
142			`ei`
143			`mvi a,4`
144			`out intr_trigger`
145			`nop`
146			`nop`
147			`mov a,h`
148			`cpi 12h`
149			`jnz fail`
150			`mov a,l`
151			`cpi 34h`
152			`jnz fail`
153
154			`; a 3-byte jump: jmp test_jump`
155			`; if this fails, the test will probably derail`
156			`mvi a,5`
157			`out intr_source`
158			`ei`
159			`mvi a,4`
160			`out intr_trigger`
161			`nop`
162			`nop`
163			`comeback:`
164			`cpi 79h`
165			`jnz fail`
166
167			`; a 3-byte call: call test_call`
168			`; if this fails, the test will probably derail`
169			`mvi a,6`
170			`out intr_source`
171			`ei`
172			`mvi a,4`
173			`out intr_trigger`
174			`inr a`
175			`; the interrupt will come back here, hopefully`
176			`nop`
177			`cpi 05h`
178			`jnz fail`
179			`mov a,b`
180			`cpi 19h`
181			`jnz fail`
182
183			`; now, with interrupts disabled, make sure interrupts are ignored`
184			`di`
185			`mvi a,07h ; source 7 catches any unwanted interrupts`
186			`out intr_source`
187			`mvi a,04h`
188			`out intr_trigger`
189			`nop`
190			`nop`
191			`nop`
192
193			`; Ok. So far we have tested only 1-cycle intr assertions. Now we'll`
194			`; see what happens when we leave intr asserted for a long time (as would`
195			`; happen intr was used for single-step debugging, for instance)`
196
197			`; try single-byte interrupt vector (INR A)`
198			`mvi a, 80`
199			`out intr_width`
200			`mvi a,1`
201			`out intr_source`
202			`ei`
203			`mvi a,014h`
204			`out intr_trigger`
205			`mvi a,027h`
206			`nop ; the interrupts will hit in this nop area`
207			`nop`
208			`inr a`
209			`nop`
210			`nop`
211			`inr a`
212			`nop`
213			`nop`
214			`nop`
215			`nop`
216			`nop`
217			`cpi 02bh`
218			`jnz fail`
219
220
221			`; finished, run into the success outcome code`
222
223			`success:`
224			`mvi a,55h`
225			`out test_outcome`
226			`hlt`
227			`fail: mvi a,0aah`
228			`out test_outcome`
229			`hlt`
230
231			`test_jump:`
232			`mvi a,79h`
233			`jmp comeback`
234
235			`test_call:`
236			`mvi b,19h`
237			`ret`
238
239			`; called when an interrupt has been acknowledged that shouldn't have`
240			`shouldnt_trigger:`
241			`jmp fail`
242
243			`; data space`
244			`ds(64)`
245			`stack: ds(2)`
246			`.end`
247