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ja_rd |
0001 0000 ;*******************************************************************************
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0002 0000 ; tb1.asm -- light8080 core test bench 1: interrupt & halt test
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0003 0000 ;*******************************************************************************
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0004 0000 ; Should be used with test bench template vhdl\test\tb_template.vhdl
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0005 0000 ; Assembler format compatible with TASM for DOS and Linux.
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0006 0000 ;*******************************************************************************
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0007 0000 ; This program will test a few different interrupt vectors and the interrupt
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0008 0000 ; enable/disable flag, but not exhaustively.
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0009 0000 ; Besides, it will not test long intr assertions (more than 1 cycle).
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0010 0000 ;*******************************************************************************
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0011 0000
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0012 0000 ; DS pseudo-directive; reserve space in bytes, without initializing it
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0013 0000 #define ds(n) \.org $+n
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0014 0000
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0015 0000 ; OUTing some value here will trigger intr in the n-th cycle from the end of
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0016 0000 ; the 'out' instruction. For example, writing a 0 will trigger intr in the 1st
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0017 0000 ; cycle of the following instruction, and so on.
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0018 0000 intr_trigger: .equ 11h
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0019 0000 ; The value OUTput to this address will be used as the 'interrupt source' when
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0020 0000 ; the intr line is asserted. In the inta acknowledge cycle, the simulated
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0021 0000 ; interrupt logic will feed the CPU the instruction at memory address
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0022 0000 ; 40h+source*4. See vhdl\test\tb_template.vhdl for details.
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0023 0000 intr_source: .equ 10h
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0024 0000 ; The value OUTput to this port is the number of cycles the intr signal will
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0025 0000 ; remain high after being asserted. By default this is 1 cycle.
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0026 0000 intr_width: .equ 12h
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0027 0000 ; OUTing something here will stop the simulation. A 0x055 will signal a
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0028 0000 ; success, a 0x0aa a failure.
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0029 0000 test_outcome: .equ 20h
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0030 0000
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0031 0000 ;*******************************************************************************
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0032 0000
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0033 0000 .org 0H
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0034 0000 C3 60 00 jmp start ; skip the rst address area
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0035 0003
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0036 0003 ; used to test that RST works
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0037 0020 .org 20H
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0038 0020 C6 01 adi 1H
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0039 0022 FB ei
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0040 0023 C9 ret
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0041 0024
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0042 0024 ; used to test the RST instruction as intr vector
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0043 0028 .org 28H
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0044 0028 3C inr a
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0045 0029 FB ei
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0046 002A C9 ret
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0047 002B
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0048 002B ;***** simulated interrupt vectors in area 0040h-005fh *****************
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0049 002B
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0050 0040 .org 40h+(0*4) ; simulated interrupt vector 0
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0051 0040 3C inr a
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0052 0044 .org 40h+(1*4) ; simulated interrupt vector 1
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0053 0044 EF rst 5
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0054 0048 .org 40h+(2*4) ; simulated interrupt vector 2
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0055 0048 23 inx h
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0056 004C .org 40h+(3*4) ; simulated interrupt vector 3
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0057 004C 3E 42 mvi a,42h
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0058 0050 .org 40h+(4*4) ; simulated interrupt vector 4
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0059 0050 21 34 12 lxi h,1234h
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0060 0054 .org 40h+(5*4) ; simulated interrupt vector 5
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0061 0054 C3 2F 01 jmp test_jump
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0062 0058 .org 40h+(6*4) ; simulated interrupt vector 6
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0063 0058 CD 34 01 call test_call
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0064 005C .org 40h+(7*4) ; simulated interrupt vector 7
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0065 005C CD 37 01 call shouldnt_trigger
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0066 005F
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0067 005F
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0068 005F ;***** program entry point *********************************************
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0069 005F
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0070 0060 start: .org 60H
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0071 0060 31 7A 01 lxi sp,stack
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0072 0063
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0073 0063 ; first of all, make sure the RST instruction works, we have a valid
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0074 0063 ; simulated stack, etc.
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0075 0063 3E 13 mvi a,13h
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0076 0065 E7 rst 4 ; this should add 1 to ACC
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0077 0066 FE 14 cpi 14h
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0078 0068 C2 2A 01 jnz fail
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0079 006B
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0080 006B ; now we'll try a few different interrupt vectors (single byte and
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0081 006B ; multi-byte). Since interrupts are disabled upon acknowledge, we have
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0082 006B ; to reenable them after every test.
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0083 006B
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0084 006B ; try single-byte interrupt vector: INR A
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0085 006B 3E 00 mvi a,0
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0086 006D D3 10 out intr_source
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0087 006F FB ei
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0088 0070 3E 14 mvi a,014h
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0089 0072 D3 11 out intr_trigger
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0090 0074 3E 27 mvi a,027h
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0091 0076 00 nop ; the interrupt will hit in this nop area
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0092 0077 00 nop
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0093 0078 00 nop
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0094 0079 00 nop
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0095 007A FE 28 cpi 028h
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0096 007C C2 2A 01 jnz fail
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0097 007F
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0098 007F ; another single-byte vector: RST 5
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0099 007F 3E 01 mvi a,1
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0100 0081 D3 10 out intr_source
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0101 0083 FB ei
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0102 0084 3E 14 mvi a,014h
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0103 0086 D3 11 out intr_trigger ; the interrupt vector will do a rst 5, and
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0104 0088 3E 20 mvi a,020h ; the rst routine will add 1 to the ACC
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0105 008A 00 nop ; and reenable interrupts
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0106 008B 00 nop
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0107 008C 00 nop
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0108 008D 00 nop
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0109 008E FE 21 cpi 021h
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0110 0090 C2 2A 01 jnz fail
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0111 0093
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0112 0093 ; another single-byte code: INX H
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0113 0093 21 FF 13 lxi h,13ffh
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0114 0096 3E 02 mvi a,2
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0115 0098 D3 10 out intr_source
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0116 009A FB ei
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0117 009B 3E 04 mvi a,4
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0118 009D D3 11 out intr_trigger
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0119 009F 00 nop
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0120 00A0 00 nop
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0121 00A1 7D mov a,l
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0122 00A2 FE 00 cpi 0H
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0123 00A4 C2 2A 01 jnz fail
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0124 00A7 7C mov a,h
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0125 00A8 FE 14 cpi 14h
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0126 00AA C2 2A 01 jnz fail
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0127 00AD
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0128 00AD ; a two-byte instruction: mvi a, 42h
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0129 00AD 3E 03 mvi a,3
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0130 00AF D3 10 out intr_source
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0131 00B1 FB ei
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0132 00B2 3E 04 mvi a,4
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0133 00B4 D3 11 out intr_trigger
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0134 00B6 00 nop
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0135 00B7 00 nop
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0136 00B8 FE 42 cpi 42h
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0137 00BA C2 2A 01 jnz fail
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0138 00BD
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0139 00BD ; a three-byte instruction: lxi h,1234h
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0140 00BD 3E 04 mvi a,4
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0141 00BF D3 10 out intr_source
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0142 00C1 FB ei
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0143 00C2 3E 04 mvi a,4
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0144 00C4 D3 11 out intr_trigger
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0145 00C6 00 nop
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0146 00C7 00 nop
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0147 00C8 7C mov a,h
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0148 00C9 FE 12 cpi 12h
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0149 00CB C2 2A 01 jnz fail
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0150 00CE 7D mov a,l
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0151 00CF FE 34 cpi 34h
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0152 00D1 C2 2A 01 jnz fail
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0153 00D4
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0154 00D4 ; a 3-byte jump: jmp test_jump
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0155 00D4 ; if this fails, the test will probably derail
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0156 00D4 3E 05 mvi a,5
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0157 00D6 D3 10 out intr_source
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0158 00D8 FB ei
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0159 00D9 3E 04 mvi a,4
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0160 00DB D3 11 out intr_trigger
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0161 00DD 00 nop
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0162 00DE 00 nop
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0163 00DF comeback:
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0164 00DF FE 79 cpi 79h
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0165 00E1 C2 2A 01 jnz fail
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0166 00E4
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0167 00E4 ; a 3-byte call: call test_call
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0168 00E4 ; if this fails, the test will probably derail
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0169 00E4 3E 06 mvi a,6
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0170 00E6 D3 10 out intr_source
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0171 00E8 FB ei
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0172 00E9 3E 04 mvi a,4
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0173 00EB D3 11 out intr_trigger
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0174 00ED 3C inr a
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0175 00EE ; the interrupt will come back here, hopefully
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0176 00EE 00 nop
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0177 00EF FE 05 cpi 05h
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0178 00F1 C2 2A 01 jnz fail
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0179 00F4 78 mov a,b
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0180 00F5 FE 19 cpi 19h
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0181 00F7 C2 2A 01 jnz fail
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0182 00FA
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0183 00FA ; now, with interrupts disabled, make sure interrupts are ignored
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0184 00FA F3 di
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0185 00FB 3E 07 mvi a,07h ; source 7 catches any unwanted interrupts
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0186 00FD D3 10 out intr_source
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0187 00FF 3E 04 mvi a,04h
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0188 0101 D3 11 out intr_trigger
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0189 0103 00 nop
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0190 0104 00 nop
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0191 0105 00 nop
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0192 0106
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0193 0106 ; Ok. So far we have tested only 1-cycle intr assertions. Now we'll
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0194 0106 ; see what happens when we leave intr asserted for a long time (as would
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0195 0106 ; happen intr was used for single-step debugging, for instance)
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0196 0106
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0197 0106 ; try single-byte interrupt vector (INR A)
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0198 0106 3E 50 mvi a, 80
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0199 0108 D3 12 out intr_width
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0200 010A 3E 01 mvi a,1
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0201 010C D3 10 out intr_source
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0202 010E FB ei
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0203 010F 3E 14 mvi a,014h
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0204 0111 D3 11 out intr_trigger
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0205 0113 3E 27 mvi a,027h
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0206 0115 00 nop ; the interrupts will hit in this nop area
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0207 0116 00 nop
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0208 0117 3C inr a
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0209 0118 00 nop
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0210 0119 00 nop
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0211 011A 3C inr a
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0212 011B 00 nop
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0213 011C 00 nop
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0214 011D 00 nop
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0215 011E 00 nop
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0216 011F 00 nop
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0217 0120 FE 2B cpi 02bh
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0218 0122 C2 2A 01 jnz fail
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0219 0125
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0220 0125
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0221 0125 ; finished, run into the success outcome code
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0222 0125
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0223 0125 success:
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0224 0125 3E 55 mvi a,55h
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0225 0127 D3 20 out test_outcome
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0226 0129 76 hlt
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0227 012A 3E AA fail: mvi a,0aah
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0228 012C D3 20 out test_outcome
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0229 012E 76 hlt
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0230 012F
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0231 012F test_jump:
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0232 012F 3E 79 mvi a,79h
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0233 0131 C3 DF 00 jmp comeback
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0234 0134
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0235 0134 test_call:
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0236 0134 06 19 mvi b,19h
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0237 0136 C9 ret
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0238 0137
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0239 0137 ; called when an interrupt has been acknowledged that shouldn't have
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0240 0137 shouldnt_trigger:
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0241 0137 C3 2A 01 jmp fail
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0242 013A
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0243 013A ; data space
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0244 013A ds(64)
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0244 017A
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0245 017A stack: ds(2)
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0245 017C
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0246 017C .end
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0247 017C tasm: Number of errors = 0
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