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[/] [light8080/] [trunk/] [ucode/] [light8080.m80] - Blame information for rev 49

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////////////////////////////////////////////////////////////////////////////////
// LIGHT8080 CORE MICROCODE (V.1 November 1st 2007)
////////////////////////////////////////////////////////////////////////////////
// NOTE: Except for bug fixing, there's no need to tinker with the microcode.
// Once the microcode table has been generated, this file is is not needed to
// synthesize or use the core.
////////////////////////////////////////////////////////////////////////////////
//
// ***** FORMAT AND OPERATION:
//
// operation 1 ; operation 2 ; flags
//
// Operation 1 sets up the ALU input registers; operation 2 takes the ALU result
// and writes it back somewhere; and the flags group all other microinstruction
// control signals.
//
// For any given microinstruction, operation 2 takes place in the cycle after
// operation 1. It happens concurrently with the next microinstruction's
// operation 1, so whenever a register is written to in an operation 2 it will
// NOT be available for the next microinstruction.
//
// In operation 1, you may load any one of T1 or T2 from the register bank or
// from DI which is simply the unregistered signal data_in.
//
// In operation 2, you specify the ALU operation and assign the ALU result to
// the register bank or the register DO, which feeds the signal data_out.
//
// You cannot address two different registers from the register bank in
// operations 1 and 2 (see the design notes on this).
//
// *** Some other elements found in the microcode source:
//
// labels: must be in a line by themselves, otherwise work like any assembler.
// __code pragmas: used by assembler to automatically generate the decode table.
// __asm pragmas: not used, but can be handy as a reference.
//
//
// ***** FLAGS:
//
// Note: '1st cycle' and '2nd cycle' denote both cycles of the present
// microinstruction (m.i.); cycle 2 of m.i. N overlaps cycle 1 of m.i. N+1.
//
// #ld_al :   Load AL register with register bank output as read by operation 1.
//            (used in memory and io access).
// #ld_addr : Load address register (H byte = register bank output as read by
//            operation 1, L byte = AL).
//            Activate vma signal for 1st cycle.
// #auxcy :   Use aux carry instead of regular carry for this operation.
// #setacy :  Set aux carry at the start of 1st cycle (used for ++).
// #end :     Jump to microinstruction address 3 after the present m.i.
// #ret :     Jump to address saved by the last JST or TJSR m.i.
// #rd :      Activate rd signal for the 2nd cycle.
// #wr :      Activate wr signal for the 2nd cycle.
// #fp_r :    This microinstruction updates all PSW flags except for C.
// #fp_c :    This microinstruction updates only the C flag in the PSW.
// #fp_rc :   This microinstruction updates all the flags in the PSW.
// #clrt1 :   Clear T1 at the end of 1st cycle.
// #io :      Activate io signal for 1st cycle.
// #ei :      Set interrupt enable register.
// #di :      Reset interrupt enable register.
// #halt :    Jump to microcode address 0x07 without saving return value.
//
////////////////////////////////////////////////////////////////////////////////
 
// RESET ucode: from 0 to 2, but uinst at address 0 is never executed
__reset
 
NOP           ; NOP
NOP           ; _pl = AND                       ;                                                                 // T1 & T2 = 0x00
NOP           ; _ph = AND     ;                                                           // T1 & T2 = 0x00
 
// FETCH ucode: from 3 to 6
// (executed in INTA cycles too, with pc increment inhibited to preserve PC)
__fetch
 
T1 = _pl      ; _pl = ADC     ; #ld_al, #auxcy, #setacy
T1 = _ph      ; _ph = ADC     ; #ld_addr, #rd, #auxcy
NOP           ; NOP           ; #decode
 
// free uinst slot
NOP           ; NOP           ;
 
// HALT ucode: address 7
__halt
NOP           ; NOP           ; #halt, #end
 
 
// NOTE: ALU single_operand ops work on T1
// ALU 2-operands work with 'A' on T2 (e.g. SUB == T2 - T1)
 
 
__code  "01dddsss"
__asm   MOV {d},{s}
 
T1 = {s}      ; NOP
NOP           ; {d} = T1      ; #end
 
 
__code  "01ddd110"
__asm   MOV {d},M
 
JSR read_m              ;
NOP           ; {d} = T1      ; #end
 
 
__code  "01110sss"
__asm   MOV M,{s}
 
T1 = {s}      ; DO = T1
JSR write_m                   // does not return
 
 
__code  "00ddd110"
__asm   MVI {d},#imm
 
JSR read_imm
NOP           ; {d} = T1      ; #end
 
 
__code  "00110110"
__asm   MVI M,#imm
 
JSR read_imm
JSR write_m
 
 
__code  "00pp0001"
__asm   LXI [p]
 
JSR read_imm
NOP           ; {p}1 = T1
JSR read_imm
NOP           ; {p}0 = T1     ; #end
 
 
__code  "00111010"
__asm   LDA addr
 
JSR read_imm_wz
JSR read_wz
NOP           ; _a = T1       ; #end
 
 
__code  "00110010"
__asm   STA addr
 
JSR read_imm_wz
T1 = _a       ; DO = T1       ;
JSR write_wz                    //does not return
 
 
__code  "00101010"
__asm   LHLD
 
 
JSR read_imm_wz
T1 = _z       ; _z = ADC      ; #ld_al, #auxcy, #setacy // L = (WZ++)
T1 = _w       ; _w = ADC      ; #ld_addr, #rd, #auxcy
T1 = DI       ; _l = T1
JSR read_wz                                             // H = (WZ)
NOP           ; _h = T1       ; #end
 
 
__code  "00100010"
__asm   SHLD
 
JSR read_imm_wz
T1 = _l       ; DO = T1
T1 = _z       ; _z = ADC      ; #ld_al, #auxcy, #setacy
T1 = _w       ; _w = ADC      ; #ld_addr, #wr, #auxcy
T1 = _h       ; DO = T1
JSR write_wz
 
 
__code  "00pp1010"
__asm   LDAX [p]
 
JSR read_p
NOP           ; _a = T1       ; #end
 
 
__code  "00pp0010"
__asm   STAX [p]
 
T1 = _a       ; DO = T1
JSR write_p
 
 
__code  "11101011"
__asm   XCHG
 
// 16 T cycles vs. 10 for the original 8080...
T1 = _d       ; NOP
NOP           ; _x = T1
T1 = _e       ; NOP
NOP           ; _y = T1
T1 = _h       ; NOP
NOP           ; _d = T1
T1 = _l       ; NOP
NOP           ; _e = T1
T1 = _x       ; NOP
NOP           ; _h = T1
T1 = _y       ; NOP
NOP           ; _l = T1         ; #end
 
 
__code  "11000110"
__asm   ADI #imm
 
JSR read_imm
T2 = _a       ; _a = ADD      ; #end, #fp_rc
 
__code  "11001110"
__asm   ACI #imm
 
JSR read_imm
T2 = _a       ; _a = ADC      ; #end, #fp_rc
 
__code  "11010110"
__asm   SUI #imm
 
JSR read_imm
T2 = _a       ; _a = SUB      ; #end, #fp_rc
 
__code  "11011110"
__asm   SBI #imm
 
JSR read_imm
T2 = _a       ; _a = SBB      ; #end, #fp_rc
 
 
__code  "11100110"
__asm   ANI #imm
 
JSR read_imm
T2 = _a       ; _a = AND      ; #end, #fp_rc
 
__code  "11101110"
__asm   XRI #imm
 
JSR read_imm
T2 = _a       ; _a = XRL      ; #end, #fp_rc
 
 
__code  "11110110"
__asm   ORI #imm
 
JSR read_imm
T2 = _a       ; _a = ORL      ; #end, #fp_rc
 
 
__code  "11111110"
__asm   CPI #imm
 
JSR read_imm
T2 = _a       ; DO = SUB      ; #end, #fp_rc
 
 
 
__code  "10000sss"
__asm   ADD {s}
 
T1 = {s}      ; NOP
T2 = _a       ; _a = ADD      ; #end, #fp_rc
 
__code  "10001sss"
__asm   ADC {s}
 
T1 = {s}      ; NOP
T2 = _a       ; _a = ADC      ; #end, #fp_rc
 
__code  "10010sss"
__asm   SUB {s}
 
T1 = {s}      ; NOP
T2 = _a       ; _a = SUB      ; #end, #fp_rc
 
__code  "10011sss"
__asm   SBB {s}
 
T1 = {s}      ; NOP
T2 = _a       ; _a = SBB      ; #end, #fp_rc
 
__code  "10100sss"
__asm   ANA {s}
 
T1 = {s}      ; NOP
T2 = _a       ; _a = AND      ; #end, #fp_rc
 
__code  "10101sss"
__asm   XRA {s}
 
T1 = {s}      ; NOP
T2 = _a       ; _a = XRL      ; #end, #fp_rc
 
__code  "10110sss"
__asm   ORA {s}
 
T1 = {s}      ; NOP
T2 = _a       ; _a = ORL      ; #end, #fp_rc
 
__code  "10111sss"
__asm   CMP {s}
 
T1 = {s}      ; NOP
T2 = _a       ; DO = SUB      ; #end, #fp_rc
 
 
__code  "10000110"
__asm   ADD M
 
JSR read_m
T2 = _a       ; _a = ADD      ; #end, #fp_rc
 
__code  "10001110"
__asm   ADC M
 
JSR read_m
T2 = _a       ; _a = ADC      ; #end, #fp_rc
 
__code  "10010110"
__asm   SUB M
 
JSR read_m
T2 = _a       ; _a = SUB      ; #end, #fp_rc
 
__code  "10011110"
__asm   SBB M
 
JSR read_m
T2 = _a       ; _a = SBB      ; #end, #fp_rc
 
__code  "10100110"
__asm   ANA M
 
JSR read_m
T2 = _a       ; _a = AND      ; #end, #fp_rc
 
__code  "10101110"
__asm   XRA M
 
JSR read_m
T2 = _a       ; _a = XRL      ; #end, #fp_rc
 
__code  "10110110"
__asm   ORA M
 
JSR read_m
T2 = _a       ; _a = ORL      ; #end, #fp_rc
 
 
__code  "10111110"
__asm   CMP M
 
JSR read_m
T2 = _a       ; DO = SUB      ; #end, #fp_rc
 
 
__code  "00ddd100"
__asm   INR {d}
 
T1 = {d}      ; {d} = ADC     ; #auxcy, #setacy, #fp_r
NOP           ; NOP           ; #end  // extra line, flag clash
 
 
__code  "00110100"
__asm   INR M
 
JSR read_m
NOP           ; DO = ADC      ; #auxcy, #setacy, #fp_r
JSR write_m
 
 
__code  "00ddd101"
__asm   DCR {d}
 
T2 = {d}      ; {d} = SBB     ; #auxcy, #setacy, #fp_r
NOP           ; NOP           ; #end   // extra line, flag clash
 
 
__code  "00110101"
__asm   DCR M
 
JSR read_m // T1 = _x = (HL); but we need it in T2!
NOP           ; NOP           ; #clrt1 // flag clash
T2 = _x       ; DO = SBB      ; #auxcy, #setacy, #fp_r
JSR write_m
 
 
__code  "00pp0011"
__asm   INX [p]
 
T1 = {p}1     ; {p}1 = ADC      ; #auxcy, #setacy
T1 = {p}0     ; {p}0 = ADC      ; #end, #auxcy
 
 
__code  "00pp1011"
__asm   DCX [p]
 
T2 = {p}1     ; {p}1 = SBB      ; #auxcy, #setacy  // T2 because SUB -> T2 - T1
T2 = {p}0     ; {p}0 = SBB      ; #end, #auxcy
 
 
__code  "00pp1001"
__asm   DAD [p]
 
T2 = {p}1     ; NOP
T1 = _l       ; _l = ADD      ; #fp_c // we need this cy
T2 = {p}0     ; NOP           ;
T1 = _h       ; _h = ADC      ; #end, #fp_c
 
 
__code  "00100111"
__asm   DAA
 
// DAA result is only valid after the 2nd cycle;
T1 = _a       ; DO = DAA        ; //DO value ignored
T1 = _a       ; _a = DAA        ; #end, #fp_rc
 
 
__code  "00000111"
__asm   RLC
 
T1 = _a       ; _a = rla       ; #end, #fp_c
 
 
__code  "00001111"
__asm   RRC
 
T1 = _a       ; _a = rra       ; #end, #fp_c
 
 
__code  "00010111"
__asm   RAL
 
T1 = _a       ; _a = rlca      ; #end, #fp_c
 
 
__code  "00011111"
__asm   RAR
 
T1 = _a       ; _a = rrca      ; #end, #fp_c
 
 
__code  "00101111"
__asm   CMA
 
T1 = _a       ; _a = NOT        ; #end
 
 
__code  "00111111"
__asm   CMC
 
NOP           ; cpc              ; #end, #fp_c
 
 
__code  "00110111"
__asm   STC
 
NOP           ; sec              ; #end, #fp_c
 
 
__code  "11000011"
__asm   JMP addr
 
JSR read_imm_wz
:jmp_addr
T1 = _z       ; NOP
NOP           ; _pl = T1
T1 = _w       ; NOP
NOP           ; _ph = T1      ; #end
 
 
 
__code  "00000000"
__asm   NOP
 
NOP           ; NOP           ; #end
 
 
__code  "11ccc010"
__asm   {JZ,JNZ,JC,JNC,JPO,JPE,JP,JM} addr
 
JSR read_imm_wz
TJSR jmp_addr           // TJSR does the JSR or does #end the instruction.
 
 
__code  "11001101"
__asm   CALL addr
 
//:call_addr
JSR read_imm_wz
:call_addr //@@
T1 = _ph      ; DO = T1         ; #clrt1
JSR push
T1 = _pl      ; DO = T1         ; #clrt1
JSR push
T1 = _z       ; NOP
NOP           ; _pl = T1
T1 = _w       ; NOP
NOP           ; _ph = T1        ; #end
 
 
 
__code  "11ccc100"
__asm   {CZ,CNZ,CC,CNC,CPO,CPE,CP,CM} addr
 
JSR read_imm_wz     // skip next 2 bytes
TJSR call_addr      // TJSR does the JSR or does #end the instruction.
 
 
__code  "11001001"
__asm   RET
 
:ret
JSR pop
NOP           ; _pl = T1
JSR pop
NOP           ; _ph = T1        ; #end
 
 
__code  "11ccc000"
__asm   {RZ,RNZ,RC,RNC,RPO,RPE,RP,RM}
 
 
TJSR ret      // TJSR does the JSR or does #end the instruction.
 
 
 
__code  "11nnn111"
__asm   {RST 0h,RST 8h,RST 10h,RST 18h,RST 20h,RST 28h,RST 30h,RST 38h}
 
T1 = _ph      ; DO = T1       ; #clrt1
JSR push
T1 = _pl      ; DO = T1       ; #clrt1
JSR push
NOP           ; _pl = rst     ; #clrt1
NOP           ; _ph = AND     ; #end  // T1 & T2 = 0, because T2=0
// No extra cycle needed, _ph is not used in the next microinstruction
 
__code  "11101001"
__asm   PCHL
 
T1 = _l       ; NOP
NOP           ; _pl = T1
T1 = _h       ; NOP
NOP           ; _ph = T1        ; #end
 
 
__code  "11pp0101"  //Except for PUSH PSW
__asm   PUSH [p]
 
T1 = {p}0     ; DO = T1         ; #clrt1  // H first...
JSR push
T1 = {p}1     ; DO = T1         ; #clrt1  // ...L last
JSR push
NOP           ; NOP             ; #end
 
 
__code  "11110101"
__asm   PUSH PSW
 
T1 = _a       ; DO = T1         ; #clrt1
JSR push
NOP           ; DO = PSW        ; #clrt1
JSR push
NOP           ; NOP             ; #end
 
 
__code  "11pp0001"  //Except for POP PSW
__asm   POP [p]
 
JSR pop
NOP           ; {p}1 = T1
JSR pop
NOP           ; {p}0 = T1       ; #end
 
 
__code  "11110001"
__asm   POP PSW
 
JSR pop
NOP           ; _f = T1         ; #fp_rc //F<-(SP); F f-fs load automatically
JSR pop
NOP           ; _a = T1         ; #end
 
 
__code  "11100011"
__asm   XTHL
 
JSR pop
NOP           ; _z = T1
JSR pop
NOP           ; _w = T1
T1 = _h       ; DO = T1         ; #clrt1
JSR push
T1 = _l       ; DO = T1         ; #clrt1
JSR push
T1 = _z       ; NOP
NOP           ; _l = T1
T1 = _w       ; NOP
NOP           ; _h = T1         ; #end
 
 
__code  "11111001"
__asm   SPHL
 
T1 = _l       ; NOP
NOP           ; _sl = T1
T1 = _h       ; NOP
NOP           ; _sh = T1           ; #end
 
 
__code  "11111011"
__asm   EI
 
NOP           ; NOP                ; #ei, #end
 
 
__code  "11110011"
__asm   DI
 
NOP           ; NOP                ; #di, #end
 
 
__code  "11011011"
__asm   IN port
 
NOP           ; _w = T1             // _w = 0
JSR read_imm                        // T1 = port
NOP           ; _z = T1             // #ld_al reads from mux...
NOP           ; NOP
T1 = _z       ; NOP           ; #ld_al
T1 = _w       ; NOP           ; #ld_addr, #rd, #io
T1 = DI       ; _a = T1       ; #end
 
 
// Can be reduced to 11 states by removing 1st uinst
// Then, _b might be put on high addr byte as in the original...
__code  "11010011"
__asm   OUT port
 
 
NOP           ; _w = T1             // _w = 0, put on high byte of io address
JSR read_imm                        // T1 = port
NOP           ; _z = T1             // #ld_al reads from mux...
T1 = _a       ; DO = T1
T1 = _z       ; NOP           ; #ld_al
T1 = _w       ; NOP           ; #ld_addr, #wr, #io
NOP           ; NOP           ; #end
 
 
__code  "01110110"
__asm   HLT
//TODO doc: #halt has to be in the same cycle as #end
NOP           ; NOP           ; #halt, #end
 
 
 
 
//********************************************
 
// T1 = (HL)
 
:read_m
 
T1 = _l       ; NOP           ; #ld_al
T1 = _h       ; NOP           ; #ld_addr, #rd
T1 = DI       ; _x = T1       ; #ret
 
// (HL) = DO, does not return
// TODO extra uinst is for wait state, which is not implemented
 
:write_m
 
T1 = _l       ; NOP           ; #ld_al
T1 = _h       ; NOP           ; #ld_addr, #wr
NOP           ; NOP           ; #end
 
 
// T1 = (PC++), DO = T1
// T2 must be 0 on entry
:read_imm
 
T1 = _pl      ; _pl = ADC     ; #ld_al, #auxcy, #setacy
T1 = _ph      ; _ph = ADC     ; #ld_addr, #rd, #auxcy
T1 = DI       ; DO = T1       ; #ret
 
 
// T1 = (WZ)
 
:read_wz
 
T1 = _z       ; NOP           ; #ld_al
T1 = _w       ; NOP           ; #ld_addr, #rd
T1 = DI       ; NOP           ; #ret
 
 
// (WZ) = DO, does not return
// TODO extra uinst is for wait state, which is not implemented
 
:write_wz
 
T1 = _z       ; NOP           ; #ld_al
T1 = _w       ; NOP           ; #ld_addr, #wr
NOP           ; NOP           ; #end
 
// T1 = (RP)
 
:read_p
 
T1 = {p}1     ; NOP           ; #ld_al
T1 = {p}0     ; NOP           ; #ld_addr, #rd
T1 = DI       ; NOP           ; #ret
 
 
// (RP) = DO, does not return
// TODO extra uinst is for wait state, which is not implemented
 
:write_p
 
T1 = {p}1     ; NOP           ; #ld_al
T1 = {p}0     ; NOP           ; #ld_addr, #wr
NOP           ; NOP           ; #end
 
// WZ = imm16
 
:read_imm_wz
 
T1 = _pl      ; _pl = ADC     ; #ld_al, #auxcy, #setacy
T1 = _ph      ; _ph = ADC     ; #ld_addr, #rd, #auxcy
T1 = DI       ; _z = T1
T1 = _pl      ; _pl = ADC     ; #ld_al, #auxcy, #setacy
T1 = _ph      ; _ph = ADC     ; #ld_addr, #rd, #auxcy
T1 = DI       ; _w = T1       ; #ret
 
// push DO
// no wait cycle!
 
:push
T2 = _sl      ; _sl = SBB     ; #auxcy, #setacy
T2 = _sh      ; _sh = SBB     ; #auxcy
T1 = _sl                        ; NOP                                           ; #ld_al
T1 = _sh                        ; NOP                                           ; #ld_addr, #wr,
NOP           ; NOP           ; #ret   // extra line, flag clash
 
 
// POP T1
 
:pop
T1 = _sl      ; _sl = ADC     ; #ld_al, #auxcy, #setacy
T1 = _sh      ; _sh = ADC     ; #ld_addr, #rd, #auxcy
T1 = DI       ; NOP                                       ; #ret        // extra line, flag clash
 
 
// End of file

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[/] [light8080/] [trunk/] [ucode/] [light8080.m80] - Blame information for rev 49

Line No.	Rev	Author	Line
1	2	ja_rd	`////////////////////////////////////////////////////////////////////////////////`
2			`// LIGHT8080 CORE MICROCODE (V.1 November 1st 2007)`
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// NOTE: Except for bug fixing, there's no need to tinker with the microcode.`
5			`// Once the microcode table has been generated, this file is is not needed to`
6			`// synthesize or use the core.`
7			`////////////////////////////////////////////////////////////////////////////////`
8			`//`
9			`// ***** FORMAT AND OPERATION:`
10			`//`
11			`// operation 1 ; operation 2 ; flags`
12			`//`
13			`// Operation 1 sets up the ALU input registers; operation 2 takes the ALU result`
14			`// and writes it back somewhere; and the flags group all other microinstruction`
15			`// control signals.`
16			`//`
17	48	ja_rd	`// For any given microinstruction, operation 2 takes place in the cycle after`
18			`// operation 1. It happens concurrently with the next microinstruction's`
19			`// operation 1, so whenever a register is written to in an operation 2 it will`
20			`// NOT be available for the next microinstruction.`
21	2	ja_rd	`//`
22			`// In operation 1, you may load any one of T1 or T2 from the register bank or`
23			`// from DI which is simply the unregistered signal data_in.`
24			`//`
25			`// In operation 2, you specify the ALU operation and assign the ALU result to`
26			`// the register bank or the register DO, which feeds the signal data_out.`
27			`//`
28			`// You cannot address two different registers from the register bank in`
29			`// operations 1 and 2 (see the design notes on this).`
30			`//`
31			`// *** Some other elements found in the microcode source:`
32			`//`
33			`// labels: must be in a line by themselves, otherwise work like any assembler.`
34			`// __code pragmas: used by assembler to automatically generate the decode table.`
35			`// __asm pragmas: not used, but can be handy as a reference.`
36			`//`
37			`//`
38			`// ***** FLAGS:`
39			`//`
40			`// Note: '1st cycle' and '2nd cycle' denote both cycles of the present`
41			`// microinstruction (m.i.); cycle 2 of m.i. N overlaps cycle 1 of m.i. N+1.`
42			`//`
43			`// #ld_al : Load AL register with register bank output as read by operation 1.`
44			`// (used in memory and io access).`
45			`// #ld_addr : Load address register (H byte = register bank output as read by`
46			`// operation 1, L byte = AL).`
47			`// Activate vma signal for 1st cycle.`
48			`// #auxcy : Use aux carry instead of regular carry for this operation.`
49			`// #setacy : Set aux carry at the start of 1st cycle (used for ++).`
50			`// #end : Jump to microinstruction address 3 after the present m.i.`
51			`// #ret : Jump to address saved by the last JST or TJSR m.i.`
52			`// #rd : Activate rd signal for the 2nd cycle.`
53			`// #wr : Activate wr signal for the 2nd cycle.`
54	48	ja_rd	`// #fp_r : This microinstruction updates all PSW flags except for C.`
55			`// #fp_c : This microinstruction updates only the C flag in the PSW.`
56			`// #fp_rc : This microinstruction updates all the flags in the PSW.`
57	2	ja_rd	`// #clrt1 : Clear T1 at the end of 1st cycle.`
58			`// #io : Activate io signal for 1st cycle.`
59			`// #ei : Set interrupt enable register.`
60			`// #di : Reset interrupt enable register.`
61			`// #halt : Jump to microcode address 0x07 without saving return value.`
62			`//`
63			`////////////////////////////////////////////////////////////////////////////////`
64
65			`// RESET ucode: from 0 to 2, but uinst at address 0 is never executed`
66			`__reset`
67
68			`NOP ; NOP`
69	5	ja_rd	`NOP ; _pl = AND ; // T1 & T2 = 0x00`
70			`NOP ; _ph = AND ; // T1 & T2 = 0x00`
71	2	ja_rd
72			`// FETCH ucode: from 3 to 6`
73			`// (executed in INTA cycles too, with pc increment inhibited to preserve PC)`
74			`__fetch`
75
76			`T1 = _pl ; _pl = ADC ; #ld_al, #auxcy, #setacy`
77			`T1 = _ph ; _ph = ADC ; #ld_addr, #rd, #auxcy`
78			`NOP ; NOP ; #decode`
79
80			`// free uinst slot`
81			`NOP ; NOP ;`
82
83			`// HALT ucode: address 7`
84			`__halt`
85			`NOP ; NOP ; #halt, #end`
86
87
88			`// NOTE: ALU single_operand ops work on T1`
89			`// ALU 2-operands work with 'A' on T2 (e.g. SUB == T2 - T1)`
90
91
92			`__code "01dddsss"`
93			`__asm MOV {d},{s}`
94
95			`T1 = {s} ; NOP`
96			`NOP ; {d} = T1 ; #end`
97
98
99			`__code "01ddd110"`
100			`__asm MOV {d},M`
101
102			`JSR read_m ;`
103			`NOP ; {d} = T1 ; #end`
104
105
106			`__code "01110sss"`
107			`__asm MOV M,{s}`
108
109			`T1 = {s} ; DO = T1`
110			`JSR write_m // does not return`
111
112
113			`__code "00ddd110"`
114			`__asm MVI {d},#imm`
115
116			`JSR read_imm`
117			`NOP ; {d} = T1 ; #end`
118
119
120			`__code "00110110"`
121			`__asm MVI M,#imm`
122
123			`JSR read_imm`
124			`JSR write_m`
125
126
127			`__code "00pp0001"`
128			`__asm LXI [p]`
129
130			`JSR read_imm`
131			`NOP ; {p}1 = T1`
132			`JSR read_imm`
133			`NOP ; {p}0 = T1 ; #end`
134
135
136			`__code "00111010"`
137			`__asm LDA addr`
138
139			`JSR read_imm_wz`
140			`JSR read_wz`
141			`NOP ; _a = T1 ; #end`
142
143
144			`__code "00110010"`
145			`__asm STA addr`
146
147			`JSR read_imm_wz`
148			`T1 = _a ; DO = T1 ;`
149			`JSR write_wz //does not return`
150
151
152			`__code "00101010"`
153			`__asm LHLD`
154
155
156			`JSR read_imm_wz`
157			`T1 = _z ; _z = ADC ; #ld_al, #auxcy, #setacy // L = (WZ++)`
158			`T1 = _w ; _w = ADC ; #ld_addr, #rd, #auxcy`
159			`T1 = DI ; _l = T1`
160			`JSR read_wz // H = (WZ)`
161			`NOP ; _h = T1 ; #end`
162
163
164			`__code "00100010"`
165			`__asm SHLD`
166
167			`JSR read_imm_wz`
168			`T1 = _l ; DO = T1`
169			`T1 = _z ; _z = ADC ; #ld_al, #auxcy, #setacy`
170			`T1 = _w ; _w = ADC ; #ld_addr, #wr, #auxcy`
171			`T1 = _h ; DO = T1`
172			`JSR write_wz`
173
174
175			`__code "00pp1010"`
176			`__asm LDAX [p]`
177
178			`JSR read_p`
179			`NOP ; _a = T1 ; #end`
180
181
182			`__code "00pp0010"`
183			`__asm STAX [p]`
184
185			`T1 = _a ; DO = T1`
186			`JSR write_p`
187
188
189			`__code "11101011"`
190			`__asm XCHG`
191
192			`// 16 T cycles vs. 10 for the original 8080...`
193			`T1 = _d ; NOP`
194			`NOP ; _x = T1`
195			`T1 = _e ; NOP`
196			`NOP ; _y = T1`
197			`T1 = _h ; NOP`
198			`NOP ; _d = T1`
199			`T1 = _l ; NOP`
200			`NOP ; _e = T1`
201			`T1 = _x ; NOP`
202			`NOP ; _h = T1`
203			`T1 = _y ; NOP`
204			`NOP ; _l = T1 ; #end`
205
206
207			`__code "11000110"`
208			`__asm ADI #imm`
209
210			`JSR read_imm`
211			`T2 = _a ; _a = ADD ; #end, #fp_rc`
212
213			`__code "11001110"`
214			`__asm ACI #imm`
215
216			`JSR read_imm`
217			`T2 = _a ; _a = ADC ; #end, #fp_rc`
218
219			`__code "11010110"`
220			`__asm SUI #imm`
221
222			`JSR read_imm`
223			`T2 = _a ; _a = SUB ; #end, #fp_rc`
224
225			`__code "11011110"`
226			`__asm SBI #imm`
227
228			`JSR read_imm`
229			`T2 = _a ; _a = SBB ; #end, #fp_rc`
230
231
232			`__code "11100110"`
233			`__asm ANI #imm`
234
235			`JSR read_imm`
236			`T2 = _a ; _a = AND ; #end, #fp_rc`
237
238			`__code "11101110"`
239			`__asm XRI #imm`
240
241			`JSR read_imm`
242			`T2 = _a ; _a = XRL ; #end, #fp_rc`
243
244
245			`__code "11110110"`
246			`__asm ORI #imm`
247
248			`JSR read_imm`
249			`T2 = _a ; _a = ORL ; #end, #fp_rc`
250
251
252			`__code "11111110"`
253			`__asm CPI #imm`
254
255			`JSR read_imm`
256			`T2 = _a ; DO = SUB ; #end, #fp_rc`
257
258
259
260			`__code "10000sss"`
261			`__asm ADD {s}`
262
263			`T1 = {s} ; NOP`
264			`T2 = _a ; _a = ADD ; #end, #fp_rc`
265
266			`__code "10001sss"`
267			`__asm ADC {s}`
268
269			`T1 = {s} ; NOP`
270			`T2 = _a ; _a = ADC ; #end, #fp_rc`
271
272			`__code "10010sss"`
273			`__asm SUB {s}`
274
275			`T1 = {s} ; NOP`
276			`T2 = _a ; _a = SUB ; #end, #fp_rc`
277
278			`__code "10011sss"`
279			`__asm SBB {s}`
280
281			`T1 = {s} ; NOP`
282			`T2 = _a ; _a = SBB ; #end, #fp_rc`
283
284			`__code "10100sss"`
285			`__asm ANA {s}`
286
287			`T1 = {s} ; NOP`
288			`T2 = _a ; _a = AND ; #end, #fp_rc`
289
290			`__code "10101sss"`
291			`__asm XRA {s}`
292
293			`T1 = {s} ; NOP`
294			`T2 = _a ; _a = XRL ; #end, #fp_rc`
295
296			`__code "10110sss"`
297			`__asm ORA {s}`
298
299			`T1 = {s} ; NOP`
300			`T2 = _a ; _a = ORL ; #end, #fp_rc`
301
302			`__code "10111sss"`
303			`__asm CMP {s}`
304
305			`T1 = {s} ; NOP`
306			`T2 = _a ; DO = SUB ; #end, #fp_rc`
307
308
309			`__code "10000110"`
310			`__asm ADD M`
311
312			`JSR read_m`
313			`T2 = _a ; _a = ADD ; #end, #fp_rc`
314
315			`__code "10001110"`
316			`__asm ADC M`
317
318			`JSR read_m`
319			`T2 = _a ; _a = ADC ; #end, #fp_rc`
320
321			`__code "10010110"`
322			`__asm SUB M`
323
324			`JSR read_m`
325			`T2 = _a ; _a = SUB ; #end, #fp_rc`
326
327			`__code "10011110"`
328			`__asm SBB M`
329
330			`JSR read_m`
331			`T2 = _a ; _a = SBB ; #end, #fp_rc`
332
333			`__code "10100110"`
334			`__asm ANA M`
335
336			`JSR read_m`
337			`T2 = _a ; _a = AND ; #end, #fp_rc`
338
339			`__code "10101110"`
340			`__asm XRA M`
341
342			`JSR read_m`
343			`T2 = _a ; _a = XRL ; #end, #fp_rc`
344
345			`__code "10110110"`
346			`__asm ORA M`
347
348			`JSR read_m`
349			`T2 = _a ; _a = ORL ; #end, #fp_rc`
350
351
352			`__code "10111110"`
353			`__asm CMP M`
354
355			`JSR read_m`
356			`T2 = _a ; DO = SUB ; #end, #fp_rc`
357
358
359			`__code "00ddd100"`
360			`__asm INR {d}`
361
362			`T1 = {d} ; {d} = ADC ; #auxcy, #setacy, #fp_r`
363			`NOP ; NOP ; #end // extra line, flag clash`
364
365
366			`__code "00110100"`
367			`__asm INR M`
368
369			`JSR read_m`
370	5	ja_rd	`NOP ; DO = ADC ; #auxcy, #setacy, #fp_r`
371	2	ja_rd	`JSR write_m`
372
373
374			`__code "00ddd101"`
375			`__asm DCR {d}`
376
377			`T2 = {d} ; {d} = SBB ; #auxcy, #setacy, #fp_r`
378			`NOP ; NOP ; #end // extra line, flag clash`
379
380
381			`__code "00110101"`
382			`__asm DCR M`
383
384			`JSR read_m // T1 = _x = (HL); but we need it in T2!`
385			`NOP ; NOP ; #clrt1 // flag clash`
386			`T2 = _x ; DO = SBB ; #auxcy, #setacy, #fp_r`
387			`JSR write_m`
388
389
390			`__code "00pp0011"`
391			`__asm INX [p]`
392
393			`T1 = {p}1 ; {p}1 = ADC ; #auxcy, #setacy`
394			`T1 = {p}0 ; {p}0 = ADC ; #end, #auxcy`
395
396
397			`__code "00pp1011"`
398			`__asm DCX [p]`
399
400			`T2 = {p}1 ; {p}1 = SBB ; #auxcy, #setacy // T2 because SUB -> T2 - T1`
401			`T2 = {p}0 ; {p}0 = SBB ; #end, #auxcy`
402
403
404			`__code "00pp1001"`
405			`__asm DAD [p]`
406
407			`T2 = {p}1 ; NOP`
408			`T1 = _l ; _l = ADD ; #fp_c // we need this cy`
409			`T2 = {p}0 ; NOP ;`
410			`T1 = _h ; _h = ADC ; #end, #fp_c`
411
412
413			`__code "00100111"`
414			`__asm DAA`
415
416			`// DAA result is only valid after the 2nd cycle;`
417			`T1 = _a ; DO = DAA ; //DO value ignored`
418			`T1 = _a ; _a = DAA ; #end, #fp_rc`
419
420
421			`__code "00000111"`
422			`__asm RLC`
423
424			`T1 = _a ; _a = rla ; #end, #fp_c`
425
426
427			`__code "00001111"`
428			`__asm RRC`
429
430			`T1 = _a ; _a = rra ; #end, #fp_c`
431
432
433			`__code "00010111"`
434			`__asm RAL`
435
436			`T1 = _a ; _a = rlca ; #end, #fp_c`
437
438
439			`__code "00011111"`
440			`__asm RAR`
441
442			`T1 = _a ; _a = rrca ; #end, #fp_c`
443
444
445			`__code "00101111"`
446			`__asm CMA`
447
448			`T1 = _a ; _a = NOT ; #end`
449
450
451			`__code "00111111"`
452			`__asm CMC`
453
454			`NOP ; cpc ; #end, #fp_c`
455
456
457			`__code "00110111"`
458			`__asm STC`
459
460			`NOP ; sec ; #end, #fp_c`
461
462
463			`__code "11000011"`
464			`__asm JMP addr`
465
466			`JSR read_imm_wz`
467			`:jmp_addr`
468			`T1 = _z ; NOP`
469			`NOP ; _pl = T1`
470			`T1 = _w ; NOP`
471			`NOP ; _ph = T1 ; #end`
472
473
474
475			`__code "00000000"`
476			`__asm NOP`
477
478			`NOP ; NOP ; #end`
479
480
481			`__code "11ccc010"`
482			`__asm {JZ,JNZ,JC,JNC,JPO,JPE,JP,JM} addr`
483
484			`JSR read_imm_wz`
485			`TJSR jmp_addr // TJSR does the JSR or does #end the instruction.`
486
487
488			`__code "11001101"`
489			`__asm CALL addr`
490
491			`//:call_addr`
492			`JSR read_imm_wz`
493			`:call_addr //@@`
494			`T1 = _ph ; DO = T1 ; #clrt1`
495			`JSR push`
496			`T1 = _pl ; DO = T1 ; #clrt1`
497			`JSR push`
498			`T1 = _z ; NOP`
499			`NOP ; _pl = T1`
500			`T1 = _w ; NOP`
501			`NOP ; _ph = T1 ; #end`
502
503
504
505			`__code "11ccc100"`
506			`__asm {CZ,CNZ,CC,CNC,CPO,CPE,CP,CM} addr`
507
508			`JSR read_imm_wz // skip next 2 bytes`
509			`TJSR call_addr // TJSR does the JSR or does #end the instruction.`
510
511
512			`__code "11001001"`
513			`__asm RET`
514
515			`:ret`
516			`JSR pop`
517			`NOP ; _pl = T1`
518			`JSR pop`
519			`NOP ; _ph = T1 ; #end`
520
521
522			`__code "11ccc000"`
523			`__asm {RZ,RNZ,RC,RNC,RPO,RPE,RP,RM}`
524
525
526			`TJSR ret // TJSR does the JSR or does #end the instruction.`
527
528
529
530			`__code "11nnn111"`
531			`__asm {RST 0h,RST 8h,RST 10h,RST 18h,RST 20h,RST 28h,RST 30h,RST 38h}`
532
533			`T1 = _ph ; DO = T1 ; #clrt1`
534			`JSR push`
535			`T1 = _pl ; DO = T1 ; #clrt1`
536			`JSR push`
537			`NOP ; _pl = rst ; #clrt1`
538			`NOP ; _ph = AND ; #end // T1 & T2 = 0, because T2=0`
539	48	ja_rd	`// No extra cycle needed, _ph is not used in the next microinstruction`
540	2	ja_rd
541			`__code "11101001"`
542			`__asm PCHL`
543
544			`T1 = _l ; NOP`
545			`NOP ; _pl = T1`
546			`T1 = _h ; NOP`
547			`NOP ; _ph = T1 ; #end`
548
549
550			`__code "11pp0101" //Except for PUSH PSW`
551			`__asm PUSH [p]`
552
553			`T1 = {p}0 ; DO = T1 ; #clrt1 // H first...`
554			`JSR push`
555			`T1 = {p}1 ; DO = T1 ; #clrt1 // ...L last`
556			`JSR push`
557			`NOP ; NOP ; #end`
558
559
560			`__code "11110101"`
561			`__asm PUSH PSW`
562
563			`T1 = _a ; DO = T1 ; #clrt1`
564			`JSR push`
565			`NOP ; DO = PSW ; #clrt1`
566			`JSR push`
567			`NOP ; NOP ; #end`
568
569
570			`__code "11pp0001" //Except for POP PSW`
571			`__asm POP [p]`
572
573			`JSR pop`
574			`NOP ; {p}1 = T1`
575			`JSR pop`
576			`NOP ; {p}0 = T1 ; #end`
577
578
579			`__code "11110001"`
580			`__asm POP PSW`
581
582			`JSR pop`
583			`NOP ; _f = T1 ; #fp_rc //F<-(SP); F f-fs load automatically`
584			`JSR pop`
585			`NOP ; _a = T1 ; #end`
586
587
588			`__code "11100011"`
589			`__asm XTHL`
590
591			`JSR pop`
592			`NOP ; _z = T1`
593			`JSR pop`
594			`NOP ; _w = T1`
595			`T1 = _h ; DO = T1 ; #clrt1`
596			`JSR push`
597			`T1 = _l ; DO = T1 ; #clrt1`
598			`JSR push`
599			`T1 = _z ; NOP`
600			`NOP ; _l = T1`
601			`T1 = _w ; NOP`
602			`NOP ; _h = T1 ; #end`
603
604
605			`__code "11111001"`
606			`__asm SPHL`
607
608			`T1 = _l ; NOP`
609			`NOP ; _sl = T1`
610			`T1 = _h ; NOP`
611			`NOP ; _sh = T1 ; #end`
612
613
614			`__code "11111011"`
615			`__asm EI`
616
617			`NOP ; NOP ; #ei, #end`
618
619
620			`__code "11110011"`
621			`__asm DI`
622
623			`NOP ; NOP ; #di, #end`
624
625
626			`__code "11011011"`
627			`__asm IN port`
628
629			`NOP ; _w = T1 // _w = 0`
630			`JSR read_imm // T1 = port`
631			`NOP ; _z = T1 // #ld_al reads from mux...`
632			`NOP ; NOP`
633			`T1 = _z ; NOP ; #ld_al`
634			`T1 = _w ; NOP ; #ld_addr, #rd, #io`
635			`T1 = DI ; _a = T1 ; #end`
636
637
638			`// Can be reduced to 11 states by removing 1st uinst`
639			`// Then, _b might be put on high addr byte as in the original...`
640			`__code "11010011"`
641			`__asm OUT port`
642
643
644			`NOP ; _w = T1 // _w = 0, put on high byte of io address`
645			`JSR read_imm // T1 = port`
646			`NOP ; _z = T1 // #ld_al reads from mux...`
647			`T1 = _a ; DO = T1`
648			`T1 = _z ; NOP ; #ld_al`
649			`T1 = _w ; NOP ; #ld_addr, #wr, #io`
650			`NOP ; NOP ; #end`
651
652
653			`__code "01110110"`
654			`__asm HLT`
655			`//TODO doc: #halt has to be in the same cycle as #end`
656			`NOP ; NOP ; #halt, #end`
657
658
659
660
661			`//********************************************`
662
663			`// T1 = (HL)`
664
665			`:read_m`
666
667			`T1 = _l ; NOP ; #ld_al`
668			`T1 = _h ; NOP ; #ld_addr, #rd`
669			`T1 = DI ; _x = T1 ; #ret`
670
671			`// (HL) = DO, does not return`
672			`// TODO extra uinst is for wait state, which is not implemented`
673
674			`:write_m`
675
676			`T1 = _l ; NOP ; #ld_al`
677			`T1 = _h ; NOP ; #ld_addr, #wr`
678			`NOP ; NOP ; #end`
679
680
681			`// T1 = (PC++), DO = T1`
682			`// T2 must be 0 on entry`
683			`:read_imm`
684
685			`T1 = _pl ; _pl = ADC ; #ld_al, #auxcy, #setacy`
686			`T1 = _ph ; _ph = ADC ; #ld_addr, #rd, #auxcy`
687			`T1 = DI ; DO = T1 ; #ret`
688
689
690			`// T1 = (WZ)`
691
692			`:read_wz`
693
694			`T1 = _z ; NOP ; #ld_al`
695			`T1 = _w ; NOP ; #ld_addr, #rd`
696			`T1 = DI ; NOP ; #ret`
697
698
699			`// (WZ) = DO, does not return`
700			`// TODO extra uinst is for wait state, which is not implemented`
701
702			`:write_wz`
703
704			`T1 = _z ; NOP ; #ld_al`
705			`T1 = _w ; NOP ; #ld_addr, #wr`
706			`NOP ; NOP ; #end`
707
708			`// T1 = (RP)`
709
710			`:read_p`
711
712			`T1 = {p}1 ; NOP ; #ld_al`
713			`T1 = {p}0 ; NOP ; #ld_addr, #rd`
714			`T1 = DI ; NOP ; #ret`
715
716
717			`// (RP) = DO, does not return`
718			`// TODO extra uinst is for wait state, which is not implemented`
719
720			`:write_p`
721
722			`T1 = {p}1 ; NOP ; #ld_al`
723			`T1 = {p}0 ; NOP ; #ld_addr, #wr`
724			`NOP ; NOP ; #end`
725
726			`// WZ = imm16`
727
728			`:read_imm_wz`
729
730			`T1 = _pl ; _pl = ADC ; #ld_al, #auxcy, #setacy`
731			`T1 = _ph ; _ph = ADC ; #ld_addr, #rd, #auxcy`
732			`T1 = DI ; _z = T1`
733			`T1 = _pl ; _pl = ADC ; #ld_al, #auxcy, #setacy`
734			`T1 = _ph ; _ph = ADC ; #ld_addr, #rd, #auxcy`
735			`T1 = DI ; _w = T1 ; #ret`
736
737			`// push DO`
738			`// no wait cycle!`
739
740			`:push`
741			`T2 = _sl ; _sl = SBB ; #auxcy, #setacy`
742			`T2 = _sh ; _sh = SBB ; #auxcy`
743			`T1 = _sl ; NOP ; #ld_al`
744			`T1 = _sh ; NOP ; #ld_addr, #wr,`
745			`NOP ; NOP ; #ret // extra line, flag clash`
746
747
748			`// POP T1`
749
750			`:pop`
751			`T1 = _sl ; _sl = ADC ; #ld_al, #auxcy, #setacy`
752			`T1 = _sh ; _sh = ADC ; #ld_addr, #rd, #auxcy`
753			`T1 = DI ; NOP ; #ret // extra line, flag clash`
754
755
756			`// End of file`