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[/] [light8080/] [trunk/] [ucode/] [light8080.m80] - Blame information for rev 71

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1 2 ja_rd
////////////////////////////////////////////////////////////////////////////////
2 64 ja_rd
// LIGHT8080 CORE MICROCODE (V.2 February 12th 2012)
3 2 ja_rd
////////////////////////////////////////////////////////////////////////////////
4
// NOTE: Except for bug fixing, there's no need to tinker with the microcode.
5
// Once the microcode table has been generated, this file is is not needed to
6
// synthesize or use the core.
7
////////////////////////////////////////////////////////////////////////////////
8
//
9
// ***** FORMAT AND OPERATION:
10
//
11
// operation 1 ; operation 2 ; flags
12
//
13
// Operation 1 sets up the ALU input registers; operation 2 takes the ALU result
14
// and writes it back somewhere; and the flags group all other microinstruction
15
// control signals.
16
//
17 48 ja_rd
// For any given microinstruction, operation 2 takes place in the cycle after
18
// operation 1. It happens concurrently with the next microinstruction's
19
// operation 1, so whenever a register is written to in an operation 2 it will
20
// NOT be available for the next microinstruction.
21 2 ja_rd
//
22
// In operation 1, you may load any one of T1 or T2 from the register bank or
23
// from DI which is simply the unregistered signal data_in.
24
//
25
// In operation 2, you specify the ALU operation and assign the ALU result to
26
// the register bank or the register DO, which feeds the signal data_out.
27
//
28
// You cannot address two different registers from the register bank in
29
// operations 1 and 2 (see the design notes on this).
30
//
31
// *** Some other elements found in the microcode source:
32
//
33
// labels: must be in a line by themselves, otherwise work like any assembler.
34
// __code pragmas: used by assembler to automatically generate the decode table.
35
// __asm pragmas: not used, but can be handy as a reference.
36
//
37
//
38
// ***** FLAGS:
39
//
40
// Note: '1st cycle' and '2nd cycle' denote both cycles of the present
41
// microinstruction (m.i.); cycle 2 of m.i. N overlaps cycle 1 of m.i. N+1.
42
//
43
// #ld_al :   Load AL register with register bank output as read by operation 1.
44
//            (used in memory and io access).
45
// #ld_addr : Load address register (H byte = register bank output as read by
46
//            operation 1, L byte = AL).
47
//            Activate vma signal for 1st cycle.
48
// #auxcy :   Use aux carry instead of regular carry for this operation.
49
// #setacy :  Set aux carry at the start of 1st cycle (used for ++).
50
// #end :     Jump to microinstruction address 3 after the present m.i.
51
// #ret :     Jump to address saved by the last JST or TJSR m.i.
52
// #rd :      Activate rd signal for the 2nd cycle.
53
// #wr :      Activate wr signal for the 2nd cycle.
54 48 ja_rd
// #fp_r :    This microinstruction updates all PSW flags except for C.
55
// #fp_c :    This microinstruction updates only the C flag in the PSW.
56
// #fp_rc :   This microinstruction updates all the flags in the PSW.
57 2 ja_rd
// #clrt1 :   Clear T1 at the end of 1st cycle.
58
// #io :      Activate io signal for 1st cycle.
59
// #ei :      Set interrupt enable register.
60
// #di :      Reset interrupt enable register.
61
// #halt :    Jump to microcode address 0x07 without saving return value.
62
//
63
////////////////////////////////////////////////////////////////////////////////
64 64 ja_rd
// V.1 November 1st 2007    -- Original version
65
// V.2 February 12th 2012   -- Fixed CY/AC clear bug with clr_acy flag
66
////////////////////////////////////////////////////////////////////////////////
67 2 ja_rd
 
68 64 ja_rd
 
69 2 ja_rd
// RESET ucode: from 0 to 2, but uinst at address 0 is never executed
70
__reset
71
 
72
NOP           ; NOP
73 58 ja_rd
NOP           ; _pl = AND     ;                 // T1 & T2 = 0x00
74
NOP           ; _ph = AND     ;                 // T1 & T2 = 0x00
75 2 ja_rd
 
76
// FETCH ucode: from 3 to 6
77
// (executed in INTA cycles too, with pc increment inhibited to preserve PC)
78
__fetch
79
 
80
T1 = _pl      ; _pl = ADC     ; #ld_al, #auxcy, #setacy
81
T1 = _ph      ; _ph = ADC     ; #ld_addr, #rd, #auxcy
82
NOP           ; NOP           ; #decode
83
 
84
// free uinst slot
85
NOP           ; NOP           ;
86
 
87
// HALT ucode: address 7
88
__halt
89
NOP           ; NOP           ; #halt, #end
90
 
91
 
92
// NOTE: ALU single_operand ops work on T1
93
// ALU 2-operands work with 'A' on T2 (e.g. SUB == T2 - T1)
94
 
95
 
96
__code  "01dddsss"
97
__asm   MOV {d},{s}
98
 
99
T1 = {s}      ; NOP
100
NOP           ; {d} = T1      ; #end
101
 
102
 
103
__code  "01ddd110"
104
__asm   MOV {d},M
105
 
106 58 ja_rd
JSR read_m    ;
107 2 ja_rd
NOP           ; {d} = T1      ; #end
108
 
109
 
110
__code  "01110sss"
111
__asm   MOV M,{s}
112
 
113
T1 = {s}      ; DO = T1
114
JSR write_m                   // does not return
115
 
116
 
117
__code  "00ddd110"
118
__asm   MVI {d},#imm
119
 
120
JSR read_imm
121
NOP           ; {d} = T1      ; #end
122
 
123
 
124
__code  "00110110"
125
__asm   MVI M,#imm
126
 
127
JSR read_imm
128
JSR write_m
129
 
130
 
131
__code  "00pp0001"
132
__asm   LXI [p]
133
 
134
JSR read_imm
135
NOP           ; {p}1 = T1
136
JSR read_imm
137
NOP           ; {p}0 = T1     ; #end
138
 
139
 
140
__code  "00111010"
141
__asm   LDA addr
142
 
143
JSR read_imm_wz
144
JSR read_wz
145
NOP           ; _a = T1       ; #end
146
 
147
 
148
__code  "00110010"
149
__asm   STA addr
150
 
151
JSR read_imm_wz
152
T1 = _a       ; DO = T1       ;
153
JSR write_wz                    //does not return
154
 
155
 
156
__code  "00101010"
157
__asm   LHLD
158
 
159
 
160
JSR read_imm_wz
161
T1 = _z       ; _z = ADC      ; #ld_al, #auxcy, #setacy // L = (WZ++)
162
T1 = _w       ; _w = ADC      ; #ld_addr, #rd, #auxcy
163
T1 = DI       ; _l = T1
164
JSR read_wz                                             // H = (WZ)
165
NOP           ; _h = T1       ; #end
166
 
167
 
168
__code  "00100010"
169
__asm   SHLD
170
 
171
JSR read_imm_wz
172
T1 = _l       ; DO = T1
173
T1 = _z       ; _z = ADC      ; #ld_al, #auxcy, #setacy
174
T1 = _w       ; _w = ADC      ; #ld_addr, #wr, #auxcy
175
T1 = _h       ; DO = T1
176
JSR write_wz
177
 
178
 
179
__code  "00pp1010"
180
__asm   LDAX [p]
181
 
182
JSR read_p
183
NOP           ; _a = T1       ; #end
184
 
185
 
186
__code  "00pp0010"
187
__asm   STAX [p]
188
 
189
T1 = _a       ; DO = T1
190
JSR write_p
191
 
192
 
193
__code  "11101011"
194
__asm   XCHG
195
 
196
// 16 T cycles vs. 10 for the original 8080...
197
T1 = _d       ; NOP
198
NOP           ; _x = T1
199
T1 = _e       ; NOP
200
NOP           ; _y = T1
201
T1 = _h       ; NOP
202
NOP           ; _d = T1
203
T1 = _l       ; NOP
204
NOP           ; _e = T1
205
T1 = _x       ; NOP
206
NOP           ; _h = T1
207
T1 = _y       ; NOP
208
NOP           ; _l = T1         ; #end
209
 
210
 
211
__code  "11000110"
212
__asm   ADI #imm
213
 
214
JSR read_imm
215
T2 = _a       ; _a = ADD      ; #end, #fp_rc
216
 
217
__code  "11001110"
218
__asm   ACI #imm
219
 
220
JSR read_imm
221
T2 = _a       ; _a = ADC      ; #end, #fp_rc
222
 
223
__code  "11010110"
224
__asm   SUI #imm
225
 
226
JSR read_imm
227
T2 = _a       ; _a = SUB      ; #end, #fp_rc
228
 
229
__code  "11011110"
230
__asm   SBI #imm
231
 
232
JSR read_imm
233
T2 = _a       ; _a = SBB      ; #end, #fp_rc
234
 
235
 
236
__code  "11100110"
237
__asm   ANI #imm
238
 
239
JSR read_imm
240 64 ja_rd
T2 = _a       ; _a = AND      ; #end, #fp_rc, #clr_acy
241 2 ja_rd
 
242
__code  "11101110"
243
__asm   XRI #imm
244
 
245
JSR read_imm
246 64 ja_rd
T2 = _a       ; _a = XRL      ; #end, #fp_rc, #clr_acy
247 2 ja_rd
 
248
 
249
__code  "11110110"
250
__asm   ORI #imm
251
 
252
JSR read_imm
253 64 ja_rd
T2 = _a       ; _a = ORL      ; #end, #fp_rc, #clr_acy
254 2 ja_rd
 
255
 
256
__code  "11111110"
257
__asm   CPI #imm
258
 
259
JSR read_imm
260
T2 = _a       ; DO = SUB      ; #end, #fp_rc
261
 
262
 
263
 
264
__code  "10000sss"
265
__asm   ADD {s}
266
 
267
T1 = {s}      ; NOP
268
T2 = _a       ; _a = ADD      ; #end, #fp_rc
269
 
270
__code  "10001sss"
271
__asm   ADC {s}
272
 
273
T1 = {s}      ; NOP
274
T2 = _a       ; _a = ADC      ; #end, #fp_rc
275
 
276
__code  "10010sss"
277
__asm   SUB {s}
278
 
279
T1 = {s}      ; NOP
280
T2 = _a       ; _a = SUB      ; #end, #fp_rc
281
 
282
__code  "10011sss"
283
__asm   SBB {s}
284
 
285
T1 = {s}      ; NOP
286
T2 = _a       ; _a = SBB      ; #end, #fp_rc
287
 
288
__code  "10100sss"
289
__asm   ANA {s}
290
 
291
T1 = {s}      ; NOP
292 64 ja_rd
T2 = _a       ; _a = AND      ; #end, #fp_rc, #clr_acy
293 2 ja_rd
 
294
__code  "10101sss"
295
__asm   XRA {s}
296
 
297
T1 = {s}      ; NOP
298 64 ja_rd
T2 = _a       ; _a = XRL      ; #end, #fp_rc, #clr_acy
299 2 ja_rd
 
300
__code  "10110sss"
301
__asm   ORA {s}
302
 
303
T1 = {s}      ; NOP
304 64 ja_rd
T2 = _a       ; _a = ORL      ; #end, #fp_rc, #clr_acy
305 2 ja_rd
 
306
__code  "10111sss"
307
__asm   CMP {s}
308
 
309
T1 = {s}      ; NOP
310
T2 = _a       ; DO = SUB      ; #end, #fp_rc
311
 
312
 
313
__code  "10000110"
314
__asm   ADD M
315
 
316
JSR read_m
317
T2 = _a       ; _a = ADD      ; #end, #fp_rc
318
 
319
__code  "10001110"
320
__asm   ADC M
321
 
322
JSR read_m
323
T2 = _a       ; _a = ADC      ; #end, #fp_rc
324
 
325
__code  "10010110"
326
__asm   SUB M
327
 
328
JSR read_m
329
T2 = _a       ; _a = SUB      ; #end, #fp_rc
330
 
331
__code  "10011110"
332
__asm   SBB M
333
 
334
JSR read_m
335
T2 = _a       ; _a = SBB      ; #end, #fp_rc
336
 
337
__code  "10100110"
338
__asm   ANA M
339
 
340
JSR read_m
341 64 ja_rd
T2 = _a       ; _a = AND      ; #end, #fp_rc, #clr_acy
342 2 ja_rd
 
343
__code  "10101110"
344
__asm   XRA M
345
 
346
JSR read_m
347 64 ja_rd
T2 = _a       ; _a = XRL      ; #end, #fp_rc, #clr_acy
348 2 ja_rd
 
349
__code  "10110110"
350
__asm   ORA M
351
 
352
JSR read_m
353 64 ja_rd
T2 = _a       ; _a = ORL      ; #end, #fp_rc, #clr_acy
354 2 ja_rd
 
355
 
356
__code  "10111110"
357
__asm   CMP M
358
 
359
JSR read_m
360
T2 = _a       ; DO = SUB      ; #end, #fp_rc
361
 
362
 
363
__code  "00ddd100"
364
__asm   INR {d}
365
 
366
T1 = {d}      ; {d} = ADC     ; #auxcy, #setacy, #fp_r
367
NOP           ; NOP           ; #end  // extra line, flag clash
368
 
369
 
370
__code  "00110100"
371
__asm   INR M
372
 
373
JSR read_m
374 5 ja_rd
NOP           ; DO = ADC      ; #auxcy, #setacy, #fp_r
375 2 ja_rd
JSR write_m
376
 
377
 
378
__code  "00ddd101"
379
__asm   DCR {d}
380
 
381
T2 = {d}      ; {d} = SBB     ; #auxcy, #setacy, #fp_r
382
NOP           ; NOP           ; #end   // extra line, flag clash
383
 
384
 
385
__code  "00110101"
386
__asm   DCR M
387
 
388
JSR read_m // T1 = _x = (HL); but we need it in T2!
389
NOP           ; NOP           ; #clrt1 // flag clash
390
T2 = _x       ; DO = SBB      ; #auxcy, #setacy, #fp_r
391
JSR write_m
392
 
393
 
394
__code  "00pp0011"
395
__asm   INX [p]
396
 
397
T1 = {p}1     ; {p}1 = ADC      ; #auxcy, #setacy
398
T1 = {p}0     ; {p}0 = ADC      ; #end, #auxcy
399
 
400
 
401
__code  "00pp1011"
402
__asm   DCX [p]
403
 
404
T2 = {p}1     ; {p}1 = SBB      ; #auxcy, #setacy  // T2 because SUB -> T2 - T1
405
T2 = {p}0     ; {p}0 = SBB      ; #end, #auxcy
406
 
407
 
408
__code  "00pp1001"
409
__asm   DAD [p]
410
 
411
T2 = {p}1     ; NOP
412
T1 = _l       ; _l = ADD      ; #fp_c // we need this cy
413
T2 = {p}0     ; NOP           ;
414
T1 = _h       ; _h = ADC      ; #end, #fp_c
415
 
416
 
417
__code  "00100111"
418
__asm   DAA
419
 
420
// DAA result is only valid after the 2nd cycle;
421
T1 = _a       ; DO = DAA        ; //DO value ignored
422
T1 = _a       ; _a = DAA        ; #end, #fp_rc
423
 
424
 
425
__code  "00000111"
426
__asm   RLC
427
 
428
T1 = _a       ; _a = rla       ; #end, #fp_c
429
 
430
 
431
__code  "00001111"
432
__asm   RRC
433
 
434
T1 = _a       ; _a = rra       ; #end, #fp_c
435
 
436
 
437
__code  "00010111"
438
__asm   RAL
439
 
440
T1 = _a       ; _a = rlca      ; #end, #fp_c
441
 
442
 
443
__code  "00011111"
444
__asm   RAR
445
 
446
T1 = _a       ; _a = rrca      ; #end, #fp_c
447
 
448
 
449
__code  "00101111"
450
__asm   CMA
451
 
452
T1 = _a       ; _a = NOT        ; #end
453
 
454
 
455
__code  "00111111"
456
__asm   CMC
457
 
458
NOP           ; cpc              ; #end, #fp_c
459
 
460
 
461
__code  "00110111"
462
__asm   STC
463
 
464
NOP           ; sec              ; #end, #fp_c
465
 
466
 
467
__code  "11000011"
468
__asm   JMP addr
469
 
470
JSR read_imm_wz
471
:jmp_addr
472
T1 = _z       ; NOP
473
NOP           ; _pl = T1
474
T1 = _w       ; NOP
475
NOP           ; _ph = T1      ; #end
476
 
477
 
478
 
479
__code  "00000000"
480
__asm   NOP
481
 
482
NOP           ; NOP           ; #end
483
 
484
 
485
__code  "11ccc010"
486
__asm   {JZ,JNZ,JC,JNC,JPO,JPE,JP,JM} addr
487
 
488
JSR read_imm_wz
489
TJSR jmp_addr           // TJSR does the JSR or does #end the instruction.
490
 
491
 
492
__code  "11001101"
493
__asm   CALL addr
494
 
495
//:call_addr
496
JSR read_imm_wz
497
:call_addr //@@
498
T1 = _ph      ; DO = T1         ; #clrt1
499
JSR push
500
T1 = _pl      ; DO = T1         ; #clrt1
501
JSR push
502
T1 = _z       ; NOP
503
NOP           ; _pl = T1
504
T1 = _w       ; NOP
505
NOP           ; _ph = T1        ; #end
506
 
507
 
508
 
509
__code  "11ccc100"
510
__asm   {CZ,CNZ,CC,CNC,CPO,CPE,CP,CM} addr
511
 
512
JSR read_imm_wz     // skip next 2 bytes
513
TJSR call_addr      // TJSR does the JSR or does #end the instruction.
514
 
515
 
516
__code  "11001001"
517
__asm   RET
518
 
519
:ret
520
JSR pop
521
NOP           ; _pl = T1
522
JSR pop
523
NOP           ; _ph = T1        ; #end
524
 
525
 
526
__code  "11ccc000"
527
__asm   {RZ,RNZ,RC,RNC,RPO,RPE,RP,RM}
528
 
529
 
530
TJSR ret      // TJSR does the JSR or does #end the instruction.
531
 
532
 
533
 
534
__code  "11nnn111"
535
__asm   {RST 0h,RST 8h,RST 10h,RST 18h,RST 20h,RST 28h,RST 30h,RST 38h}
536
 
537
T1 = _ph      ; DO = T1       ; #clrt1
538
JSR push
539
T1 = _pl      ; DO = T1       ; #clrt1
540
JSR push
541
NOP           ; _pl = rst     ; #clrt1
542
NOP           ; _ph = AND     ; #end  // T1 & T2 = 0, because T2=0
543 48 ja_rd
// No extra cycle needed, _ph is not used in the next microinstruction
544 2 ja_rd
 
545
__code  "11101001"
546
__asm   PCHL
547
 
548
T1 = _l       ; NOP
549
NOP           ; _pl = T1
550
T1 = _h       ; NOP
551
NOP           ; _ph = T1        ; #end
552
 
553
 
554
__code  "11pp0101"  //Except for PUSH PSW
555
__asm   PUSH [p]
556
 
557
T1 = {p}0     ; DO = T1         ; #clrt1  // H first...
558
JSR push
559
T1 = {p}1     ; DO = T1         ; #clrt1  // ...L last
560
JSR push
561
NOP           ; NOP             ; #end
562
 
563
 
564
__code  "11110101"
565
__asm   PUSH PSW
566
 
567
T1 = _a       ; DO = T1         ; #clrt1
568
JSR push
569
NOP           ; DO = PSW        ; #clrt1
570
JSR push
571
NOP           ; NOP             ; #end
572
 
573
 
574
__code  "11pp0001"  //Except for POP PSW
575
__asm   POP [p]
576
 
577
JSR pop
578
NOP           ; {p}1 = T1
579
JSR pop
580
NOP           ; {p}0 = T1       ; #end
581
 
582
 
583
__code  "11110001"
584
__asm   POP PSW
585
 
586
JSR pop
587
NOP           ; _f = T1         ; #fp_rc //F<-(SP); F f-fs load automatically
588
JSR pop
589
NOP           ; _a = T1         ; #end
590
 
591
 
592
__code  "11100011"
593
__asm   XTHL
594
 
595
JSR pop
596
NOP           ; _z = T1
597
JSR pop
598
NOP           ; _w = T1
599
T1 = _h       ; DO = T1         ; #clrt1
600
JSR push
601
T1 = _l       ; DO = T1         ; #clrt1
602
JSR push
603
T1 = _z       ; NOP
604
NOP           ; _l = T1
605
T1 = _w       ; NOP
606
NOP           ; _h = T1         ; #end
607
 
608
 
609
__code  "11111001"
610
__asm   SPHL
611
 
612
T1 = _l       ; NOP
613
NOP           ; _sl = T1
614
T1 = _h       ; NOP
615
NOP           ; _sh = T1           ; #end
616
 
617
 
618
__code  "11111011"
619
__asm   EI
620
 
621
NOP           ; NOP                ; #ei, #end
622
 
623
 
624
__code  "11110011"
625
__asm   DI
626
 
627
NOP           ; NOP                ; #di, #end
628
 
629
 
630
__code  "11011011"
631
__asm   IN port
632
 
633
NOP           ; _w = T1             // _w = 0
634
JSR read_imm                        // T1 = port
635
NOP           ; _z = T1             // #ld_al reads from mux...
636
NOP           ; NOP
637
T1 = _z       ; NOP           ; #ld_al
638
T1 = _w       ; NOP           ; #ld_addr, #rd, #io
639
T1 = DI       ; _a = T1       ; #end
640
 
641
 
642
// Can be reduced to 11 states by removing 1st uinst
643
// Then, _b might be put on high addr byte as in the original...
644
__code  "11010011"
645
__asm   OUT port
646
 
647
 
648
NOP           ; _w = T1             // _w = 0, put on high byte of io address
649
JSR read_imm                        // T1 = port
650
NOP           ; _z = T1             // #ld_al reads from mux...
651
T1 = _a       ; DO = T1
652
T1 = _z       ; NOP           ; #ld_al
653
T1 = _w       ; NOP           ; #ld_addr, #wr, #io
654
NOP           ; NOP           ; #end
655
 
656
 
657
__code  "01110110"
658
__asm   HLT
659
//TODO doc: #halt has to be in the same cycle as #end
660
NOP           ; NOP           ; #halt, #end
661
 
662
 
663
 
664
 
665
//********************************************
666
 
667
// T1 = (HL)
668
 
669
:read_m
670
 
671
T1 = _l       ; NOP           ; #ld_al
672
T1 = _h       ; NOP           ; #ld_addr, #rd
673
T1 = DI       ; _x = T1       ; #ret
674
 
675
// (HL) = DO, does not return
676
// TODO extra uinst is for wait state, which is not implemented
677
 
678
:write_m
679
 
680
T1 = _l       ; NOP           ; #ld_al
681
T1 = _h       ; NOP           ; #ld_addr, #wr
682
NOP           ; NOP           ; #end
683
 
684
 
685
// T1 = (PC++), DO = T1
686
// T2 must be 0 on entry
687
:read_imm
688
 
689
T1 = _pl      ; _pl = ADC     ; #ld_al, #auxcy, #setacy
690
T1 = _ph      ; _ph = ADC     ; #ld_addr, #rd, #auxcy
691
T1 = DI       ; DO = T1       ; #ret
692
 
693
 
694
// T1 = (WZ)
695
 
696
:read_wz
697
 
698
T1 = _z       ; NOP           ; #ld_al
699
T1 = _w       ; NOP           ; #ld_addr, #rd
700
T1 = DI       ; NOP           ; #ret
701
 
702
 
703
// (WZ) = DO, does not return
704
// TODO extra uinst is for wait state, which is not implemented
705
 
706
:write_wz
707
 
708
T1 = _z       ; NOP           ; #ld_al
709
T1 = _w       ; NOP           ; #ld_addr, #wr
710
NOP           ; NOP           ; #end
711
 
712
// T1 = (RP)
713
 
714
:read_p
715
 
716
T1 = {p}1     ; NOP           ; #ld_al
717
T1 = {p}0     ; NOP           ; #ld_addr, #rd
718
T1 = DI       ; NOP           ; #ret
719
 
720
 
721
// (RP) = DO, does not return
722
// TODO extra uinst is for wait state, which is not implemented
723
 
724
:write_p
725
 
726
T1 = {p}1     ; NOP           ; #ld_al
727
T1 = {p}0     ; NOP           ; #ld_addr, #wr
728
NOP           ; NOP           ; #end
729
 
730
// WZ = imm16
731
 
732
:read_imm_wz
733
 
734
T1 = _pl      ; _pl = ADC     ; #ld_al, #auxcy, #setacy
735
T1 = _ph      ; _ph = ADC     ; #ld_addr, #rd, #auxcy
736
T1 = DI       ; _z = T1
737
T1 = _pl      ; _pl = ADC     ; #ld_al, #auxcy, #setacy
738
T1 = _ph      ; _ph = ADC     ; #ld_addr, #rd, #auxcy
739
T1 = DI       ; _w = T1       ; #ret
740
 
741
// push DO
742
// no wait cycle!
743
 
744
:push
745
T2 = _sl      ; _sl = SBB     ; #auxcy, #setacy
746
T2 = _sh      ; _sh = SBB     ; #auxcy
747 58 ja_rd
T1 = _sl      ; NOP           ; #ld_al
748
T1 = _sh      ; NOP           ; #ld_addr, #wr,
749 2 ja_rd
NOP           ; NOP           ; #ret   // extra line, flag clash
750
 
751
 
752
// POP T1
753
 
754
:pop
755
T1 = _sl      ; _sl = ADC     ; #ld_al, #auxcy, #setacy
756
T1 = _sh      ; _sh = ADC     ; #ld_addr, #rd, #auxcy
757 58 ja_rd
T1 = DI       ; NOP           ; #ret  // extra line, flag clash
758 2 ja_rd
 
759
 
760
// End of file

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