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[/] [light8080/] [trunk/] [verilog/] [rtl/] [uart.v] - Blame information for rev 79

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//---------------------------------------------------------------------------------------
// uart top level module  
//
//---------------------------------------------------------------------------------------
 
module uart
(
        clock, reset,
        serIn, serOut,
        txData, txValid,
        txBusy, txDone,
        rxData, rxValid,
        baudDiv
);
//---------------------------------------------------------------------------------------
// module interfaces 
// global signals 
input                   clock;          // global clock input 
input                   reset;          // global reset input 
// uart serial signals 
input                   serIn;          // serial data input 
output                  serOut;         // serial data output 
// transmit and receive internal interface signals 
input   [7:0]    txData;         // data byte to transmit 
input                   txValid;        // asserted to indicate that there is a new data byte for transmission 
output                  txBusy;         // signs that transmitter is busy 
output                  txDone;         // transmitter done pulse 
output  [7:0]    rxData;         // data byte received 
output                  rxValid;        // signs that a new byte was received 
// baud rate configuration register 
input   [15:0]   baudDiv;        // baud rate setting register = round(clock_freq/baud_rate/16) - 1
 
//---------------------------------------------------------------------------------------
// internal declarations 
// registered output 
reg serOut, txBusy, txDone, rxValid;
reg [7:0] rxData;
 
// internals 
reg [8:0] txShiftReg;
reg [7:0] rxShiftReg;
reg [3:0] txBaudCnt, txBitCnt, rxBaudCnt, rxBitCnt;
reg [15:0] baudCount;
reg baudCE16, sserIn, rxBusy;
 
//---------------------------------------------------------------------------------------
// module implementation 
// transmitter control process 
always @ (posedge reset or posedge clock)
begin
        if (reset)
        begin
                txBusy <= 1'b0;
                txDone <= 1'b0;
                txShiftReg <= 9'b0;
                serOut <= 1'b1;
                txBaudCnt <= 4'b0;
                txBitCnt <= 4'b0;
        end
        else if (!txBusy)
        begin
                // check if transmitter operation should start 
                if (txValid)
                begin
                        // register the data shift register and assert the transmitter busy flag 
                        txShiftReg <= {txData, 1'b0};
                        txBusy <= 1'b1;
                end
 
                // defaults 
                serOut <= 1'b1;
                txDone <= 1'b0;
                txBaudCnt <= 4'b0;
                txBitCnt <= 4'b0;
        end
        else if (baudCE16)
        begin
                // check if next bit should be sent out 
                if (txBaudCnt == 4'b0)
                begin
                        //check if this is the last bit 
                        if (txBitCnt == 4'd10)
                        begin
                                // clear the busy flag and pulse done flag 
                                txBusy <= 1'b0;
                                txDone <= 1'b1;
                        end
 
                        // update the bit counter 
                        txBitCnt <= txBitCnt + 4'd1;
 
                        // update the serial output and shift register 
                        serOut <= txShiftReg[0];
                        txShiftReg <= {1'b1, txShiftReg[8:1]};
                end
 
                // update the baud clock counter 
                txBaudCnt <= txBaudCnt + 4'd1;
        end
end
 
// receiver control process 
always @ (posedge reset or posedge clock)
begin
        if (reset)
        begin
                rxBusy <= 1'b0;
                rxShiftReg <= 8'b0;
                rxBaudCnt <= 4'b0;
                rxBitCnt <= 4'b0;
                rxData <= 8'b0;
                rxValid <= 1'b0;
        end
        else if (!rxBusy)
        begin
                // check start bit 
                if (!sserIn && baudCE16)
                begin
                        // check if the serial input is zero for 8 baudCE16 cycles 
                        if (rxBaudCnt == 4'd7)
                        begin
                                // sign that receiver is busy and clear the bit counter 
                                rxBusy <= 1'b1;
                                rxBaudCnt <= 4'b0;
                        end
                        else
                                rxBaudCnt <= rxBaudCnt + 4'd1;
                end
 
                // defaults 
                rxBitCnt <= 4'b0;
                rxValid <= 1'b0;
        end
        else if (baudCE16)
        begin
                // check if bit should be sampled 
                if (rxBaudCnt == 4'd15)
                begin
                        // update the input shift register and bit counter 
                        rxShiftReg <= {sserIn, rxShiftReg[7:1]};
                        rxBitCnt <= rxBitCnt + 4'd1;
 
                        // check if this is the last data bit 
                        if (rxBitCnt == 4'd8)
                        begin
                                // sample the received data byte 
                                rxData <= rxShiftReg;
                                rxValid <= 1'b1;
 
                                // clear receiver busy flag 
                                rxBusy <= 1'b0;
                        end
                end
 
                // update the baud clock counter 
                rxBaudCnt <= rxBaudCnt + 4'd1;
        end
end
 
// sample serial input 
always @ (posedge reset or posedge clock)
begin
        if (reset)
                sserIn <= 1'b0;
        else
                sserIn <= serIn;
end
 
// baud rate clock generator 
always @ (posedge reset or posedge clock)
begin
        if (reset)
        begin
                baudCount <= 16'b0;
                baudCE16 <= 1'b0;
        end
        else if (baudCount == baudDiv)
        begin
                // clear the divider counter and pulse the clock enable signal 
                baudCount <= 16'b0;
                baudCE16 <= 1'b1;
        end
        else
        begin
                // update the clock divider counter and clear the 
                baudCount <= baudCount + 16'd1;
                baudCE16 <= 1'b0;
        end
end
 
endmodule
//---------------------------------------------------------------------------------------
//                                              Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	65	motilito	`//---------------------------------------------------------------------------------------`
2			`// uart top level module`
3			`//`
4			`//---------------------------------------------------------------------------------------`
5
6			`module uart`
7			`(`
8			`clock, reset,`
9			`serIn, serOut,`
10			`txData, txValid,`
11			`txBusy, txDone,`
12			`rxData, rxValid,`
13			`baudDiv`
14			`);`
15			`//---------------------------------------------------------------------------------------`
16			`// module interfaces`
17			`// global signals`
18			`input clock; // global clock input`
19			`input reset; // global reset input`
20			`// uart serial signals`
21			`input serIn; // serial data input`
22			`output serOut; // serial data output`
23			`// transmit and receive internal interface signals`
24			`input [7:0] txData; // data byte to transmit`
25			`input txValid; // asserted to indicate that there is a new data byte for transmission`
26			`output txBusy; // signs that transmitter is busy`
27			`output txDone; // transmitter done pulse`
28			`output [7:0] rxData; // data byte received`
29			`output rxValid; // signs that a new byte was received`
30			`// baud rate configuration register`
31			`input [15:0] baudDiv; // baud rate setting register = round(clock_freq/baud_rate/16) - 1`
32
33			`//---------------------------------------------------------------------------------------`
34			`// internal declarations`
35			`// registered output`
36			`reg serOut, txBusy, txDone, rxValid;`
37			`reg [7:0] rxData;`
38
39			`// internals`
40			`reg [8:0] txShiftReg;`
41			`reg [7:0] rxShiftReg;`
42			`reg [3:0] txBaudCnt, txBitCnt, rxBaudCnt, rxBitCnt;`
43			`reg [15:0] baudCount;`
44			`reg baudCE16, sserIn, rxBusy;`
45
46			`//---------------------------------------------------------------------------------------`
47			`// module implementation`
48			`// transmitter control process`
49			`always @ (posedge reset or posedge clock)`
50			`begin`
51			`if (reset)`
52			`begin`
53			`txBusy <= 1'b0;`
54			`txDone <= 1'b0;`
55			`txShiftReg <= 9'b0;`
56			`serOut <= 1'b1;`
57			`txBaudCnt <= 4'b0;`
58			`txBitCnt <= 4'b0;`
59			`end`
60			`else if (!txBusy)`
61			`begin`
62			`// check if transmitter operation should start`
63			`if (txValid)`
64			`begin`
65			`// register the data shift register and assert the transmitter busy flag`
66			`txShiftReg <= {txData, 1'b0};`
67			`txBusy <= 1'b1;`
68			`end`
69
70			`// defaults`
71			`serOut <= 1'b1;`
72			`txDone <= 1'b0;`
73			`txBaudCnt <= 4'b0;`
74			`txBitCnt <= 4'b0;`
75			`end`
76			`else if (baudCE16)`
77			`begin`
78			`// check if next bit should be sent out`
79			`if (txBaudCnt == 4'b0)`
80			`begin`
81			`//check if this is the last bit`
82			`if (txBitCnt == 4'd10)`
83			`begin`
84			`// clear the busy flag and pulse done flag`
85			`txBusy <= 1'b0;`
86			`txDone <= 1'b1;`
87			`end`
88
89			`// update the bit counter`
90			`txBitCnt <= txBitCnt + 4'd1;`
91
92			`// update the serial output and shift register`
93			`serOut <= txShiftReg[0];`
94			`txShiftReg <= {1'b1, txShiftReg[8:1]};`
95			`end`
96
97			`// update the baud clock counter`
98			`txBaudCnt <= txBaudCnt + 4'd1;`
99			`end`
100			`end`
101
102			`// receiver control process`
103			`always @ (posedge reset or posedge clock)`
104			`begin`
105			`if (reset)`
106			`begin`
107			`rxBusy <= 1'b0;`
108			`rxShiftReg <= 8'b0;`
109			`rxBaudCnt <= 4'b0;`
110			`rxBitCnt <= 4'b0;`
111			`rxData <= 8'b0;`
112			`rxValid <= 1'b0;`
113			`end`
114			`else if (!rxBusy)`
115			`begin`
116			`// check start bit`
117			`if (!sserIn && baudCE16)`
118			`begin`
119			`// check if the serial input is zero for 8 baudCE16 cycles`
120			`if (rxBaudCnt == 4'd7)`
121			`begin`
122			`// sign that receiver is busy and clear the bit counter`
123			`rxBusy <= 1'b1;`
124			`rxBaudCnt <= 4'b0;`
125			`end`
126			`else`
127			`rxBaudCnt <= rxBaudCnt + 4'd1;`
128			`end`
129
130			`// defaults`
131			`rxBitCnt <= 4'b0;`
132			`rxValid <= 1'b0;`
133			`end`
134			`else if (baudCE16)`
135			`begin`
136			`// check if bit should be sampled`
137			`if (rxBaudCnt == 4'd15)`
138			`begin`
139			`// update the input shift register and bit counter`
140			`rxShiftReg <= {sserIn, rxShiftReg[7:1]};`
141			`rxBitCnt <= rxBitCnt + 4'd1;`
142
143			`// check if this is the last data bit`
144			`if (rxBitCnt == 4'd8)`
145			`begin`
146			`// sample the received data byte`
147			`rxData <= rxShiftReg;`
148			`rxValid <= 1'b1;`
149
150			`// clear receiver busy flag`
151			`rxBusy <= 1'b0;`
152			`end`
153			`end`
154
155			`// update the baud clock counter`
156			`rxBaudCnt <= rxBaudCnt + 4'd1;`
157			`end`
158			`end`
159
160			`// sample serial input`
161			`always @ (posedge reset or posedge clock)`
162			`begin`
163			`if (reset)`
164			`sserIn <= 1'b0;`
165			`else`
166			`sserIn <= serIn;`
167			`end`
168
169			`// baud rate clock generator`
170			`always @ (posedge reset or posedge clock)`
171			`begin`
172			`if (reset)`
173			`begin`
174			`baudCount <= 16'b0;`
175			`baudCE16 <= 1'b0;`
176			`end`
177			`else if (baudCount == baudDiv)`
178			`begin`
179			`// clear the divider counter and pulse the clock enable signal`
180			`baudCount <= 16'b0;`
181			`baudCE16 <= 1'b1;`
182			`end`
183			`else`
184			`begin`
185			`// update the clock divider counter and clear the`
186			`baudCount <= baudCount + 16'd1;`
187			`baudCE16 <= 1'b0;`
188			`end`
189			`end`
190
191			`endmodule`
192			`//---------------------------------------------------------------------------------------`
193			`// Th.. Th.. Th.. Thats all folks !!!`
194			`//---------------------------------------------------------------------------------------`

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[/] [light8080/] [trunk/] [verilog/] [rtl/] [uart.v] - Blame information for rev 79