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[/] [light8080/] [trunk/] [verilog/] [syn/] [altera_c2/] [l80soc.qsf] - Blame information for rev 85

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2010 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors.  Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
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# Date created = 15:57:36  February 17, 2012
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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#               l80soc_assignment_defaults.qdf
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#    If this file doesn't exist, see file:
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#               assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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#    file is updated automatically by the Quartus II software
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#    and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C8Q208C8
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set_global_assignment -name TOP_LEVEL_ENTITY l80soc
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:57:36  FEBRUARY 17, 2012"
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set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
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set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\cores\\rs/
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set_global_assignment -name SEARCH_PATH "c:\\altera\\81\\ip\\altera\\reed_solomon\\lib/"
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set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog/
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name FMAX_REQUIREMENT "15 ns"
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set_global_assignment -name VERILOG_FILE ../../rtl/l80soc.v
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set_global_assignment -name VERILOG_FILE ../../rtl/intr_ctrl.v
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set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
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set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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