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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='4'><B>xilinx_s3 Project Status (03/03/2012 - 19:50:25)</B></TD></TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
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<TD>xilinx_s3.ise</TD>
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<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
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<TD>Placed and Routed</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
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<TD>l80soc</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
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<TD>
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No Errors</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
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<TD>xc3s200-4ft256</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
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<TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/*.xmsgs'>26 Warnings</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.4</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
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<TD>
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<A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.unroutes'>All Signals Completely Routed</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
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<TD>Balanced</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
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<TD>
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<A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
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<TD>Xilinx Default (unlocked)</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
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<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0) <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
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</TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
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<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
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<TD ALIGN=RIGHT>233</TD>
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<TD ALIGN=RIGHT>3,840</TD>
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<TD ALIGN=RIGHT>6%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
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<TD ALIGN=RIGHT>377</TD>
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<TD ALIGN=RIGHT>3,840</TD>
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<TD ALIGN=RIGHT>9%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
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<TD ALIGN=RIGHT>253</TD>
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<TD ALIGN=RIGHT>1,920</TD>
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<TD ALIGN=RIGHT>13%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing only related logic</TD>
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<TD ALIGN=RIGHT>253</TD>
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<TD ALIGN=RIGHT>253</TD>
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<TD ALIGN=RIGHT>100%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing unrelated logic</TD>
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<TD ALIGN=RIGHT>0</TD>
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<TD ALIGN=RIGHT>253</TD>
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<TD ALIGN=RIGHT>0%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number of 4 input LUTs</B></TD>
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<TD ALIGN=RIGHT>378</TD>
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<TD ALIGN=RIGHT>3,840</TD>
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<TD ALIGN=RIGHT>9%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
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<TD ALIGN=RIGHT>361</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as a route-thru</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used for Dual Port RAMs</TD>
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<TD ALIGN=RIGHT>16</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
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<TD ALIGN=RIGHT>24</TD>
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<TD ALIGN=RIGHT>173</TD>
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<TD ALIGN=RIGHT>13%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16s</TD>
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<TD ALIGN=RIGHT>3</TD>
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<TD ALIGN=RIGHT>12</TD>
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<TD ALIGN=RIGHT>25%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD>
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<TD ALIGN=RIGHT>1</TD>
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<TD ALIGN=RIGHT>8</TD>
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<TD ALIGN=RIGHT>12%</TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
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<TD ALIGN=RIGHT>3.36</TD>
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<TD> </TD>
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<TD> </TD>
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<TD COLSPAN='2'> </TD>
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</TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
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<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
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<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
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<TD COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
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<A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.unroutes'>All Signals Completely Routed</A></TD>
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<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
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<TD COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
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<TD>
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<A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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<TD BGCOLOR='#FFFF99'><B> </B></TD>
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<TD COLSPAN='2'> </TD>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
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<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:01 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>24 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/xst.xmsgs'>9 Infos</A></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:06 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:13 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/map.xmsgs'>2 Infos</A></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:23 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
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<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\l80soc.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat Mar 3 19:50:25 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Projects/WiCores/light8080/dev/trunk/verilog/syn/xilinx_s3\_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
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<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
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</TABLE>
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<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
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</TABLE>
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<br><center><b>Date Generated:</b> 03/03/2012 - 19:50:25</center>
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