| 1 |
2 |
ja_rd |
--##############################################################################
|
| 2 |
10 |
ja_rd |
-- light8080 : Intel 8080 binary compatible core
|
| 3 |
2 |
ja_rd |
--##############################################################################
|
| 4 |
64 |
ja_rd |
-- v1.3 (12 FEB 2012) Fix: General solution to AND, OR, XOR clearing CY,ACY.
|
| 5 |
54 |
ja_rd |
-- v1.2 (08 jul 2010) Fix: XOR operations were not clearing CY,ACY.
|
| 6 |
10 |
ja_rd |
-- v1.1 (20 sep 2008) Microcode bug in INR fixed.
|
| 7 |
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-- v1.0 (05 nov 2007) First release. Jose A. Ruiz.
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| 8 |
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--
|
| 9 |
19 |
ja_rd |
-- This file and all the light8080 project files are freeware (See COPYING.TXT)
|
| 10 |
3 |
ja_rd |
--##############################################################################
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| 11 |
19 |
ja_rd |
-- (See timing diagrams at bottom of file. More comprehensive explainations can
|
| 12 |
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|
-- be found in the design notes)
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| 13 |
10 |
ja_rd |
--##############################################################################
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| 14 |
2 |
ja_rd |
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| 15 |
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library IEEE;
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| 16 |
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use IEEE.STD_LOGIC_1164.ALL;
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| 17 |
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use IEEE.STD_LOGIC_ARITH.ALL;
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| 18 |
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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| 19 |
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| 20 |
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--##############################################################################
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| 21 |
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-- vma : enable a memory or io r/w access.
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| 22 |
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-- io : access in progress is io (and not memory)
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| 23 |
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-- rd : read memory or io
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| 24 |
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-- wr : write memory or io
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| 25 |
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-- data_out : data output
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| 26 |
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-- addr_out : memory and io address
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| 27 |
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-- data_in : data input
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| 28 |
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-- halt : halt status (1 when in halt state)
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| 29 |
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-- inte : interrupt status (1 when enabled)
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| 30 |
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-- intr : interrupt request
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| 31 |
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-- inta : interrupt acknowledge
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| 32 |
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-- reset : synchronous reset
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| 33 |
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-- clk : clock
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| 34 |
19 |
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--
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| 35 |
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-- (see timing diagrams at bottom of file)
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| 36 |
2 |
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--##############################################################################
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| 37 |
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entity light8080 is
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| 38 |
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Port (
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| 39 |
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addr_out : out std_logic_vector(15 downto 0);
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| 40 |
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| 41 |
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inta : out std_logic;
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| 42 |
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inte : out std_logic;
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| 43 |
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halt : out std_logic;
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| 44 |
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intr : in std_logic;
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| 45 |
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| 46 |
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vma : out std_logic;
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| 47 |
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io : out std_logic;
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| 48 |
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rd : out std_logic;
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| 49 |
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wr : out std_logic;
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| 50 |
19 |
ja_rd |
fetch : out std_logic;
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| 51 |
2 |
ja_rd |
data_in : in std_logic_vector(7 downto 0);
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| 52 |
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data_out : out std_logic_vector(7 downto 0);
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| 53 |
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| 54 |
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clk : in std_logic;
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| 55 |
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reset : in std_logic );
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| 56 |
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end light8080;
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| 57 |
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| 58 |
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--##############################################################################
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| 59 |
10 |
ja_rd |
-- All memory and io accesses are synchronous (rising clock edge). Signal vma
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| 60 |
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-- works as the master memory and io synchronous enable. More specifically:
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| 61 |
2 |
ja_rd |
--
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| 62 |
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-- * All memory/io control signals (io,rd,wr) are valid only when vma is
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| 63 |
64 |
ja_rd |
-- high. They never activate when vma is inactive.
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| 64 |
2 |
ja_rd |
-- * Signals data_out and address are only valid when vma='1'. The high
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| 65 |
10 |
ja_rd |
-- address byte is 0x00 for all io accesses.
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| 66 |
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-- * Signal data_in should be valid by the end of the cycle after vma='1',
|
| 67 |
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-- data is clocked in by the rising clock edge.
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| 68 |
2 |
ja_rd |
--
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| 69 |
10 |
ja_rd |
-- All signals are assumed to be synchronous to the master clock. Prevention of
|
| 70 |
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-- metastability, if necessary, is up to you.
|
| 71 |
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--
|
| 72 |
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-- Signal reset needs to be active for just 1 clock cycle (it is sampled on a
|
| 73 |
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-- positive clock edge and is subject to setup and hold times).
|
| 74 |
4 |
ja_rd |
-- Once reset is deasserted, the first fetch at address 0x0000 will happen 4
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| 75 |
2 |
ja_rd |
-- cycles later.
|
| 76 |
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--
|
| 77 |
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-- Signal intr is sampled on all positive clock edges. If asserted when inte is
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| 78 |
4 |
ja_rd |
-- high, interrupts will be disabled, inta will be asserted high and a fetch
|
| 79 |
39 |
ja_rd |
-- cycle will occur immediately after the current instruction ends execution,
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| 80 |
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-- except if intr was asserted at the last cycle of an instruction. In that case
|
| 81 |
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-- it will be honored after the next instruction ends.
|
| 82 |
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-- The fetched instruction will be executed normally, except that PC will not
|
| 83 |
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-- be valid in any subsequent fetch cycles of the same instruction,
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| 84 |
10 |
ja_rd |
-- and will not be incremented (In practice, the same as the original 8080).
|
| 85 |
39 |
ja_rd |
-- inta will remain high for the duration of the fetched instruction, including
|
| 86 |
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-- fetch and execution time (in the original 8080 it was high only for the
|
| 87 |
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-- opcode fetch cycle).
|
| 88 |
10 |
ja_rd |
-- PC will not be autoincremented while inta is high, but it can be explicitly
|
| 89 |
39 |
ja_rd |
-- modified (e.g. RST, CALL, etc.). Again, the same as the original.
|
| 90 |
2 |
ja_rd |
-- Interrupts will be disabled upon assertion of inta, and remain disabled
|
| 91 |
4 |
ja_rd |
-- until explicitly enabled by the program (as in the original).
|
| 92 |
39 |
ja_rd |
-- If intr is asserted when inte is low, the interrupt will not be attended but
|
| 93 |
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-- it will be registered in an int_pending flag, so it will be honored when
|
| 94 |
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-- interrupts are enabled.
|
| 95 |
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--
|
| 96 |
2 |
ja_rd |
--
|
| 97 |
4 |
ja_rd |
-- The above means that any instruction can be supplied in an inta cycle,
|
| 98 |
10 |
ja_rd |
-- either single byte or multibyte. See the design notes.
|
| 99 |
2 |
ja_rd |
--##############################################################################
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| 100 |
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| 101 |
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architecture microcoded of light8080 is
|
| 102 |
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|
|
| 103 |
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-- addr_low: low byte of address
|
| 104 |
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signal addr_low : std_logic_vector(7 downto 0);
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| 105 |
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-- IR: instruction register. some bits left unused.
|
| 106 |
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signal IR : std_logic_vector(7 downto 0);
|
| 107 |
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-- s_field: IR field, sss source reg code
|
| 108 |
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signal s_field : std_logic_vector(2 downto 0);
|
| 109 |
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-- d_field: IR field, ddd destination reg code
|
| 110 |
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signal d_field : std_logic_vector(2 downto 0);
|
| 111 |
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-- p_field: IR field, pp 16-bit reg pair code
|
| 112 |
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signal p_field : std_logic_vector(1 downto 0);
|
| 113 |
|
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-- rbh: 1 when p_field=11, used in reg bank addressing for 'special' regs
|
| 114 |
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signal rbh : std_logic; -- 1 when P=11 (special case)
|
| 115 |
|
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-- alu_op: uinst field, ALU operation code
|
| 116 |
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signal alu_op : std_logic_vector(3 downto 0);
|
| 117 |
|
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-- DI: data input to ALU block from data_in, unregistered
|
| 118 |
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signal DI : std_logic_vector(7 downto 0);
|
| 119 |
|
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-- uc_addr: microcode (ucode) address
|
| 120 |
|
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signal uc_addr : std_logic_vector(7 downto 0);
|
| 121 |
|
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-- next_uc_addr: computed next microcode address (uaddr++/jump/ret/fetch)
|
| 122 |
|
|
signal next_uc_addr : std_logic_vector(8 downto 0);
|
| 123 |
|
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-- uc_jmp_addr: uinst field, absolute ucode jump address
|
| 124 |
|
|
signal uc_jmp_addr : std_logic_vector(7 downto 0);
|
| 125 |
|
|
-- uc_ret_address: ucode return address saved in previous jump
|
| 126 |
|
|
signal uc_ret_addr : std_logic_vector(7 downto 0);
|
| 127 |
|
|
-- addr_plus_1: uaddr + 1
|
| 128 |
|
|
signal addr_plus_1 : std_logic_vector(7 downto 0);
|
| 129 |
|
|
-- do_reset: reset, delayed 1 cycle -- used to reset the microcode sequencer
|
| 130 |
|
|
signal do_reset : std_logic;
|
| 131 |
|
|
|
| 132 |
|
|
-- uc_flags1: uinst field, encoded flag of group 1 (see ucode file)
|
| 133 |
|
|
signal uc_flags1 : std_logic_vector(2 downto 0);
|
| 134 |
|
|
-- uc_flags2: uinst field, encoded flag of group 2 (see ucode file)
|
| 135 |
|
|
signal uc_flags2 : std_logic_vector(2 downto 0);
|
| 136 |
|
|
-- uc_addr_sel: selection of next uc_addr, composition of 4 flags
|
| 137 |
|
|
signal uc_addr_sel : std_logic_vector(3 downto 0);
|
| 138 |
|
|
-- NOTE: see microcode file for information on flags
|
| 139 |
|
|
signal uc_jsr : std_logic; -- uinst field, decoded 'jsr' flag
|
| 140 |
|
|
signal uc_tjsr : std_logic; -- uinst field, decoded 'tjsr' flag
|
| 141 |
|
|
signal uc_decode : std_logic; -- uinst field, decoded 'decode' flag
|
| 142 |
|
|
signal uc_end : std_logic; -- uinst field, decoded 'end' flag
|
| 143 |
|
|
signal condition_reg :std_logic; -- registered tjst condition
|
| 144 |
|
|
-- condition: tjsr condition (computed ccc condition from '80 instructions)
|
| 145 |
|
|
signal condition : std_logic;
|
| 146 |
|
|
-- condition_sel: IR field, ccc condition code
|
| 147 |
|
|
signal condition_sel :std_logic_vector(2 downto 0);
|
| 148 |
|
|
signal uc_do_jmp : std_logic; -- uinst jump (jsr/tjsr) flag, pipelined
|
| 149 |
|
|
signal uc_do_ret : std_logic; -- ret flag, pipelined
|
| 150 |
|
|
signal uc_halt_flag : std_logic; -- uinst field, decoded 'halt' flag
|
| 151 |
|
|
signal uc_halt : std_logic; -- halt command
|
| 152 |
|
|
signal halt_reg : std_logic; -- halt status reg, output as 'halt' signal
|
| 153 |
|
|
signal uc_ei : std_logic; -- uinst field, decoded 'ei' flag
|
| 154 |
49 |
ja_rd |
signal uc_di : std_logic; -- uinst field, decoded 'di' flag
|
| 155 |
2 |
ja_rd |
signal inte_reg : std_logic; -- inte status reg, output as 'inte' signal
|
| 156 |
|
|
signal int_pending : std_logic; -- intr requested, inta not active yet
|
| 157 |
|
|
signal inta_reg : std_logic; -- inta status reg, output as 'inta'
|
| 158 |
|
|
signal clr_t1 : std_logic; -- uinst field, explicitly erase T1
|
| 159 |
|
|
signal do_clr_t1 : std_logic; -- clr_t1 pipelined
|
| 160 |
|
|
signal clr_t2 : std_logic; -- uinst field, explicitly erase T2
|
| 161 |
|
|
signal do_clr_t2 : std_logic; -- clr_t2 pipelined
|
| 162 |
|
|
signal ucode : std_logic_vector(31 downto 0); -- microcode word
|
| 163 |
|
|
signal ucode_field2 : std_logic_vector(24 downto 0); -- pipelined microcode
|
| 164 |
|
|
|
| 165 |
49 |
ja_rd |
-- used to delay interrup enable for one entire instruction after EI
|
| 166 |
|
|
signal delayed_ei : std_logic;
|
| 167 |
|
|
|
| 168 |
2 |
ja_rd |
-- microcode ROM : see design notes and microcode source file
|
| 169 |
|
|
type t_rom is array (0 to 511) of std_logic_vector(31 downto 0);
|
| 170 |
|
|
|
| 171 |
|
|
signal rom : t_rom := (
|
| 172 |
|
|
"00000000000000000000000000000000", -- 000
|
| 173 |
|
|
"00000000000001001000000001000100", -- 001
|
| 174 |
|
|
"00000000000001000000000001000100", -- 002
|
| 175 |
|
|
"10111101101001001000000001001101", -- 003
|
| 176 |
|
|
"10110110101001000000000001001101", -- 004
|
| 177 |
|
|
"00100000000000000000000000000000", -- 005
|
| 178 |
|
|
"00000000000000000000000000000000", -- 006
|
| 179 |
|
|
"11100100000000000000000000000000", -- 007
|
| 180 |
|
|
"00000000101010000000000000000000", -- 008
|
| 181 |
|
|
"00000100000100000000000001010111", -- 009
|
| 182 |
|
|
"00001000000000000000110000011001", -- 00a
|
| 183 |
|
|
"00000100000100000000000001010111", -- 00b
|
| 184 |
|
|
"00000000101010000000000010010111", -- 00c
|
| 185 |
|
|
"00001000000000000000110000011100", -- 00d
|
| 186 |
|
|
"00001000000000000000110000011111", -- 00e
|
| 187 |
|
|
"00000100000100000000000001010111", -- 00f
|
| 188 |
|
|
"00001000000000000000110000011111", -- 010
|
| 189 |
|
|
"00001000000000000000110000011100", -- 011
|
| 190 |
|
|
"00001000000000000000110000011111", -- 012
|
| 191 |
|
|
"00000000000110001000000001010111", -- 013
|
| 192 |
|
|
"00001000000000000000110000011111", -- 014
|
| 193 |
|
|
"00000100000110000000000001010111", -- 015
|
| 194 |
|
|
"00001000000000000000110000101110", -- 016
|
| 195 |
|
|
"00001000000000000000110000100010", -- 017
|
| 196 |
|
|
"00000100000000111000000001010111", -- 018
|
| 197 |
|
|
"00001000000000000000110000101110", -- 019
|
| 198 |
|
|
"00000000101000111000000010010111", -- 01a
|
| 199 |
|
|
"00001000000000000000110000100101", -- 01b
|
| 200 |
|
|
"00001000000000000000110000101110", -- 01c
|
| 201 |
|
|
"10111101101001100000000001001101", -- 01d
|
| 202 |
|
|
"10110110101001101000000001001101", -- 01e
|
| 203 |
|
|
"00000000100000101000000001010111", -- 01f
|
| 204 |
|
|
"00001000000000000000110000100010", -- 020
|
| 205 |
|
|
"00000100000000100000000001010111", -- 021
|
| 206 |
|
|
"00001000000000000000110000101110", -- 022
|
| 207 |
|
|
"00000000101000101000000010010111", -- 023
|
| 208 |
|
|
"10111101101001100000000001001101", -- 024
|
| 209 |
|
|
"10111010101001101000000001001101", -- 025
|
| 210 |
|
|
"00000000101000100000000010010111", -- 026
|
| 211 |
|
|
"00001000000000000000110000100101", -- 027
|
| 212 |
|
|
"00001000000000000000110000101000", -- 028
|
| 213 |
|
|
"00000100000000111000000001010111", -- 029
|
| 214 |
|
|
"00000000101000111000000010010111", -- 02a
|
| 215 |
|
|
"00001000000000000000110000101011", -- 02b
|
| 216 |
|
|
"00000000101000010000000000000000", -- 02c
|
| 217 |
|
|
"00000000000001010000000001010111", -- 02d
|
| 218 |
|
|
"00000000101000011000000000000000", -- 02e
|
| 219 |
|
|
"00000000000001011000000001010111", -- 02f
|
| 220 |
|
|
"00000000101000100000000000000000", -- 030
|
| 221 |
|
|
"00000000000000010000000001010111", -- 031
|
| 222 |
|
|
"00000000101000101000000000000000", -- 032
|
| 223 |
|
|
"00000000000000011000000001010111", -- 033
|
| 224 |
|
|
"00000000101001010000000000000000", -- 034
|
| 225 |
|
|
"00000000000000100000000001010111", -- 035
|
| 226 |
|
|
"00000000101001011000000000000000", -- 036
|
| 227 |
|
|
"00000100000000101000000001010111", -- 037
|
| 228 |
|
|
"00001000000000000000110000011111", -- 038
|
| 229 |
|
|
"00000100011000111000001101001100", -- 039
|
| 230 |
|
|
"00001000000000000000110000011111", -- 03a
|
| 231 |
|
|
"00000100011000111000001101001101", -- 03b
|
| 232 |
|
|
"00001000000000000000110000011111", -- 03c
|
| 233 |
|
|
"00000100011000111000001101001110", -- 03d
|
| 234 |
|
|
"00001000000000000000110000011111", -- 03e
|
| 235 |
|
|
"00000100011000111000001101001111", -- 03f
|
| 236 |
|
|
"00001000000000000000110000011111", -- 040
|
| 237 |
64 |
ja_rd |
"00000100011000111100001101000100", -- 041
|
| 238 |
2 |
ja_rd |
"00001000000000000000110000011111", -- 042
|
| 239 |
64 |
ja_rd |
"00000100011000111100001101000101", -- 043
|
| 240 |
2 |
ja_rd |
"00001000000000000000110000011111", -- 044
|
| 241 |
64 |
ja_rd |
"00000100011000111100001101000110", -- 045
|
| 242 |
2 |
ja_rd |
"00001000000000000000110000011111", -- 046
|
| 243 |
|
|
"00000100011000111000001110001110", -- 047
|
| 244 |
|
|
"00000000101010000000000000000000", -- 048
|
| 245 |
|
|
"00000100011000111000001101001100", -- 049
|
| 246 |
|
|
"00000000101010000000000000000000", -- 04a
|
| 247 |
|
|
"00000100011000111000001101001101", -- 04b
|
| 248 |
|
|
"00000000101010000000000000000000", -- 04c
|
| 249 |
|
|
"00000100011000111000001101001110", -- 04d
|
| 250 |
|
|
"00000000101010000000000000000000", -- 04e
|
| 251 |
|
|
"00000100011000111000001101001111", -- 04f
|
| 252 |
|
|
"00000000101010000000000000000000", -- 050
|
| 253 |
64 |
ja_rd |
"00000100011000111100001101000100", -- 051
|
| 254 |
2 |
ja_rd |
"00000000101010000000000000000000", -- 052
|
| 255 |
64 |
ja_rd |
"00000100011000111100001101000101", -- 053
|
| 256 |
2 |
ja_rd |
"00000000101010000000000000000000", -- 054
|
| 257 |
64 |
ja_rd |
"00000100011000111100001101000110", -- 055
|
| 258 |
2 |
ja_rd |
"00000000101010000000000000000000", -- 056
|
| 259 |
|
|
"00000100011000111000001110001110", -- 057
|
| 260 |
|
|
"00001000000000000000110000011001", -- 058
|
| 261 |
|
|
"00000100011000111000001101001100", -- 059
|
| 262 |
|
|
"00001000000000000000110000011001", -- 05a
|
| 263 |
|
|
"00000100011000111000001101001101", -- 05b
|
| 264 |
|
|
"00001000000000000000110000011001", -- 05c
|
| 265 |
|
|
"00000100011000111000001101001110", -- 05d
|
| 266 |
|
|
"00001000000000000000110000011001", -- 05e
|
| 267 |
|
|
"00000100011000111000001101001111", -- 05f
|
| 268 |
|
|
"00001000000000000000110000011001", -- 060
|
| 269 |
64 |
ja_rd |
"00000100011000111100001101000100", -- 061
|
| 270 |
2 |
ja_rd |
"00001000000000000000110000011001", -- 062
|
| 271 |
64 |
ja_rd |
"00000100011000111100001101000101", -- 063
|
| 272 |
2 |
ja_rd |
"00001000000000000000110000011001", -- 064
|
| 273 |
64 |
ja_rd |
"00000100011000111100001101000110", -- 065
|
| 274 |
2 |
ja_rd |
"00001000000000000000110000011001", -- 066
|
| 275 |
|
|
"00000100011000111000001110001110", -- 067
|
| 276 |
|
|
"10111100101100000000001001001101", -- 068
|
| 277 |
|
|
"00000100000000000000000000000000", -- 069
|
| 278 |
|
|
"00001000000000000000110000011001", -- 06a
|
| 279 |
6 |
ja_rd |
"10111100000000000000001010001101", -- 06b
|
| 280 |
2 |
ja_rd |
"00001000000000000000110000011100", -- 06c
|
| 281 |
|
|
"10111100011100000000001001001111", -- 06d
|
| 282 |
|
|
"00000100000000000000000000000000", -- 06e
|
| 283 |
|
|
"00001000000000000000110000011001", -- 06f
|
| 284 |
|
|
"11000000000000000000000000000000", -- 070
|
| 285 |
|
|
"10111100011001010000001010001111", -- 071
|
| 286 |
|
|
"00001000000000000000110000011100", -- 072
|
| 287 |
|
|
"10111100101110001000000001001101", -- 073
|
| 288 |
|
|
"10100100101110000000000001001101", -- 074
|
| 289 |
|
|
"10111100011110001000000001001111", -- 075
|
| 290 |
|
|
"10100100011110000000000001001111", -- 076
|
| 291 |
|
|
"00000000011110001000000000000000", -- 077
|
| 292 |
|
|
"00000000101000101000000101001100", -- 078
|
| 293 |
|
|
"00000000011110000000000000000000", -- 079
|
| 294 |
|
|
"00000100101000100000000101001101", -- 07a
|
| 295 |
|
|
"00000000101000111000000010101000", -- 07b
|
| 296 |
|
|
"00000100101000111000001101101000", -- 07c
|
| 297 |
|
|
"00000100101000111000000101000000", -- 07d
|
| 298 |
|
|
"00000100101000111000000101000001", -- 07e
|
| 299 |
|
|
"00000100101000111000000101000010", -- 07f
|
| 300 |
|
|
"00000100101000111000000101000011", -- 080
|
| 301 |
|
|
"00000100101000111000000001000111", -- 081
|
| 302 |
|
|
"00000100000000000000000100101100", -- 082
|
| 303 |
|
|
"00000100000000000000000100101101", -- 083
|
| 304 |
|
|
"00001000000000000000110000101110", -- 084
|
| 305 |
|
|
"00000000101001100000000000000000", -- 085
|
| 306 |
|
|
"00000000000001001000000001010111", -- 086
|
| 307 |
|
|
"00000000101001101000000000000000", -- 087
|
| 308 |
|
|
"00000100000001000000000001010111", -- 088
|
| 309 |
|
|
"00000100000000000000000000000000", -- 089
|
| 310 |
|
|
"00001000000000000000110000101110", -- 08a
|
| 311 |
|
|
"00010000000000000000100000000101", -- 08b
|
| 312 |
|
|
"00001000000000000000110000101110", -- 08c
|
| 313 |
|
|
"11000000101001000000000010010111", -- 08d
|
| 314 |
|
|
"00001000000000000000110000110100", -- 08e
|
| 315 |
|
|
"11000000101001001000000010010111", -- 08f
|
| 316 |
|
|
"00001000000000000000110000110100", -- 090
|
| 317 |
|
|
"00000000101001100000000000000000", -- 091
|
| 318 |
|
|
"00000000000001001000000001010111", -- 092
|
| 319 |
|
|
"00000000101001101000000000000000", -- 093
|
| 320 |
|
|
"00000100000001000000000001010111", -- 094
|
| 321 |
|
|
"00001000000000000000110000101110", -- 095
|
| 322 |
|
|
"00010000000000000000100000001101", -- 096
|
| 323 |
|
|
"00001000000000000000110000111001", -- 097
|
| 324 |
|
|
"00000000000001001000000001010111", -- 098
|
| 325 |
|
|
"00001000000000000000110000111001", -- 099
|
| 326 |
|
|
"00000100000001000000000001010111", -- 09a
|
| 327 |
|
|
"00010000000000000000100000010111", -- 09b
|
| 328 |
|
|
"11000000101001000000000010010111", -- 09c
|
| 329 |
|
|
"00001000000000000000110000110100", -- 09d
|
| 330 |
|
|
"11000000101001001000000010010111", -- 09e
|
| 331 |
|
|
"00001000000000000000110000110100", -- 09f
|
| 332 |
|
|
"11000000000001001000000001011111", -- 0a0
|
| 333 |
|
|
"00000100000001000000000001000100", -- 0a1
|
| 334 |
|
|
"00000000101000101000000000000000", -- 0a2
|
| 335 |
|
|
"00000000000001001000000001010111", -- 0a3
|
| 336 |
|
|
"00000000101000100000000000000000", -- 0a4
|
| 337 |
|
|
"00000100000001000000000001010111", -- 0a5
|
| 338 |
|
|
"11000000101110000000000010010111", -- 0a6
|
| 339 |
|
|
"00001000000000000000110000110100", -- 0a7
|
| 340 |
|
|
"11000000101110001000000010010111", -- 0a8
|
| 341 |
|
|
"00001000000000000000110000110100", -- 0a9
|
| 342 |
|
|
"00000100000000000000000000000000", -- 0aa
|
| 343 |
|
|
"11000000101000111000000010010111", -- 0ab
|
| 344 |
|
|
"00001000000000000000110000110100", -- 0ac
|
| 345 |
|
|
"11000000000000000000000010110000", -- 0ad
|
| 346 |
|
|
"00001000000000000000110000110100", -- 0ae
|
| 347 |
|
|
"00000100000000000000000000000000", -- 0af
|
| 348 |
|
|
"00001000000000000000110000111001", -- 0b0
|
| 349 |
|
|
"00000000000110001000000001010111", -- 0b1
|
| 350 |
|
|
"00001000000000000000110000111001", -- 0b2
|
| 351 |
|
|
"00000100000110000000000001010111", -- 0b3
|
| 352 |
|
|
"00001000000000000000110000111001", -- 0b4
|
| 353 |
|
|
"00000000000000110000001101010111", -- 0b5
|
| 354 |
|
|
"00001000000000000000110000111001", -- 0b6
|
| 355 |
|
|
"00000100000000111000000001010111", -- 0b7
|
| 356 |
|
|
"00001000000000000000110000111001", -- 0b8
|
| 357 |
|
|
"00000000000001100000000001010111", -- 0b9
|
| 358 |
|
|
"00001000000000000000110000111001", -- 0ba
|
| 359 |
|
|
"00000000000001101000000001010111", -- 0bb
|
| 360 |
|
|
"11000000101000100000000010010111", -- 0bc
|
| 361 |
|
|
"00001000000000000000110000110100", -- 0bd
|
| 362 |
|
|
"11000000101000101000000010010111", -- 0be
|
| 363 |
|
|
"00001000000000000000110000110100", -- 0bf
|
| 364 |
|
|
"00000000101001100000000000000000", -- 0c0
|
| 365 |
|
|
"00000000000000101000000001010111", -- 0c1
|
| 366 |
|
|
"00000000101001101000000000000000", -- 0c2
|
| 367 |
|
|
"00000100000000100000000001010111", -- 0c3
|
| 368 |
|
|
"00000000101000101000000000000000", -- 0c4
|
| 369 |
|
|
"00000000000001111000000001010111", -- 0c5
|
| 370 |
|
|
"00000000101000100000000000000000", -- 0c6
|
| 371 |
|
|
"00000100000001110000000001010111", -- 0c7
|
| 372 |
|
|
"01100100000000000000000000000000", -- 0c8
|
| 373 |
|
|
"01000100000000000000000000000000", -- 0c9
|
| 374 |
|
|
"00000000000001101000000001010111", -- 0ca
|
| 375 |
|
|
"00001000000000000000110000011111", -- 0cb
|
| 376 |
|
|
"00000000000001100000000001010111", -- 0cc
|
| 377 |
|
|
"00000000000000000000000000000000", -- 0cd
|
| 378 |
|
|
"00000001101001100000000000000000", -- 0ce
|
| 379 |
|
|
"10010110101001101000000000000000", -- 0cf
|
| 380 |
|
|
"00000100100000111000000001010111", -- 0d0
|
| 381 |
|
|
"00000000000001101000000001010111", -- 0d1
|
| 382 |
|
|
"00001000000000000000110000011111", -- 0d2
|
| 383 |
|
|
"00000000000001100000000001010111", -- 0d3
|
| 384 |
|
|
"00000000101000111000000010010111", -- 0d4
|
| 385 |
|
|
"00000001101001100000000000000000", -- 0d5
|
| 386 |
|
|
"10011010101001101000000000000000", -- 0d6
|
| 387 |
|
|
"00000100000000000000000000000000", -- 0d7
|
| 388 |
|
|
"11100100000000000000000000000000", -- 0d8
|
| 389 |
|
|
"00000001101000101000000000000000", -- 0d9
|
| 390 |
|
|
"00010110101000100000000000000000", -- 0da
|
| 391 |
|
|
"00001100100001010000000001010111", -- 0db
|
| 392 |
|
|
"00000001101000101000000000000000", -- 0dc
|
| 393 |
|
|
"00011010101000100000000000000000", -- 0dd
|
| 394 |
|
|
"00000100000000000000000000000000", -- 0de
|
| 395 |
|
|
"10111101101001001000000001001101", -- 0df
|
| 396 |
|
|
"10110110101001000000000001001101", -- 0e0
|
| 397 |
|
|
"00001100100000000000000010010111", -- 0e1
|
| 398 |
|
|
"00000001101001100000000000000000", -- 0e2
|
| 399 |
|
|
"00010110101001101000000000000000", -- 0e3
|
| 400 |
|
|
"00001100100000000000000000000000", -- 0e4
|
| 401 |
|
|
"00000001101001100000000000000000", -- 0e5
|
| 402 |
|
|
"00011010101001101000000000000000", -- 0e6
|
| 403 |
|
|
"00000100000000000000000000000000", -- 0e7
|
| 404 |
|
|
"00000001101110001000000000000000", -- 0e8
|
| 405 |
|
|
"00010110101110000000000000000000", -- 0e9
|
| 406 |
|
|
"00001100100000000000000000000000", -- 0ea
|
| 407 |
|
|
"00000001101110001000000000000000", -- 0eb
|
| 408 |
|
|
"00011010101110000000000000000000", -- 0ec
|
| 409 |
|
|
"00000100000000000000000000000000", -- 0ed
|
| 410 |
|
|
"10111101101001001000000001001101", -- 0ee
|
| 411 |
|
|
"10110110101001000000000001001101", -- 0ef
|
| 412 |
|
|
"00000000100001100000000001010111", -- 0f0
|
| 413 |
|
|
"10111101101001001000000001001101", -- 0f1
|
| 414 |
|
|
"10110110101001000000000001001101", -- 0f2
|
| 415 |
|
|
"00001100100001101000000001010111", -- 0f3
|
| 416 |
|
|
"10111100011001111000000001001111", -- 0f4
|
| 417 |
|
|
"10100000011001110000000001001111", -- 0f5
|
| 418 |
|
|
"00000001101001111000000000000000", -- 0f6
|
| 419 |
|
|
"00011010101001110000000000000000", -- 0f7
|
| 420 |
|
|
"00001100000000000000000000000000", -- 0f8
|
| 421 |
|
|
"10111101101001111000000001001101", -- 0f9
|
| 422 |
|
|
"10110110101001110000000001001101", -- 0fa
|
| 423 |
|
|
"00001100100000000000000000000000", -- 0fb
|
| 424 |
|
|
"00000100000000000000000000000000", -- 0fc
|
| 425 |
|
|
"00000100000000000000000000000000", -- 0fd
|
| 426 |
|
|
"00000100000000000000000000000000", -- 0fe
|
| 427 |
|
|
"00000100000000000000000000000000", -- 0ff
|
| 428 |
|
|
"00001000000000000000100000001001", -- 100
|
| 429 |
|
|
"00001000000000000000000000010010", -- 101
|
| 430 |
|
|
"00001000000000000000000000101010", -- 102
|
| 431 |
|
|
"00001000000000000000010000110011", -- 103
|
| 432 |
|
|
"00001000000000000000010000101000", -- 104
|
| 433 |
|
|
"00001000000000000000010000101101", -- 105
|
| 434 |
|
|
"00001000000000000000000000001110", -- 106
|
| 435 |
|
|
"00001000000000000000010000111101", -- 107
|
| 436 |
|
|
"00001000000000000000000000000000", -- 108
|
| 437 |
|
|
"00001000000000000000010000110111", -- 109
|
| 438 |
|
|
"00001000000000000000000000101000", -- 10a
|
| 439 |
|
|
"00001000000000000000010000110101", -- 10b
|
| 440 |
|
|
"00001000000000000000010000101000", -- 10c
|
| 441 |
|
|
"00001000000000000000010000101101", -- 10d
|
| 442 |
|
|
"00001000000000000000000000001110", -- 10e
|
| 443 |
|
|
"00001000000000000000010000111110", -- 10f
|
| 444 |
|
|
"00001000000000000000000000000000", -- 110
|
| 445 |
|
|
"00001000000000000000000000010010", -- 111
|
| 446 |
|
|
"00001000000000000000000000101010", -- 112
|
| 447 |
|
|
"00001000000000000000010000110011", -- 113
|
| 448 |
|
|
"00001000000000000000010000101000", -- 114
|
| 449 |
|
|
"00001000000000000000010000101101", -- 115
|
| 450 |
|
|
"00001000000000000000000000001110", -- 116
|
| 451 |
|
|
"00001000000000000000010000111111", -- 117
|
| 452 |
|
|
"00001000000000000000000000000000", -- 118
|
| 453 |
|
|
"00001000000000000000010000110111", -- 119
|
| 454 |
|
|
"00001000000000000000000000101000", -- 11a
|
| 455 |
|
|
"00001000000000000000010000110101", -- 11b
|
| 456 |
|
|
"00001000000000000000010000101000", -- 11c
|
| 457 |
|
|
"00001000000000000000010000101101", -- 11d
|
| 458 |
|
|
"00001000000000000000000000001110", -- 11e
|
| 459 |
|
|
"00001000000000000000100000000000", -- 11f
|
| 460 |
|
|
"00001000000000000000000000000000", -- 120
|
| 461 |
|
|
"00001000000000000000000000010010", -- 121
|
| 462 |
|
|
"00001000000000000000000000100010", -- 122
|
| 463 |
|
|
"00001000000000000000010000110011", -- 123
|
| 464 |
|
|
"00001000000000000000010000101000", -- 124
|
| 465 |
|
|
"00001000000000000000010000101101", -- 125
|
| 466 |
|
|
"00001000000000000000000000001110", -- 126
|
| 467 |
|
|
"00001000000000000000010000111011", -- 127
|
| 468 |
|
|
"00001000000000000000000000000000", -- 128
|
| 469 |
|
|
"00001000000000000000010000110111", -- 129
|
| 470 |
|
|
"00001000000000000000000000011100", -- 12a
|
| 471 |
|
|
"00001000000000000000010000110101", -- 12b
|
| 472 |
|
|
"00001000000000000000010000101000", -- 12c
|
| 473 |
|
|
"00001000000000000000010000101101", -- 12d
|
| 474 |
|
|
"00001000000000000000000000001110", -- 12e
|
| 475 |
|
|
"00001000000000000000100000000001", -- 12f
|
| 476 |
|
|
"00001000000000000000000000000000", -- 130
|
| 477 |
|
|
"00001000000000000000000000010010", -- 131
|
| 478 |
|
|
"00001000000000000000000000011001", -- 132
|
| 479 |
|
|
"00001000000000000000010000110011", -- 133
|
| 480 |
|
|
"00001000000000000000010000101010", -- 134
|
| 481 |
|
|
"00001000000000000000010000101111", -- 135
|
| 482 |
|
|
"00001000000000000000000000010000", -- 136
|
| 483 |
|
|
"00001000000000000000100000000011", -- 137
|
| 484 |
|
|
"00001000000000000000000000000000", -- 138
|
| 485 |
|
|
"00001000000000000000010000110111", -- 139
|
| 486 |
|
|
"00001000000000000000000000010110", -- 13a
|
| 487 |
|
|
"00001000000000000000010000110101", -- 13b
|
| 488 |
|
|
"00001000000000000000010000101000", -- 13c
|
| 489 |
|
|
"00001000000000000000010000101101", -- 13d
|
| 490 |
|
|
"00001000000000000000000000001110", -- 13e
|
| 491 |
|
|
"00001000000000000000100000000010", -- 13f
|
| 492 |
|
|
"00001000000000000000000000001000", -- 140
|
| 493 |
|
|
"00001000000000000000000000001000", -- 141
|
| 494 |
|
|
"00001000000000000000000000001000", -- 142
|
| 495 |
|
|
"00001000000000000000000000001000", -- 143
|
| 496 |
|
|
"00001000000000000000000000001000", -- 144
|
| 497 |
|
|
"00001000000000000000000000001000", -- 145
|
| 498 |
|
|
"00001000000000000000000000001010", -- 146
|
| 499 |
|
|
"00001000000000000000000000001000", -- 147
|
| 500 |
|
|
"00001000000000000000000000001000", -- 148
|
| 501 |
|
|
"00001000000000000000000000001000", -- 149
|
| 502 |
|
|
"00001000000000000000000000001000", -- 14a
|
| 503 |
|
|
"00001000000000000000000000001000", -- 14b
|
| 504 |
|
|
"00001000000000000000000000001000", -- 14c
|
| 505 |
|
|
"00001000000000000000000000001000", -- 14d
|
| 506 |
|
|
"00001000000000000000000000001010", -- 14e
|
| 507 |
|
|
"00001000000000000000000000001000", -- 14f
|
| 508 |
|
|
"00001000000000000000000000001000", -- 150
|
| 509 |
|
|
"00001000000000000000000000001000", -- 151
|
| 510 |
|
|
"00001000000000000000000000001000", -- 152
|
| 511 |
|
|
"00001000000000000000000000001000", -- 153
|
| 512 |
|
|
"00001000000000000000000000001000", -- 154
|
| 513 |
|
|
"00001000000000000000000000001000", -- 155
|
| 514 |
|
|
"00001000000000000000000000001010", -- 156
|
| 515 |
|
|
"00001000000000000000000000001000", -- 157
|
| 516 |
|
|
"00001000000000000000000000001000", -- 158
|
| 517 |
|
|
"00001000000000000000000000001000", -- 159
|
| 518 |
|
|
"00001000000000000000000000001000", -- 15a
|
| 519 |
|
|
"00001000000000000000000000001000", -- 15b
|
| 520 |
|
|
"00001000000000000000000000001000", -- 15c
|
| 521 |
|
|
"00001000000000000000000000001000", -- 15d
|
| 522 |
|
|
"00001000000000000000000000001010", -- 15e
|
| 523 |
|
|
"00001000000000000000000000001000", -- 15f
|
| 524 |
|
|
"00001000000000000000000000001000", -- 160
|
| 525 |
|
|
"00001000000000000000000000001000", -- 161
|
| 526 |
|
|
"00001000000000000000000000001000", -- 162
|
| 527 |
|
|
"00001000000000000000000000001000", -- 163
|
| 528 |
|
|
"00001000000000000000000000001000", -- 164
|
| 529 |
|
|
"00001000000000000000000000001000", -- 165
|
| 530 |
|
|
"00001000000000000000000000001010", -- 166
|
| 531 |
|
|
"00001000000000000000000000001000", -- 167
|
| 532 |
|
|
"00001000000000000000000000001000", -- 168
|
| 533 |
|
|
"00001000000000000000000000001000", -- 169
|
| 534 |
|
|
"00001000000000000000000000001000", -- 16a
|
| 535 |
|
|
"00001000000000000000000000001000", -- 16b
|
| 536 |
|
|
"00001000000000000000000000001000", -- 16c
|
| 537 |
|
|
"00001000000000000000000000001000", -- 16d
|
| 538 |
|
|
"00001000000000000000000000001010", -- 16e
|
| 539 |
|
|
"00001000000000000000000000001000", -- 16f
|
| 540 |
|
|
"00001000000000000000000000001100", -- 170
|
| 541 |
|
|
"00001000000000000000000000001100", -- 171
|
| 542 |
|
|
"00001000000000000000000000001100", -- 172
|
| 543 |
|
|
"00001000000000000000000000001100", -- 173
|
| 544 |
|
|
"00001000000000000000000000001100", -- 174
|
| 545 |
|
|
"00001000000000000000000000001100", -- 175
|
| 546 |
|
|
"00001000000000000000110000011000", -- 176
|
| 547 |
|
|
"00001000000000000000000000001100", -- 177
|
| 548 |
|
|
"00001000000000000000000000001000", -- 178
|
| 549 |
|
|
"00001000000000000000000000001000", -- 179
|
| 550 |
|
|
"00001000000000000000000000001000", -- 17a
|
| 551 |
|
|
"00001000000000000000000000001000", -- 17b
|
| 552 |
|
|
"00001000000000000000000000001000", -- 17c
|
| 553 |
|
|
"00001000000000000000000000001000", -- 17d
|
| 554 |
|
|
"00001000000000000000000000001010", -- 17e
|
| 555 |
|
|
"00001000000000000000000000001000", -- 17f
|
| 556 |
|
|
"00001000000000000000010000001000", -- 180
|
| 557 |
|
|
"00001000000000000000010000001000", -- 181
|
| 558 |
|
|
"00001000000000000000010000001000", -- 182
|
| 559 |
|
|
"00001000000000000000010000001000", -- 183
|
| 560 |
|
|
"00001000000000000000010000001000", -- 184
|
| 561 |
|
|
"00001000000000000000010000001000", -- 185
|
| 562 |
|
|
"00001000000000000000010000011000", -- 186
|
| 563 |
|
|
"00001000000000000000010000001000", -- 187
|
| 564 |
|
|
"00001000000000000000010000001010", -- 188
|
| 565 |
|
|
"00001000000000000000010000001010", -- 189
|
| 566 |
|
|
"00001000000000000000010000001010", -- 18a
|
| 567 |
|
|
"00001000000000000000010000001010", -- 18b
|
| 568 |
|
|
"00001000000000000000010000001010", -- 18c
|
| 569 |
|
|
"00001000000000000000010000001010", -- 18d
|
| 570 |
|
|
"00001000000000000000010000011010", -- 18e
|
| 571 |
|
|
"00001000000000000000010000001010", -- 18f
|
| 572 |
|
|
"00001000000000000000010000001100", -- 190
|
| 573 |
|
|
"00001000000000000000010000001100", -- 191
|
| 574 |
|
|
"00001000000000000000010000001100", -- 192
|
| 575 |
|
|
"00001000000000000000010000001100", -- 193
|
| 576 |
|
|
"00001000000000000000010000001100", -- 194
|
| 577 |
|
|
"00001000000000000000010000001100", -- 195
|
| 578 |
|
|
"00001000000000000000010000011100", -- 196
|
| 579 |
|
|
"00001000000000000000010000001100", -- 197
|
| 580 |
|
|
"00001000000000000000010000001110", -- 198
|
| 581 |
|
|
"00001000000000000000010000001110", -- 199
|
| 582 |
|
|
"00001000000000000000010000001110", -- 19a
|
| 583 |
|
|
"00001000000000000000010000001110", -- 19b
|
| 584 |
|
|
"00001000000000000000010000001110", -- 19c
|
| 585 |
|
|
"00001000000000000000010000001110", -- 19d
|
| 586 |
|
|
"00001000000000000000010000011110", -- 19e
|
| 587 |
|
|
"00001000000000000000010000001110", -- 19f
|
| 588 |
|
|
"00001000000000000000010000010000", -- 1a0
|
| 589 |
|
|
"00001000000000000000010000010000", -- 1a1
|
| 590 |
|
|
"00001000000000000000010000010000", -- 1a2
|
| 591 |
|
|
"00001000000000000000010000010000", -- 1a3
|
| 592 |
|
|
"00001000000000000000010000010000", -- 1a4
|
| 593 |
|
|
"00001000000000000000010000010000", -- 1a5
|
| 594 |
|
|
"00001000000000000000010000100000", -- 1a6
|
| 595 |
|
|
"00001000000000000000010000010000", -- 1a7
|
| 596 |
|
|
"00001000000000000000010000010010", -- 1a8
|
| 597 |
|
|
"00001000000000000000010000010010", -- 1a9
|
| 598 |
|
|
"00001000000000000000010000010010", -- 1aa
|
| 599 |
|
|
"00001000000000000000010000010010", -- 1ab
|
| 600 |
|
|
"00001000000000000000010000010010", -- 1ac
|
| 601 |
|
|
"00001000000000000000010000010010", -- 1ad
|
| 602 |
|
|
"00001000000000000000010000100010", -- 1ae
|
| 603 |
|
|
"00001000000000000000010000010010", -- 1af
|
| 604 |
|
|
"00001000000000000000010000010100", -- 1b0
|
| 605 |
|
|
"00001000000000000000010000010100", -- 1b1
|
| 606 |
|
|
"00001000000000000000010000010100", -- 1b2
|
| 607 |
|
|
"00001000000000000000010000010100", -- 1b3
|
| 608 |
|
|
"00001000000000000000010000010100", -- 1b4
|
| 609 |
|
|
"00001000000000000000010000010100", -- 1b5
|
| 610 |
|
|
"00001000000000000000010000100100", -- 1b6
|
| 611 |
|
|
"00001000000000000000010000010100", -- 1b7
|
| 612 |
|
|
"00001000000000000000010000010110", -- 1b8
|
| 613 |
|
|
"00001000000000000000010000010110", -- 1b9
|
| 614 |
|
|
"00001000000000000000010000010110", -- 1ba
|
| 615 |
|
|
"00001000000000000000010000010110", -- 1bb
|
| 616 |
|
|
"00001000000000000000010000010110", -- 1bc
|
| 617 |
|
|
"00001000000000000000010000010110", -- 1bd
|
| 618 |
|
|
"00001000000000000000010000100110", -- 1be
|
| 619 |
|
|
"00001000000000000000010000010110", -- 1bf
|
| 620 |
|
|
"00001000000000000000100000011011", -- 1c0
|
| 621 |
|
|
"00001000000000000000100000110000", -- 1c1
|
| 622 |
|
|
"00001000000000000000100000001010", -- 1c2
|
| 623 |
|
|
"00001000000000000000100000000100", -- 1c3
|
| 624 |
|
|
"00001000000000000000100000010101", -- 1c4
|
| 625 |
|
|
"00001000000000000000100000100110", -- 1c5
|
| 626 |
|
|
"00001000000000000000000000111000", -- 1c6
|
| 627 |
|
|
"00001000000000000000100000011100", -- 1c7
|
| 628 |
|
|
"00001000000000000000100000011011", -- 1c8
|
| 629 |
|
|
"00001000000000000000100000010111", -- 1c9
|
| 630 |
|
|
"00001000000000000000100000001010", -- 1ca
|
| 631 |
|
|
"00001000000000000000000000000000", -- 1cb
|
| 632 |
|
|
"00001000000000000000100000010101", -- 1cc
|
| 633 |
|
|
"00001000000000000000100000001100", -- 1cd
|
| 634 |
|
|
"00001000000000000000000000111010", -- 1ce
|
| 635 |
|
|
"00001000000000000000100000011100", -- 1cf
|
| 636 |
|
|
"00001000000000000000100000011011", -- 1d0
|
| 637 |
|
|
"00001000000000000000100000110000", -- 1d1
|
| 638 |
|
|
"00001000000000000000100000001010", -- 1d2
|
| 639 |
|
|
"00001000000000000000110000010001", -- 1d3
|
| 640 |
|
|
"00001000000000000000100000010101", -- 1d4
|
| 641 |
|
|
"00001000000000000000100000100110", -- 1d5
|
| 642 |
|
|
"00001000000000000000000000111100", -- 1d6
|
| 643 |
|
|
"00001000000000000000100000011100", -- 1d7
|
| 644 |
|
|
"00001000000000000000100000011011", -- 1d8
|
| 645 |
|
|
"00001000000000000000000000000000", -- 1d9
|
| 646 |
|
|
"00001000000000000000100000001010", -- 1da
|
| 647 |
|
|
"00001000000000000000110000001010", -- 1db
|
| 648 |
|
|
"00001000000000000000100000010101", -- 1dc
|
| 649 |
|
|
"00001000000000000000000000000000", -- 1dd
|
| 650 |
|
|
"00001000000000000000000000111110", -- 1de
|
| 651 |
|
|
"00001000000000000000100000011100", -- 1df
|
| 652 |
|
|
"00001000000000000000100000011011", -- 1e0
|
| 653 |
|
|
"00001000000000000000100000110000", -- 1e1
|
| 654 |
|
|
"00001000000000000000100000001010", -- 1e2
|
| 655 |
|
|
"00001000000000000000100000111000", -- 1e3
|
| 656 |
|
|
"00001000000000000000100000010101", -- 1e4
|
| 657 |
|
|
"00001000000000000000100000100110", -- 1e5
|
| 658 |
|
|
"00001000000000000000010000000000", -- 1e6
|
| 659 |
|
|
"00001000000000000000100000011100", -- 1e7
|
| 660 |
|
|
"00001000000000000000100000011011", -- 1e8
|
| 661 |
|
|
"00001000000000000000100000100010", -- 1e9
|
| 662 |
|
|
"00001000000000000000100000001010", -- 1ea
|
| 663 |
|
|
"00001000000000000000000000101100", -- 1eb
|
| 664 |
|
|
"00001000000000000000100000010101", -- 1ec
|
| 665 |
|
|
"00001000000000000000000000000000", -- 1ed
|
| 666 |
|
|
"00001000000000000000010000000010", -- 1ee
|
| 667 |
|
|
"00001000000000000000100000011100", -- 1ef
|
| 668 |
|
|
"00001000000000000000100000011011", -- 1f0
|
| 669 |
|
|
"00001000000000000000100000110100", -- 1f1
|
| 670 |
|
|
"00001000000000000000100000001010", -- 1f2
|
| 671 |
|
|
"00001000000000000000110000001001", -- 1f3
|
| 672 |
|
|
"00001000000000000000100000010101", -- 1f4
|
| 673 |
|
|
"00001000000000000000100000101011", -- 1f5
|
| 674 |
|
|
"00001000000000000000010000000100", -- 1f6
|
| 675 |
|
|
"00001000000000000000100000011100", -- 1f7
|
| 676 |
|
|
"00001000000000000000100000011011", -- 1f8
|
| 677 |
|
|
"00001000000000000000110000000100", -- 1f9
|
| 678 |
|
|
"00001000000000000000100000001010", -- 1fa
|
| 679 |
|
|
"00001000000000000000110000001000", -- 1fb
|
| 680 |
|
|
"00001000000000000000100000010101", -- 1fc
|
| 681 |
|
|
"00001000000000000000000000000000", -- 1fd
|
| 682 |
|
|
"00001000000000000000010000000110", -- 1fe
|
| 683 |
|
|
"00001000000000000000100000011100" -- 1ff
|
| 684 |
|
|
|
| 685 |
|
|
);
|
| 686 |
|
|
|
| 687 |
|
|
-- end of microcode ROM
|
| 688 |
|
|
|
| 689 |
|
|
signal load_al : std_logic; -- uinst field, load AL reg from rbank
|
| 690 |
|
|
signal load_addr : std_logic; -- uinst field, enable external addr reg load
|
| 691 |
|
|
signal load_t1 : std_logic; -- uinst field, load reg T1
|
| 692 |
|
|
signal load_t2 : std_logic; -- uinst field, load reg T2
|
| 693 |
|
|
signal mux_in : std_logic; -- uinst field, T1/T2 input data selection
|
| 694 |
|
|
signal load_do : std_logic; -- uinst field, pipelined, load DO reg
|
| 695 |
|
|
-- rb_addr_sel: uinst field, rbank address selection: (sss,ddd,pp,ra_field)
|
| 696 |
|
|
signal rb_addr_sel : std_logic_vector(1 downto 0);
|
| 697 |
|
|
-- ra_field: uinst field, explicit reg bank address
|
| 698 |
|
|
signal ra_field : std_logic_vector(3 downto 0);
|
| 699 |
|
|
signal rbank_data : std_logic_vector(7 downto 0); -- rbank output
|
| 700 |
|
|
signal alu_output : std_logic_vector(7 downto 0); -- ALU output
|
| 701 |
|
|
-- data_output: datapath output: ALU output vs. F reg
|
| 702 |
|
|
signal data_output : std_logic_vector(7 downto 0);
|
| 703 |
|
|
signal T1 : std_logic_vector(7 downto 0); -- T1 reg (ALU operand)
|
| 704 |
|
|
signal T2 : std_logic_vector(7 downto 0); -- T2 reg (ALU operand)
|
| 705 |
|
|
-- alu_input: data loaded into T1, T2: rbank data vs. DI
|
| 706 |
|
|
signal alu_input : std_logic_vector(7 downto 0);
|
| 707 |
|
|
signal we_rb : std_logic; -- uinst field, commands a write to the rbank
|
| 708 |
|
|
signal inhibit_pc_increment : std_logic; -- avoid PC changes (during INTA)
|
| 709 |
|
|
signal rbank_rd_addr: std_logic_vector(3 downto 0); -- rbank rd addr
|
| 710 |
|
|
signal rbank_wr_addr: std_logic_vector(3 downto 0); -- rbank wr addr
|
| 711 |
|
|
signal DO : std_logic_vector(7 downto 0); -- data output reg
|
| 712 |
|
|
|
| 713 |
64 |
ja_rd |
-- Register bank as an array of 16 bytes.
|
| 714 |
|
|
-- This will be implemented as asynchronous LUT RAM in those devices where this
|
| 715 |
|
|
-- feature is available (Xilinx) and as multiplexed registers where it isn't
|
| 716 |
|
|
-- (Altera).
|
| 717 |
2 |
ja_rd |
type t_reg_bank is array(0 to 15) of std_logic_vector(7 downto 0);
|
| 718 |
|
|
-- Register bank : BC, DE, HL, AF, [PC, XY, ZW, SP]
|
| 719 |
|
|
signal rbank : t_reg_bank;
|
| 720 |
|
|
|
| 721 |
|
|
signal flag_reg : std_logic_vector(7 downto 0); -- F register
|
| 722 |
|
|
-- flag_pattern: uinst field, F update pattern: which flags are updated
|
| 723 |
|
|
signal flag_pattern : std_logic_vector(1 downto 0);
|
| 724 |
|
|
signal flag_s : std_logic; -- new computed S flag
|
| 725 |
|
|
signal flag_z : std_logic; -- new computed Z flag
|
| 726 |
|
|
signal flag_p : std_logic; -- new computed P flag
|
| 727 |
|
|
signal flag_cy : std_logic; -- new computed C flag
|
| 728 |
|
|
signal flag_cy_1 : std_logic; -- C flag computed from arith/logic operation
|
| 729 |
|
|
signal flag_cy_2 : std_logic; -- C flag computed from CPC circuit
|
| 730 |
|
|
signal do_cy_op : std_logic; -- ALU explicit CY operation (CPC, etc.)
|
| 731 |
|
|
signal do_cy_op_d : std_logic; -- do_cy_op, pipelined
|
| 732 |
|
|
signal do_cpc : std_logic; -- ALU operation is CPC
|
| 733 |
|
|
signal do_cpc_d : std_logic; -- do_cpc, pipelined
|
| 734 |
|
|
signal do_daa : std_logic; -- ALU operation is DAA
|
| 735 |
64 |
ja_rd |
signal clear_cy : std_logic; -- Instruction unconditionally clears CY
|
| 736 |
|
|
signal clear_ac : std_logic; -- Instruction unconditionally clears AC
|
| 737 |
|
|
signal set_ac : std_logic; -- Instruction unconditionally sets AC
|
| 738 |
2 |
ja_rd |
signal flag_ac : std_logic; -- new computed half carry flag
|
| 739 |
|
|
-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)
|
| 740 |
|
|
signal flag_aux_cy : std_logic;
|
| 741 |
|
|
signal load_psw : std_logic; -- load F register
|
| 742 |
|
|
|
| 743 |
|
|
-- aux carry computation and control signals
|
| 744 |
|
|
signal use_aux : std_logic; -- decoded from flags in 1st phase
|
| 745 |
|
|
signal use_aux_cy : std_logic; -- 2nd phase signal
|
| 746 |
|
|
signal reg_aux_cy : std_logic;
|
| 747 |
|
|
signal aux_cy_in : std_logic;
|
| 748 |
|
|
signal set_aux_cy : std_logic;
|
| 749 |
|
|
signal set_aux : std_logic;
|
| 750 |
|
|
|
| 751 |
|
|
-- ALU control signals -- together they select ALU operation
|
| 752 |
|
|
signal alu_fn : std_logic_vector(1 downto 0);
|
| 753 |
|
|
signal use_logic : std_logic; -- logic/arith mux control
|
| 754 |
|
|
signal mux_fn : std_logic_vector(1 downto 0);
|
| 755 |
|
|
signal use_psw : std_logic; -- ALU/F mux control
|
| 756 |
|
|
|
| 757 |
|
|
-- ALU arithmetic operands and result
|
| 758 |
|
|
signal arith_op1 : std_logic_vector(8 downto 0);
|
| 759 |
|
|
signal arith_op2 : std_logic_vector(8 downto 0);
|
| 760 |
|
|
signal arith_op2_sgn: std_logic_vector(8 downto 0);
|
| 761 |
|
|
signal arith_res : std_logic_vector(8 downto 0);
|
| 762 |
|
|
signal arith_res8 : std_logic_vector(7 downto 0);
|
| 763 |
|
|
|
| 764 |
|
|
-- ALU DAA intermediate signals (DAA has fully dedicated logic)
|
| 765 |
|
|
signal daa_res : std_logic_vector(8 downto 0);
|
| 766 |
|
|
signal daa_res8 : std_logic_vector(7 downto 0);
|
| 767 |
|
|
signal daa_res9 : std_logic_vector(8 downto 0);
|
| 768 |
|
|
signal daa_test1 : std_logic;
|
| 769 |
|
|
signal daa_test1a : std_logic;
|
| 770 |
|
|
signal daa_test2 : std_logic;
|
| 771 |
|
|
signal daa_test2a : std_logic;
|
| 772 |
|
|
signal arith_daa_res :std_logic_vector(7 downto 0);
|
| 773 |
|
|
signal cy_daa : std_logic;
|
| 774 |
|
|
|
| 775 |
|
|
-- ALU CY flag intermediate signals
|
| 776 |
|
|
signal cy_in_sgn : std_logic;
|
| 777 |
|
|
signal cy_in : std_logic;
|
| 778 |
|
|
signal cy_in_gated : std_logic;
|
| 779 |
|
|
signal cy_adder : std_logic;
|
| 780 |
|
|
signal cy_arith : std_logic;
|
| 781 |
|
|
signal cy_shifter : std_logic;
|
| 782 |
|
|
|
| 783 |
|
|
-- ALU intermediate results
|
| 784 |
|
|
signal logic_res : std_logic_vector(7 downto 0);
|
| 785 |
|
|
signal shift_res : std_logic_vector(7 downto 0);
|
| 786 |
|
|
signal alu_mux1 : std_logic_vector(7 downto 0);
|
| 787 |
|
|
|
| 788 |
49 |
ja_rd |
|
| 789 |
2 |
ja_rd |
begin
|
| 790 |
|
|
|
| 791 |
|
|
DI <= data_in;
|
| 792 |
|
|
|
| 793 |
|
|
process(clk) -- IR register, load when uc_decode flag activates
|
| 794 |
|
|
begin
|
| 795 |
|
|
if clk'event and clk='1' then
|
| 796 |
|
|
if uc_decode = '1' then
|
| 797 |
|
|
IR <= DI;
|
| 798 |
|
|
end if;
|
| 799 |
|
|
end if;
|
| 800 |
|
|
end process;
|
| 801 |
|
|
|
| 802 |
|
|
s_field <= IR(2 downto 0); -- IR field extraction : sss reg code
|
| 803 |
|
|
d_field <= IR(5 downto 3); -- ddd reg code
|
| 804 |
|
|
p_field <= IR(5 downto 4); -- pp 16-bit reg pair code
|
| 805 |
|
|
|
| 806 |
|
|
|
| 807 |
|
|
--##############################################################################
|
| 808 |
|
|
-- Microcode sequencer
|
| 809 |
|
|
|
| 810 |
|
|
process(clk) -- do_reset is reset delayed 1 cycle
|
| 811 |
|
|
begin
|
| 812 |
|
|
if clk'event and clk='1' then
|
| 813 |
|
|
do_reset <= reset;
|
| 814 |
|
|
end if;
|
| 815 |
|
|
end process;
|
| 816 |
|
|
|
| 817 |
|
|
uc_flags1 <= ucode(31 downto 29);
|
| 818 |
|
|
uc_flags2 <= ucode(28 downto 26);
|
| 819 |
|
|
|
| 820 |
|
|
-- microcode address control flags are gated by do_reset (reset has priority)
|
| 821 |
|
|
uc_do_ret <= '1' when uc_flags2 = "011" and do_reset = '0' else '0';
|
| 822 |
|
|
uc_jsr <= '1' when uc_flags2 = "010" and do_reset = '0' else '0';
|
| 823 |
|
|
uc_tjsr <= '1' when uc_flags2 = "100" and do_reset = '0' else '0';
|
| 824 |
|
|
uc_decode <= '1' when uc_flags1 = "001" and do_reset = '0' else '0';
|
| 825 |
|
|
uc_end <= '1' when (uc_flags2 = "001" or (uc_tjsr='1' and condition_reg='0'))
|
| 826 |
|
|
and do_reset = '0' else '0';
|
| 827 |
|
|
|
| 828 |
|
|
-- other microinstruction flags are decoded
|
| 829 |
|
|
uc_halt_flag <= '1' when uc_flags1 = "111" else '0';
|
| 830 |
|
|
uc_halt <= '1' when uc_halt_flag='1' and inta_reg='0' else '0';
|
| 831 |
|
|
uc_ei <= '1' when uc_flags1 = "011" else '0';
|
| 832 |
|
|
uc_di <= '1' when uc_flags1 = "010" or inta_reg='1' else '0';
|
| 833 |
|
|
-- clr_t1/2 clears T1/T2 when explicitly commanded; T2 and T1 clear implicitly
|
| 834 |
|
|
-- at the end of each instruction (by uc_decode)
|
| 835 |
|
|
clr_t2 <= '1' when uc_flags2 = "001" else '0';
|
| 836 |
|
|
clr_t1 <= '1' when uc_flags1 = "110" else '0';
|
| 837 |
|
|
use_aux <= '1' when uc_flags1 = "101" else '0';
|
| 838 |
|
|
set_aux <= '1' when uc_flags2 = "111" else '0';
|
| 839 |
|
|
|
| 840 |
|
|
load_al <= ucode(24);
|
| 841 |
|
|
load_addr <= ucode(25);
|
| 842 |
|
|
|
| 843 |
|
|
do_cy_op_d <= '1' when ucode(5 downto 2)="1011" else '0'; -- decode CY ALU op
|
| 844 |
|
|
do_cpc_d <= ucode(0); -- decode CPC ALU op
|
| 845 |
|
|
|
| 846 |
|
|
-- uinst jump command, either unconditional or on a given condition
|
| 847 |
|
|
uc_do_jmp <= uc_jsr or (uc_tjsr and condition_reg);
|
| 848 |
|
|
|
| 849 |
|
|
vma <= load_addr; -- addr is valid, either for memmory or io
|
| 850 |
|
|
|
| 851 |
19 |
ja_rd |
-- assume the only uinst that does memory access in the range 0..f is 'fetch'
|
| 852 |
|
|
fetch <= '1' when uc_addr(7 downto 4)=X"0" and load_addr='1' else '0';
|
| 853 |
|
|
|
| 854 |
2 |
ja_rd |
-- external bus interface control signals
|
| 855 |
|
|
io <= '1' when uc_flags1="100" else '0'; -- IO access (vs. memory)
|
| 856 |
|
|
rd <= '1' when uc_flags2="101" else '0'; -- RD access
|
| 857 |
|
|
wr <= '1' when uc_flags2="110" else '0'; -- WR access
|
| 858 |
|
|
|
| 859 |
|
|
uc_jmp_addr <= ucode(11 downto 10) & ucode(5 downto 0);
|
| 860 |
|
|
|
| 861 |
|
|
uc_addr_sel <= uc_do_ret & uc_do_jmp & uc_decode & uc_end;
|
| 862 |
|
|
|
| 863 |
|
|
addr_plus_1 <= uc_addr + 1;
|
| 864 |
|
|
|
| 865 |
|
|
-- TODO simplify this!!
|
| 866 |
|
|
|
| 867 |
|
|
-- NOTE: when end='1' we jump either to the FETCH ucode ot to the HALT ucode
|
| 868 |
|
|
-- depending on the value of the halt signal.
|
| 869 |
|
|
-- We use the unregistered uc_halt instead of halt_reg because otherwise #end
|
| 870 |
|
|
-- should be on the cycle following #halt, wasting a cycle.
|
| 871 |
|
|
-- This means that the flag #halt has to be used with #end or will be ignored.
|
| 872 |
|
|
|
| 873 |
|
|
with uc_addr_sel select
|
| 874 |
|
|
next_uc_addr <= '0'&uc_ret_addr when "1000", -- ret
|
| 875 |
|
|
'0'&uc_jmp_addr when "0100", -- jsr/tjsr
|
| 876 |
|
|
'0'&addr_plus_1 when "0000", -- uaddr++
|
| 877 |
|
|
"000000"&uc_halt&"11"
|
| 878 |
|
|
when "0001", -- end: go to fetch/halt uaddr
|
| 879 |
|
|
'1'&DI when others; -- decode fetched address
|
| 880 |
|
|
|
| 881 |
|
|
-- Note how we used DI (containing instruction opcode) as a microcode address
|
| 882 |
|
|
|
| 883 |
|
|
-- read microcode rom
|
| 884 |
|
|
process (clk)
|
| 885 |
|
|
begin
|
| 886 |
|
|
if clk'event and clk='1' then
|
| 887 |
|
|
ucode <= rom(conv_integer(next_uc_addr));
|
| 888 |
|
|
end if;
|
| 889 |
|
|
end process;
|
| 890 |
|
|
|
| 891 |
|
|
-- microcode address register
|
| 892 |
|
|
process (clk)
|
| 893 |
|
|
begin
|
| 894 |
|
|
if clk'event and clk='1' then
|
| 895 |
|
|
if reset = '1' then
|
| 896 |
|
|
uc_addr <= X"00";
|
| 897 |
|
|
else
|
| 898 |
|
|
uc_addr <= next_uc_addr(7 downto 0);
|
| 899 |
|
|
end if;
|
| 900 |
|
|
end if;
|
| 901 |
|
|
end process;
|
| 902 |
|
|
|
| 903 |
|
|
-- ucode address 1-level 'return stack'
|
| 904 |
|
|
process (clk)
|
| 905 |
|
|
begin
|
| 906 |
|
|
if clk'event and clk='1' then
|
| 907 |
|
|
if reset = '1' then
|
| 908 |
|
|
uc_ret_addr <= X"00";
|
| 909 |
|
|
elsif uc_do_jmp='1' then
|
| 910 |
|
|
uc_ret_addr <= addr_plus_1;
|
| 911 |
|
|
end if;
|
| 912 |
|
|
end if;
|
| 913 |
|
|
end process;
|
| 914 |
|
|
|
| 915 |
|
|
|
| 916 |
|
|
alu_op <= ucode(3 downto 0);
|
| 917 |
|
|
|
| 918 |
|
|
-- pipeline uinst field2 for 1-cycle delayed execution.
|
| 919 |
|
|
-- note the same rbank addr field is used in cycles 1 and 2; this enforces
|
| 920 |
|
|
-- some constraints on uinst programming but simplifies the system.
|
| 921 |
|
|
process(clk)
|
| 922 |
|
|
begin
|
| 923 |
|
|
if clk'event and clk='1' then
|
| 924 |
|
|
ucode_field2 <= do_cy_op_d & do_cpc_d & clr_t2 & clr_t1 &
|
| 925 |
|
|
set_aux & use_aux & rbank_rd_addr &
|
| 926 |
|
|
ucode(14 downto 4) & alu_op;
|
| 927 |
|
|
end if;
|
| 928 |
|
|
end process;
|
| 929 |
|
|
|
| 930 |
|
|
--#### HALT logic
|
| 931 |
|
|
process(clk)
|
| 932 |
|
|
begin
|
| 933 |
|
|
if clk'event and clk='1' then
|
| 934 |
|
|
if reset = '1' or int_pending = '1' then --inta_reg
|
| 935 |
|
|
halt_reg <= '0';
|
| 936 |
|
|
else
|
| 937 |
|
|
if uc_halt = '1' then
|
| 938 |
|
|
halt_reg <= '1';
|
| 939 |
|
|
end if;
|
| 940 |
|
|
end if;
|
| 941 |
|
|
end if;
|
| 942 |
|
|
end process;
|
| 943 |
|
|
|
| 944 |
|
|
halt <= halt_reg;
|
| 945 |
|
|
|
| 946 |
|
|
--#### INTE logic -- inte_reg = '1' means interrupts ENABLED
|
| 947 |
|
|
process(clk)
|
| 948 |
|
|
begin
|
| 949 |
|
|
if clk'event and clk='1' then
|
| 950 |
|
|
if reset = '1' then
|
| 951 |
|
|
inte_reg <= '0';
|
| 952 |
49 |
ja_rd |
delayed_ei <= '0';
|
| 953 |
2 |
ja_rd |
else
|
| 954 |
49 |
ja_rd |
if (uc_di='1' or uc_ei='1') and uc_end='1' then
|
| 955 |
|
|
--inte_reg <= uc_ei;
|
| 956 |
|
|
delayed_ei <= uc_ei; -- FIXME DI must not be delayed
|
| 957 |
2 |
ja_rd |
end if;
|
| 958 |
49 |
ja_rd |
if uc_end = '1' then -- at the last cycle of every instruction...
|
| 959 |
|
|
if uc_di='1' then -- ...disable interrupts if the instruction is DI...
|
| 960 |
|
|
inte_reg <= '0';
|
| 961 |
|
|
else
|
| 962 |
|
|
-- ...of enable interrupts after the instruction following EI
|
| 963 |
|
|
inte_reg <= delayed_ei;
|
| 964 |
|
|
end if;
|
| 965 |
|
|
end if;
|
| 966 |
2 |
ja_rd |
end if;
|
| 967 |
|
|
end if;
|
| 968 |
|
|
end process;
|
| 969 |
|
|
|
| 970 |
|
|
inte <= inte_reg;
|
| 971 |
|
|
|
| 972 |
39 |
ja_rd |
-- interrupts are ignored when inte='0' but they are registered and will be
|
| 973 |
|
|
-- honored when interrupts are enabled
|
| 974 |
2 |
ja_rd |
process(clk)
|
| 975 |
|
|
begin
|
| 976 |
|
|
if clk'event and clk='1' then
|
| 977 |
|
|
if reset = '1' then
|
| 978 |
|
|
int_pending <= '0';
|
| 979 |
|
|
else
|
| 980 |
39 |
ja_rd |
-- intr will raise int_pending only if inta has not been asserted.
|
| 981 |
|
|
-- Otherwise, if intr overlapped inta, we'd enter a microcode endless
|
| 982 |
|
|
-- loop, executing the interrupt vector again and again.
|
| 983 |
|
|
if intr='1' and inte_reg='1' and int_pending='0' and inta_reg='0' then
|
| 984 |
2 |
ja_rd |
int_pending <= '1';
|
| 985 |
|
|
else
|
| 986 |
39 |
ja_rd |
-- int_pending is cleared when we're about to service the interrupt,
|
| 987 |
|
|
-- that is when interrupts are enabled and the current instruction ends.
|
| 988 |
2 |
ja_rd |
if inte_reg = '1' and uc_end='1' then
|
| 989 |
|
|
int_pending <= '0';
|
| 990 |
|
|
end if;
|
| 991 |
|
|
end if;
|
| 992 |
|
|
end if;
|
| 993 |
|
|
end if;
|
| 994 |
|
|
end process;
|
| 995 |
|
|
|
| 996 |
|
|
|
| 997 |
|
|
--#### INTA logic
|
| 998 |
|
|
-- INTA goes high from END to END, that is for the entire time the instruction
|
| 999 |
|
|
-- takes to fetch and execute; in the original 8080 it was asserted only for
|
| 1000 |
|
|
-- the M1 cycle.
|
| 1001 |
|
|
-- All instructions can be used in an inta cycle, including XTHL which was
|
| 1002 |
|
|
-- forbidden in the original 8080.
|
| 1003 |
|
|
-- It's up to you figuring out which cycle is which in multibyte instructions.
|
| 1004 |
|
|
process(clk)
|
| 1005 |
|
|
begin
|
| 1006 |
|
|
if clk'event and clk='1' then
|
| 1007 |
|
|
if reset = '1' then
|
| 1008 |
|
|
inta_reg <= '0';
|
| 1009 |
|
|
else
|
| 1010 |
|
|
if int_pending = '1' and uc_end='1' then
|
| 1011 |
|
|
-- enter INTA state
|
| 1012 |
|
|
inta_reg <= '1';
|
| 1013 |
|
|
else
|
| 1014 |
|
|
-- exit INTA state
|
| 1015 |
|
|
-- NOTE: don't reset inta when exiting halt state (uc_halt_flag='1').
|
| 1016 |
|
|
-- If we omit this condition, when intr happens on halt state, inta
|
| 1017 |
|
|
-- will only last for 1 cycle, because in halt state uc_end is
|
| 1018 |
|
|
-- always asserted.
|
| 1019 |
|
|
if uc_end = '1' and uc_halt_flag='0' then
|
| 1020 |
|
|
inta_reg <= '0';
|
| 1021 |
|
|
end if;
|
| 1022 |
|
|
end if;
|
| 1023 |
|
|
end if;
|
| 1024 |
|
|
end if;
|
| 1025 |
|
|
end process;
|
| 1026 |
|
|
|
| 1027 |
|
|
inta <= inta_reg;
|
| 1028 |
|
|
|
| 1029 |
|
|
|
| 1030 |
|
|
--##############################################################################
|
| 1031 |
|
|
-- Datapath
|
| 1032 |
|
|
|
| 1033 |
|
|
-- extract pipelined microcode fields
|
| 1034 |
|
|
ra_field <= ucode(18 downto 15);
|
| 1035 |
|
|
load_t1 <= ucode(23);
|
| 1036 |
|
|
load_t2 <= ucode(22);
|
| 1037 |
|
|
mux_in <= ucode(21);
|
| 1038 |
|
|
rb_addr_sel <= ucode(20 downto 19);
|
| 1039 |
|
|
load_do <= ucode_field2(7);
|
| 1040 |
|
|
set_aux_cy <= ucode_field2(20);
|
| 1041 |
|
|
do_clr_t1 <= ucode_field2(21);
|
| 1042 |
|
|
do_clr_t2 <= ucode_field2(22);
|
| 1043 |
|
|
|
| 1044 |
|
|
|
| 1045 |
|
|
-- T1 register
|
| 1046 |
|
|
process (clk)
|
| 1047 |
|
|
begin
|
| 1048 |
|
|
if clk'event and clk='1' then
|
| 1049 |
|
|
if reset = '1' or uc_decode = '1' or do_clr_t1='1' then
|
| 1050 |
|
|
T1 <= X"00";
|
| 1051 |
|
|
else
|
| 1052 |
|
|
if load_t1 = '1' then
|
| 1053 |
|
|
T1 <= alu_input;
|
| 1054 |
|
|
end if;
|
| 1055 |
|
|
end if;
|
| 1056 |
|
|
end if;
|
| 1057 |
|
|
end process;
|
| 1058 |
|
|
|
| 1059 |
|
|
-- T2 register
|
| 1060 |
|
|
process (clk)
|
| 1061 |
|
|
begin
|
| 1062 |
|
|
if clk'event and clk='1' then
|
| 1063 |
|
|
if reset = '1' or uc_decode = '1' or do_clr_t2='1' then
|
| 1064 |
|
|
T2 <= X"00";
|
| 1065 |
|
|
else
|
| 1066 |
|
|
if load_t2 = '1' then
|
| 1067 |
|
|
T2 <= alu_input;
|
| 1068 |
|
|
end if;
|
| 1069 |
|
|
end if;
|
| 1070 |
|
|
end if;
|
| 1071 |
|
|
end process;
|
| 1072 |
|
|
|
| 1073 |
|
|
-- T1/T2 input data mux
|
| 1074 |
|
|
alu_input <= rbank_data when mux_in = '1' else DI;
|
| 1075 |
|
|
|
| 1076 |
|
|
-- register bank address mux logic
|
| 1077 |
|
|
|
| 1078 |
|
|
rbh <= '1' when p_field = "11" else '0';
|
| 1079 |
|
|
|
| 1080 |
|
|
with rb_addr_sel select
|
| 1081 |
|
|
rbank_rd_addr <= ra_field when "00",
|
| 1082 |
|
|
"0"&s_field when "01",
|
| 1083 |
|
|
"0"&d_field when "10",
|
| 1084 |
|
|
rbh&p_field&ra_field(0) when others;
|
| 1085 |
|
|
|
| 1086 |
|
|
-- RBank writes are inhibited in INTA state, but only for PC increments.
|
| 1087 |
|
|
inhibit_pc_increment <= '1' when inta_reg='1' and use_aux_cy='1'
|
| 1088 |
|
|
and rbank_wr_addr(3 downto 1) = "100"
|
| 1089 |
|
|
else '0';
|
| 1090 |
|
|
we_rb <= ucode_field2(6) and not inhibit_pc_increment;
|
| 1091 |
|
|
|
| 1092 |
|
|
-- Register bank logic
|
| 1093 |
|
|
-- NOTE: read is asynchronous, while write is synchronous; but note also
|
| 1094 |
|
|
-- that write phase for a given uinst happens the cycle after the read phase.
|
| 1095 |
|
|
-- This way we give the ALU time to do its job.
|
| 1096 |
|
|
rbank_wr_addr <= ucode_field2(18 downto 15);
|
| 1097 |
|
|
process(clk)
|
| 1098 |
|
|
begin
|
| 1099 |
|
|
if clk'event and clk='1' then
|
| 1100 |
|
|
if we_rb = '1' then
|
| 1101 |
|
|
rbank(conv_integer(rbank_wr_addr)) <= alu_output;
|
| 1102 |
|
|
end if;
|
| 1103 |
|
|
end if;
|
| 1104 |
|
|
end process;
|
| 1105 |
|
|
rbank_data <= rbank(conv_integer(rbank_rd_addr));
|
| 1106 |
|
|
|
| 1107 |
|
|
-- should we read F register or ALU output?
|
| 1108 |
|
|
use_psw <= '1' when ucode_field2(5 downto 4)="11" else '0';
|
| 1109 |
|
|
data_output <= flag_reg when use_psw = '1' else alu_output;
|
| 1110 |
|
|
|
| 1111 |
|
|
|
| 1112 |
|
|
process (clk)
|
| 1113 |
|
|
begin
|
| 1114 |
|
|
if clk'event and clk='1' then
|
| 1115 |
|
|
if load_do = '1' then
|
| 1116 |
|
|
DO <= data_output;
|
| 1117 |
|
|
end if;
|
| 1118 |
|
|
end if;
|
| 1119 |
|
|
end process;
|
| 1120 |
|
|
|
| 1121 |
|
|
--##############################################################################
|
| 1122 |
|
|
-- ALU
|
| 1123 |
|
|
|
| 1124 |
|
|
alu_fn <= ucode_field2(1 downto 0);
|
| 1125 |
|
|
use_logic <= ucode_field2(2);
|
| 1126 |
|
|
mux_fn <= ucode_field2(4 downto 3);
|
| 1127 |
|
|
--#### make sure this is "00" in the microcode when no F updates should happen!
|
| 1128 |
|
|
flag_pattern <= ucode_field2(9 downto 8);
|
| 1129 |
|
|
use_aux_cy <= ucode_field2(19);
|
| 1130 |
|
|
do_cpc <= ucode_field2(23);
|
| 1131 |
|
|
do_cy_op <= ucode_field2(24);
|
| 1132 |
54 |
ja_rd |
do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0';
|
| 1133 |
64 |
ja_rd |
|
| 1134 |
|
|
-- ucode_field2(14) will be set for those instructions that modify CY and AC
|
| 1135 |
|
|
-- without following the standard rules -- AND, OR and XOR instructions.
|
| 1136 |
|
|
|
| 1137 |
|
|
-- Some instructions will unconditionally clear CY (AND, OR, XOR)
|
| 1138 |
|
|
clear_cy <= ucode_field2(14);
|
| 1139 |
|
|
|
| 1140 |
|
|
-- Some instructions will unconditionally clear AC (OR, XOR)...
|
| 1141 |
|
|
clear_ac <= '1' when ucode_field2(14) = '1' and
|
| 1142 |
|
|
ucode_field2(5 downto 0) /= "000100"
|
| 1143 |
|
|
else '0';
|
| 1144 |
|
|
-- ...and some others unconditionally SET AC (AND)
|
| 1145 |
|
|
set_ac <= '1' when ucode_field2(14) = '1' and
|
| 1146 |
|
|
ucode_field2(5 downto 0) = "000100"
|
| 1147 |
|
|
else '0';
|
| 1148 |
2 |
ja_rd |
|
| 1149 |
|
|
aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1';
|
| 1150 |
|
|
|
| 1151 |
|
|
-- carry input selection: normal or aux (for 16 bit increments)?
|
| 1152 |
|
|
cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in;
|
| 1153 |
|
|
|
| 1154 |
|
|
-- carry is not used (0) in add/sub operations
|
| 1155 |
|
|
cy_in_gated <= cy_in and alu_fn(0);
|
| 1156 |
|
|
|
| 1157 |
|
|
--##### Adder/substractor
|
| 1158 |
|
|
|
| 1159 |
|
|
-- zero extend adder operands to 9 bits to ease CY output synthesis
|
| 1160 |
|
|
-- use zero extension because we're only interested in cy from 7 to 8
|
| 1161 |
|
|
arith_op1 <= '0' & T2;
|
| 1162 |
|
|
arith_op2 <= '0' & T1;
|
| 1163 |
|
|
|
| 1164 |
|
|
-- The adder/substractor is done in 2 stages to help XSL synth it properly
|
| 1165 |
|
|
-- Other codings result in 1 adder + a substractor + 1 mux
|
| 1166 |
|
|
|
| 1167 |
|
|
-- do 2nd op 2's complement if substracting...
|
| 1168 |
|
|
arith_op2_sgn <= arith_op2 when alu_fn(1) = '0' else not arith_op2;
|
| 1169 |
|
|
-- ...and complement cy input too
|
| 1170 |
|
|
cy_in_sgn <= cy_in_gated when alu_fn(1) = '0' else not cy_in_gated;
|
| 1171 |
|
|
|
| 1172 |
|
|
-- once 2nd operand has been negated (or not) add operands normally
|
| 1173 |
|
|
arith_res <= arith_op1 + arith_op2_sgn + cy_in_sgn;
|
| 1174 |
|
|
|
| 1175 |
|
|
-- take only 8 bits; 9th bit of adder is cy output
|
| 1176 |
|
|
arith_res8 <= arith_res(7 downto 0);
|
| 1177 |
|
|
cy_adder <= arith_res(8);
|
| 1178 |
|
|
|
| 1179 |
|
|
--##### DAA dedicated logic
|
| 1180 |
|
|
-- Note a DAA takes 2 cycles to complete!
|
| 1181 |
|
|
|
| 1182 |
|
|
--daa_test1a='1' when daa_res9(7 downto 4) > 0x06
|
| 1183 |
|
|
daa_test1a <= arith_op2(3) and (arith_op2(2) or arith_op2(1) or arith_op2(0));
|
| 1184 |
|
|
daa_test1 <= '1' when flag_reg(4)='1' or daa_test1a='1' else '0';
|
| 1185 |
|
|
|
| 1186 |
|
|
process(clk)
|
| 1187 |
|
|
begin
|
| 1188 |
|
|
if clk'event and clk='1' then
|
| 1189 |
|
|
if reset='1' then
|
| 1190 |
|
|
daa_res9 <= "000000000";
|
| 1191 |
|
|
else
|
| 1192 |
|
|
if daa_test1='1' then
|
| 1193 |
|
|
daa_res9 <= arith_op2 + "000000110";
|
| 1194 |
|
|
else
|
| 1195 |
|
|
daa_res9 <= arith_op2;
|
| 1196 |
|
|
end if;
|
| 1197 |
|
|
end if;
|
| 1198 |
|
|
end if;
|
| 1199 |
|
|
end process;
|
| 1200 |
|
|
|
| 1201 |
|
|
--daa_test2a='1' when daa_res9(7 downto 4) > 0x06 FIXME unused?
|
| 1202 |
|
|
daa_test2a <= daa_res9(7) and (daa_res9(6) or daa_res9(5) or daa_res9(4));
|
| 1203 |
|
|
daa_test2 <= '1' when flag_reg(0)='1' or daa_test1a='1' else '0';
|
| 1204 |
|
|
|
| 1205 |
|
|
daa_res <= '0'&daa_res9(7 downto 0) + "01100000" when daa_test2='1'
|
| 1206 |
|
|
else daa_res9;
|
| 1207 |
|
|
|
| 1208 |
|
|
cy_daa <= daa_res(8);
|
| 1209 |
|
|
|
| 1210 |
|
|
-- DAA vs. adder mux
|
| 1211 |
|
|
arith_daa_res <= daa_res(7 downto 0) when do_daa='1' else arith_res8;
|
| 1212 |
|
|
|
| 1213 |
|
|
-- DAA vs. adder CY mux
|
| 1214 |
|
|
cy_arith <= cy_daa when do_daa='1' else cy_adder;
|
| 1215 |
|
|
|
| 1216 |
|
|
--##### Logic operations block
|
| 1217 |
|
|
logic_res <= T1 and T2 when alu_fn = "00" else
|
| 1218 |
|
|
T1 xor T2 when alu_fn = "01" else
|
| 1219 |
|
|
T1 or T2 when alu_fn = "10" else
|
| 1220 |
|
|
not T1;
|
| 1221 |
|
|
|
| 1222 |
|
|
--##### Shifter
|
| 1223 |
|
|
shifter:
|
| 1224 |
|
|
for i in 1 to 6 generate
|
| 1225 |
|
|
begin
|
| 1226 |
|
|
shift_res(i) <= T1(i-1) when alu_fn(0) = '0' else T1(i+1);
|
| 1227 |
|
|
end generate;
|
| 1228 |
|
|
shift_res(0) <= T1(7) when alu_fn = "00" else -- rot left
|
| 1229 |
|
|
cy_in when alu_fn = "10" else -- rot left through carry
|
| 1230 |
|
|
T1(1); -- rot right
|
| 1231 |
|
|
shift_res(7) <= T1(0) when alu_fn = "01" else -- rot right
|
| 1232 |
|
|
cy_in when alu_fn = "11" else -- rot right through carry
|
| 1233 |
|
|
T1(6); -- rot left
|
| 1234 |
|
|
|
| 1235 |
|
|
cy_shifter <= T1(7) when alu_fn(0) = '0' else -- left
|
| 1236 |
|
|
T1(0); -- right
|
| 1237 |
|
|
|
| 1238 |
|
|
alu_mux1 <= logic_res when use_logic = '1' else shift_res;
|
| 1239 |
|
|
|
| 1240 |
|
|
|
| 1241 |
|
|
with mux_fn select
|
| 1242 |
|
|
alu_output <= alu_mux1 when "00",
|
| 1243 |
|
|
arith_daa_res when "01",
|
| 1244 |
|
|
not alu_mux1 when "10",
|
| 1245 |
|
|
"00"&d_field&"000" when others; -- RST
|
| 1246 |
|
|
|
| 1247 |
|
|
--###### flag computation
|
| 1248 |
|
|
|
| 1249 |
|
|
flag_s <= alu_output(7);
|
| 1250 |
|
|
flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor
|
| 1251 |
|
|
alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));
|
| 1252 |
|
|
flag_z <= '1' when alu_output=X"00" else '0';
|
| 1253 |
64 |
ja_rd |
-- AC is either the CY from bit 4 OR 0 if the instruction clears it implicitly
|
| 1254 |
|
|
flag_ac <= '1' when set_ac = '1' else
|
| 1255 |
|
|
'0' when clear_ac = '1' else
|
| 1256 |
|
|
(arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4));
|
| 1257 |
2 |
ja_rd |
|
| 1258 |
64 |
ja_rd |
-- CY comes from the adder or the shifter, or is 0 if the instruction
|
| 1259 |
|
|
-- implicitly clears it.
|
| 1260 |
|
|
flag_cy_1 <= '0' when clear_cy = '1' else
|
| 1261 |
|
|
cy_arith when use_logic = '1' and clear_cy = '0' else
|
| 1262 |
54 |
ja_rd |
cy_shifter;
|
| 1263 |
2 |
ja_rd |
flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc
|
| 1264 |
|
|
flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;
|
| 1265 |
|
|
|
| 1266 |
|
|
flag_aux_cy <= cy_adder;
|
| 1267 |
|
|
|
| 1268 |
|
|
-- auxiliary carry reg
|
| 1269 |
|
|
process(clk)
|
| 1270 |
|
|
begin
|
| 1271 |
|
|
if clk'event and clk='1' then
|
| 1272 |
|
|
if reset='1' or uc_decode = '1' then
|
| 1273 |
|
|
reg_aux_cy <= '1'; -- inits to 0 every instruction
|
| 1274 |
|
|
else
|
| 1275 |
|
|
reg_aux_cy <= flag_aux_cy;
|
| 1276 |
|
|
end if;
|
| 1277 |
|
|
end if;
|
| 1278 |
|
|
end process;
|
| 1279 |
|
|
|
| 1280 |
|
|
-- load PSW from ALU (i.e. POP AF) or from flag signals
|
| 1281 |
|
|
load_psw <= '1' when we_rb='1' and rbank_wr_addr="0110" else '0';
|
| 1282 |
|
|
|
| 1283 |
|
|
-- The F register has been split in two separate groupt that always update
|
| 1284 |
|
|
-- together (C and all others).
|
| 1285 |
|
|
|
| 1286 |
|
|
-- F register, flags S,Z,AC,P
|
| 1287 |
|
|
process(clk)
|
| 1288 |
|
|
begin
|
| 1289 |
|
|
if clk'event and clk='1' then
|
| 1290 |
|
|
if reset='1' then
|
| 1291 |
|
|
flag_reg(7) <= '0';
|
| 1292 |
|
|
flag_reg(6) <= '0';
|
| 1293 |
|
|
flag_reg(4) <= '0';
|
| 1294 |
|
|
flag_reg(2) <= '0';
|
| 1295 |
|
|
elsif flag_pattern(1) = '1' then
|
| 1296 |
|
|
if load_psw = '1' then
|
| 1297 |
|
|
flag_reg(7) <= alu_output(7);
|
| 1298 |
|
|
flag_reg(6) <= alu_output(6);
|
| 1299 |
|
|
flag_reg(4) <= alu_output(4);
|
| 1300 |
|
|
flag_reg(2) <= alu_output(2);
|
| 1301 |
|
|
else
|
| 1302 |
|
|
flag_reg(7) <= flag_s;
|
| 1303 |
|
|
flag_reg(6) <= flag_z;
|
| 1304 |
|
|
flag_reg(4) <= flag_ac;
|
| 1305 |
|
|
flag_reg(2) <= flag_p;
|
| 1306 |
|
|
end if;
|
| 1307 |
|
|
end if;
|
| 1308 |
|
|
end if;
|
| 1309 |
|
|
end procesS;
|
| 1310 |
|
|
|
| 1311 |
|
|
-- F register, flag C
|
| 1312 |
|
|
process(clk)
|
| 1313 |
|
|
begin
|
| 1314 |
|
|
if clk'event and clk='1' then
|
| 1315 |
|
|
if reset = '1' then
|
| 1316 |
|
|
flag_reg(0) <= '0';
|
| 1317 |
|
|
elsif flag_pattern(0) = '1' then
|
| 1318 |
|
|
if load_psw = '1' then
|
| 1319 |
|
|
flag_reg(0) <= alu_output(0);
|
| 1320 |
|
|
else
|
| 1321 |
|
|
flag_reg(0) <= flag_cy;
|
| 1322 |
|
|
end if;
|
| 1323 |
|
|
end if;
|
| 1324 |
|
|
end if;
|
| 1325 |
|
|
end procesS;
|
| 1326 |
|
|
|
| 1327 |
|
|
flag_reg(5) <= '0'; -- constant flag
|
| 1328 |
|
|
flag_reg(3) <= '0'; -- constant flag
|
| 1329 |
|
|
flag_reg(1) <= '1'; -- constant flag
|
| 1330 |
|
|
|
| 1331 |
|
|
--##### Condition computation
|
| 1332 |
|
|
|
| 1333 |
|
|
condition_sel <= d_field(2 downto 0);
|
| 1334 |
|
|
with condition_sel select
|
| 1335 |
|
|
condition <=
|
| 1336 |
|
|
not flag_reg(6) when "000", -- NZ
|
| 1337 |
|
|
flag_reg(6) when "001", -- Z
|
| 1338 |
|
|
not flag_reg(0) when "010", -- NC
|
| 1339 |
|
|
flag_reg(0) when "011", -- C
|
| 1340 |
|
|
not flag_reg(2) when "100", -- PO
|
| 1341 |
|
|
flag_reg(2) when "101", -- PE
|
| 1342 |
|
|
not flag_reg(7) when "110", -- P
|
| 1343 |
|
|
flag_reg(7) when others;-- M
|
| 1344 |
|
|
|
| 1345 |
|
|
|
| 1346 |
|
|
-- condition is registered to shorten the delay path; the extra 1-cycle
|
| 1347 |
|
|
-- delay is not relevant because conditions are tested in the next instruction
|
| 1348 |
|
|
-- at the earliest, and there's at least the fetch uinsts intervening.
|
| 1349 |
|
|
process(clk)
|
| 1350 |
|
|
begin
|
| 1351 |
|
|
if clk'event and clk='1' then
|
| 1352 |
|
|
if reset = '1' then
|
| 1353 |
|
|
condition_reg <= '0';
|
| 1354 |
|
|
else
|
| 1355 |
|
|
condition_reg <= condition;
|
| 1356 |
|
|
end if;
|
| 1357 |
|
|
end if;
|
| 1358 |
|
|
end process;
|
| 1359 |
|
|
|
| 1360 |
|
|
-- low byte address register
|
| 1361 |
|
|
process(clk)
|
| 1362 |
|
|
begin
|
| 1363 |
|
|
if clk'event and clk='1' then
|
| 1364 |
|
|
if reset = '1' then
|
| 1365 |
|
|
addr_low <= X"00";
|
| 1366 |
|
|
elsif load_al = '1' then
|
| 1367 |
|
|
addr_low <= rbank_data;
|
| 1368 |
|
|
end if;
|
| 1369 |
|
|
end if;
|
| 1370 |
|
|
end process;
|
| 1371 |
|
|
|
| 1372 |
|
|
-- note external address registers (high byte) are loaded directly from rbank
|
| 1373 |
|
|
addr_out <= rbank_data & addr_low;
|
| 1374 |
|
|
|
| 1375 |
|
|
data_out <= DO;
|
| 1376 |
|
|
|
| 1377 |
|
|
end microcoded;
|
| 1378 |
19 |
ja_rd |
|
| 1379 |
|
|
--------------------------------------------------------------------------------
|
| 1380 |
|
|
-- Timing diagram 1: RD and WR cycles
|
| 1381 |
|
|
--------------------------------------------------------------------------------
|
| 1382 |
|
|
-- 1 2 3 4 5 6 7 8
|
| 1383 |
|
|
-- __ __ __ __ __ __ __ __
|
| 1384 |
|
|
-- clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
|
| 1385 |
|
|
--
|
| 1386 |
39 |
ja_rd |
-- ==|=====|=====|=====|=====|=====|=====|=====|=====|
|
| 1387 |
|
|
--
|
| 1388 |
19 |
ja_rd |
-- addr_o xxxxxxxxxxxxxx< ADR >xxxxxxxxxxx< ADR >xxxxxxxxxxx
|
| 1389 |
|
|
--
|
| 1390 |
|
|
-- data_i xxxxxxxxxxxxxxxxxxxx< Din >xxxxxxxxxxxxxxxxxxxxxxx
|
| 1391 |
|
|
--
|
| 1392 |
|
|
-- data_o xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx< Dout>xxxxxxxxxxx
|
| 1393 |
|
|
-- _____ _____
|
| 1394 |
|
|
-- vma_o ______________/ \___________/ \___________
|
| 1395 |
|
|
-- _____
|
| 1396 |
|
|
-- rd_o ______________/ \_____________________________
|
| 1397 |
|
|
-- _____
|
| 1398 |
|
|
-- wr_o ________________________________/ \___________
|
| 1399 |
|
|
--
|
| 1400 |
|
|
-- (functional diagram, actual time delays not shown)
|
| 1401 |
|
|
--------------------------------------------------------------------------------
|
| 1402 |
|
|
-- This diagram shows a read cycle and a write cycle back to back.
|
| 1403 |
|
|
-- In clock edges (4) and (7), the address is loaded into the external
|
| 1404 |
|
|
-- synchronous RAM address register.
|
| 1405 |
|
|
-- In clock edge (5), read data is loaded into the CPU.
|
| 1406 |
|
|
-- In clock edge (7), write data is loaded into the external synchronous RAM.
|
| 1407 |
|
|
-- In actual operation, the CPU does about 1 rd/wr cycle for each 5 clock
|
| 1408 |
|
|
-- cycles, which is a waste of RAM bandwidth.
|
| 1409 |
|
|
--
|
