1 |
2 |
ja_rd |
--------------------------------------------------------------------------------
|
2 |
21 |
ja_rd |
-- Generated from template tb_template.vhdl by hexconv.pl
|
3 |
2 |
ja_rd |
--------------------------------------------------------------------------------
|
4 |
21 |
ja_rd |
-- Light8080 simulation test bench.
|
5 |
2 |
ja_rd |
--------------------------------------------------------------------------------
|
6 |
21 |
ja_rd |
-- Source for the 8080 program is in asm\tb0.asm
|
7 |
|
|
--------------------------------------------------------------------------------
|
8 |
|
|
--
|
9 |
|
|
-- This test bench provides a simulated CPU system to test programs. This test
|
10 |
|
|
-- bench does not do any assertions or checks, all assertions are left to the
|
11 |
|
|
-- software.
|
12 |
|
|
--
|
13 |
|
|
-- The simulated environment has 2KB of RAM, mirror-mapped to all the memory
|
14 |
|
|
-- map of the 8080, initialized with the test program object code. See the perl
|
15 |
|
|
-- script 'util\hexconv.pl' and BAT files in the asm directory.
|
16 |
|
|
--
|
17 |
|
|
-- Besides, it provides some means to trigger hardware irq from software,
|
18 |
|
|
-- including the specification of the instructions fed to the CPU as interrupt
|
19 |
|
|
-- vectors during inta cycles.
|
20 |
|
|
--
|
21 |
|
|
-- We will simulate 8 possible irq sources. The software can trigger any one of
|
22 |
|
|
-- them by writing at registers 0x010 and 0x011. Register 0x010 holds the irq
|
23 |
|
|
-- source to be triggered (0 to 7) and register 0x011 holds the number of clock
|
24 |
|
|
-- cycles that will elapse from the end of the instruction that writes to the
|
25 |
|
|
-- register to the assertion of intr.
|
26 |
|
|
--
|
27 |
|
|
-- When the interrupt is acknowledged and inta is asserted, the test bench reads
|
28 |
|
|
-- the value at register 0x010 as the irq source, and feeds an instruction to
|
29 |
|
|
-- the CPU starting from the RAM address 0040h+source*4.
|
30 |
|
|
-- That is, address range 0040h-005fh is reserved for the simulated 'interrupt
|
31 |
|
|
-- vectors', a total of 4 bytes for each of the 8 sources. This allows the
|
32 |
|
|
-- software to easily test different interrupt vectors without any hand
|
33 |
|
|
-- assembly. All of this is strictly simulation-only stuff.
|
34 |
|
|
--
|
35 |
|
|
--
|
36 |
|
|
-- Upon completion, the software must write a value to register 0x020. Writing
|
37 |
|
|
-- a 0x055 means 'success', writing a 0x0aa means 'failure'. Success and
|
38 |
|
|
-- failure conditions are defined by the software.
|
39 |
|
|
--------------------------------------------------------------------------------
|
40 |
2 |
ja_rd |
|
41 |
21 |
ja_rd |
library ieee;
|
42 |
|
|
use ieee.std_logic_1164.ALL;
|
43 |
|
|
use ieee.std_logic_unsigned.all;
|
44 |
|
|
use ieee.numeric_std.ALL;
|
45 |
2 |
ja_rd |
|
46 |
21 |
ja_rd |
entity light8080_tb0 is
|
47 |
|
|
end entity light8080_tb0;
|
48 |
2 |
ja_rd |
|
49 |
21 |
ja_rd |
architecture behavior of light8080_tb0 is
|
50 |
2 |
ja_rd |
|
51 |
|
|
--------------------------------------------------------------------------------
|
52 |
|
|
-- Simulation parameters
|
53 |
|
|
|
54 |
21 |
ja_rd |
-- T: simulated clock period
|
55 |
2 |
ja_rd |
constant T : time := 100 ns;
|
56 |
|
|
|
57 |
21 |
ja_rd |
-- MAX_SIM_LENGTH: maximum simulation time
|
58 |
|
|
constant MAX_SIM_LENGTH : time := T*7000; -- enough for the tb0
|
59 |
|
|
|
60 |
|
|
|
61 |
2 |
ja_rd |
--------------------------------------------------------------------------------
|
62 |
|
|
|
63 |
59 |
ja_rd |
-- Component Declaration for the Unit Under Test (UUT)
|
64 |
21 |
ja_rd |
component light8080
|
65 |
|
|
port (
|
66 |
|
|
addr_out : out std_logic_vector(15 downto 0);
|
67 |
|
|
|
68 |
|
|
inta : out std_logic;
|
69 |
|
|
inte : out std_logic;
|
70 |
|
|
halt : out std_logic;
|
71 |
|
|
intr : in std_logic;
|
72 |
|
|
|
73 |
|
|
vma : out std_logic;
|
74 |
|
|
io : out std_logic;
|
75 |
|
|
rd : out std_logic;
|
76 |
|
|
wr : out std_logic;
|
77 |
|
|
fetch : out std_logic;
|
78 |
|
|
data_in : in std_logic_vector(7 downto 0);
|
79 |
|
|
data_out : out std_logic_vector(7 downto 0);
|
80 |
|
|
|
81 |
|
|
clk : in std_logic;
|
82 |
|
|
reset : in std_logic );
|
83 |
|
|
end component;
|
84 |
2 |
ja_rd |
|
85 |
|
|
|
86 |
21 |
ja_rd |
signal data_i : std_logic_vector(7 downto 0) := (others=>'0');
|
87 |
|
|
signal vma_o : std_logic;
|
88 |
|
|
signal rd_o : std_logic;
|
89 |
|
|
signal wr_o : std_logic;
|
90 |
|
|
signal io_o : std_logic;
|
91 |
|
|
signal data_o : std_logic_vector(7 downto 0);
|
92 |
|
|
signal data_mem : std_logic_vector(7 downto 0);
|
93 |
|
|
signal addr_o : std_logic_vector(15 downto 0);
|
94 |
|
|
signal fetch_o : std_logic;
|
95 |
|
|
signal inta_o : std_logic;
|
96 |
|
|
signal inte_o : std_logic;
|
97 |
|
|
signal intr_i : std_logic := '0';
|
98 |
|
|
signal halt_o : std_logic;
|
99 |
|
|
|
100 |
|
|
signal reset : std_logic := '0';
|
101 |
|
|
signal clk : std_logic := '1';
|
102 |
|
|
signal done : std_logic := '0';
|
103 |
2 |
ja_rd |
|
104 |
|
|
type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0);
|
105 |
|
|
|
106 |
|
|
signal rom : t_rom := (
|
107 |
21 |
ja_rd |
|
108 |
|
|
X"31",X"f3",X"05",X"3e",X"77",X"e6",X"00",X"ca",
|
109 |
2 |
ja_rd |
X"0d",X"00",X"cd",X"e0",X"04",X"d2",X"13",X"00",
|
110 |
|
|
X"cd",X"e0",X"04",X"ea",X"19",X"00",X"cd",X"e0",
|
111 |
|
|
X"04",X"f2",X"1f",X"00",X"cd",X"e0",X"04",X"c2",
|
112 |
|
|
X"2e",X"00",X"da",X"2e",X"00",X"e2",X"2e",X"00",
|
113 |
|
|
X"fa",X"2e",X"00",X"c3",X"31",X"00",X"cd",X"e0",
|
114 |
|
|
X"04",X"c6",X"06",X"c2",X"39",X"00",X"cd",X"e0",
|
115 |
|
|
X"04",X"da",X"42",X"00",X"e2",X"42",X"00",X"f2",
|
116 |
|
|
X"45",X"00",X"cd",X"e0",X"04",X"c6",X"70",X"e2",
|
117 |
|
|
X"4d",X"00",X"cd",X"e0",X"04",X"fa",X"56",X"00",
|
118 |
|
|
X"ca",X"56",X"00",X"d2",X"59",X"00",X"cd",X"e0",
|
119 |
|
|
X"04",X"c6",X"81",X"fa",X"61",X"00",X"cd",X"e0",
|
120 |
|
|
X"04",X"ca",X"6a",X"00",X"da",X"6a",X"00",X"e2",
|
121 |
|
|
X"6d",X"00",X"cd",X"e0",X"04",X"c6",X"fe",X"da",
|
122 |
|
|
X"75",X"00",X"cd",X"e0",X"04",X"ca",X"7e",X"00",
|
123 |
|
|
X"e2",X"7e",X"00",X"fa",X"81",X"00",X"cd",X"e0",
|
124 |
|
|
X"04",X"fe",X"00",X"da",X"99",X"00",X"ca",X"99",
|
125 |
|
|
X"00",X"fe",X"f5",X"da",X"99",X"00",X"c2",X"99",
|
126 |
|
|
X"00",X"fe",X"ff",X"ca",X"99",X"00",X"da",X"9c",
|
127 |
|
|
X"00",X"cd",X"e0",X"04",X"ce",X"0a",X"ce",X"0a",
|
128 |
|
|
X"fe",X"0b",X"ca",X"a8",X"00",X"cd",X"e0",X"04",
|
129 |
|
|
X"d6",X"0c",X"d6",X"0f",X"fe",X"f0",X"ca",X"b4",
|
130 |
|
|
X"00",X"cd",X"e0",X"04",X"de",X"f1",X"de",X"0e",
|
131 |
|
|
X"fe",X"f0",X"ca",X"c0",X"00",X"cd",X"e0",X"04",
|
132 |
|
|
X"e6",X"55",X"fe",X"50",X"ca",X"ca",X"00",X"cd",
|
133 |
|
|
X"e0",X"04",X"f6",X"3a",X"fe",X"7a",X"ca",X"d4",
|
134 |
|
|
X"00",X"cd",X"e0",X"04",X"ee",X"0f",X"fe",X"75",
|
135 |
|
|
X"ca",X"de",X"00",X"cd",X"e0",X"04",X"e6",X"00",
|
136 |
|
|
X"dc",X"e0",X"04",X"e4",X"e0",X"04",X"fc",X"e0",
|
137 |
|
|
X"04",X"c4",X"e0",X"04",X"fe",X"00",X"ca",X"f4",
|
138 |
|
|
X"00",X"cd",X"e0",X"04",X"d6",X"77",X"d4",X"e0",
|
139 |
|
|
X"04",X"ec",X"e0",X"04",X"f4",X"e0",X"04",X"cc",
|
140 |
|
|
X"e0",X"04",X"fe",X"89",X"ca",X"0a",X"01",X"cd",
|
141 |
|
|
X"e0",X"04",X"e6",X"ff",X"e4",X"17",X"01",X"fe",
|
142 |
|
|
X"d9",X"ca",X"74",X"01",X"cd",X"e0",X"04",X"e8",
|
143 |
|
|
X"c6",X"10",X"ec",X"23",X"01",X"c6",X"02",X"e0",
|
144 |
|
|
X"cd",X"e0",X"04",X"e0",X"c6",X"20",X"fc",X"2f",
|
145 |
|
|
X"01",X"c6",X"04",X"e8",X"cd",X"e0",X"04",X"f0",
|
146 |
|
|
X"c6",X"80",X"f4",X"3b",X"01",X"c6",X"80",X"f8",
|
147 |
|
|
X"cd",X"e0",X"04",X"f8",X"c6",X"40",X"d4",X"47",
|
148 |
|
|
X"01",X"c6",X"40",X"f0",X"cd",X"e0",X"04",X"d8",
|
149 |
|
|
X"c6",X"8f",X"dc",X"53",X"01",X"d6",X"02",X"d0",
|
150 |
|
|
X"cd",X"e0",X"04",X"d0",X"c6",X"f7",X"c4",X"5f",
|
151 |
|
|
X"01",X"c6",X"fe",X"d8",X"cd",X"e0",X"04",X"c8",
|
152 |
|
|
X"c6",X"01",X"cc",X"6b",X"01",X"c6",X"d0",X"c0",
|
153 |
|
|
X"cd",X"e0",X"04",X"c0",X"c6",X"47",X"fe",X"47",
|
154 |
|
|
X"c8",X"cd",X"e0",X"04",X"3e",X"77",X"3c",X"47",
|
155 |
|
|
X"04",X"48",X"0d",X"51",X"5a",X"63",X"6c",X"7d",
|
156 |
|
|
X"3d",X"4f",X"59",X"6b",X"45",X"50",X"62",X"7c",
|
157 |
|
|
X"57",X"14",X"6a",X"4d",X"0c",X"61",X"44",X"05",
|
158 |
|
|
X"58",X"7b",X"5f",X"1c",X"43",X"60",X"24",X"4c",
|
159 |
|
|
X"69",X"55",X"15",X"7a",X"67",X"25",X"54",X"42",
|
160 |
|
|
X"68",X"2c",X"5d",X"1d",X"4b",X"79",X"6f",X"2d",
|
161 |
|
|
X"65",X"5c",X"53",X"4a",X"41",X"78",X"fe",X"77",
|
162 |
|
|
X"c4",X"e0",X"04",X"af",X"06",X"01",X"0e",X"03",
|
163 |
|
|
X"16",X"07",X"1e",X"0f",X"26",X"1f",X"2e",X"3f",
|
164 |
|
|
X"80",X"81",X"82",X"83",X"84",X"85",X"87",X"fe",
|
165 |
|
|
X"f0",X"c4",X"e0",X"04",X"90",X"91",X"92",X"93",
|
166 |
|
|
X"94",X"95",X"fe",X"78",X"c4",X"e0",X"04",X"97",
|
167 |
|
|
X"c4",X"e0",X"04",X"3e",X"80",X"87",X"06",X"01",
|
168 |
|
|
X"0e",X"02",X"16",X"03",X"1e",X"04",X"26",X"05",
|
169 |
|
|
X"2e",X"06",X"88",X"06",X"80",X"80",X"80",X"89",
|
170 |
|
|
X"80",X"80",X"8a",X"80",X"80",X"8b",X"80",X"80",
|
171 |
|
|
X"8c",X"80",X"80",X"8d",X"80",X"80",X"8f",X"fe",
|
172 |
|
|
X"37",X"c4",X"e0",X"04",X"3e",X"80",X"87",X"06",
|
173 |
|
|
X"01",X"98",X"06",X"ff",X"80",X"99",X"80",X"9a",
|
174 |
|
|
X"80",X"9b",X"80",X"9c",X"80",X"9d",X"fe",X"e0",
|
175 |
|
|
X"c4",X"e0",X"04",X"3e",X"80",X"87",X"9f",X"fe",
|
176 |
|
|
X"ff",X"c4",X"e0",X"04",X"3e",X"ff",X"06",X"fe",
|
177 |
|
|
X"0e",X"fc",X"16",X"ef",X"1e",X"7f",X"26",X"f4",
|
178 |
|
|
X"2e",X"bf",X"a7",X"a1",X"a2",X"a3",X"a4",X"a5",
|
179 |
|
|
X"a7",X"fe",X"24",X"c4",X"e0",X"04",X"af",X"06",
|
180 |
|
|
X"01",X"0e",X"02",X"16",X"04",X"1e",X"08",X"26",
|
181 |
|
|
X"10",X"2e",X"20",X"b0",X"b1",X"b2",X"b3",X"b4",
|
182 |
|
|
X"b5",X"b7",X"fe",X"3f",X"c4",X"e0",X"04",X"3e",
|
183 |
|
|
X"00",X"26",X"8f",X"2e",X"4f",X"a8",X"a9",X"aa",
|
184 |
|
|
X"ab",X"ac",X"ad",X"fe",X"cf",X"c4",X"e0",X"04",
|
185 |
|
|
X"af",X"c4",X"e0",X"04",X"06",X"44",X"0e",X"45",
|
186 |
21 |
ja_rd |
X"16",X"46",X"1e",X"47",X"26",X"04",X"2e",X"ec",
|
187 |
2 |
ja_rd |
X"70",X"06",X"00",X"46",X"3e",X"44",X"b8",X"c4",
|
188 |
|
|
X"e0",X"04",X"72",X"16",X"00",X"56",X"3e",X"46",
|
189 |
|
|
X"ba",X"c4",X"e0",X"04",X"73",X"1e",X"00",X"5e",
|
190 |
|
|
X"3e",X"47",X"bb",X"c4",X"e0",X"04",X"74",X"26",
|
191 |
21 |
ja_rd |
X"04",X"2e",X"ec",X"66",X"3e",X"04",X"bc",X"c4",
|
192 |
|
|
X"e0",X"04",X"75",X"26",X"04",X"2e",X"ec",X"6e",
|
193 |
|
|
X"3e",X"ec",X"bd",X"c4",X"e0",X"04",X"26",X"04",
|
194 |
|
|
X"2e",X"ec",X"3e",X"32",X"77",X"be",X"c4",X"e0",
|
195 |
2 |
ja_rd |
X"04",X"86",X"fe",X"64",X"c4",X"e0",X"04",X"af",
|
196 |
|
|
X"7e",X"fe",X"32",X"c4",X"e0",X"04",X"26",X"04",
|
197 |
21 |
ja_rd |
X"2e",X"ec",X"7e",X"96",X"c4",X"e0",X"04",X"3e",
|
198 |
2 |
ja_rd |
X"80",X"87",X"8e",X"fe",X"33",X"c4",X"e0",X"04",
|
199 |
|
|
X"3e",X"80",X"87",X"9e",X"fe",X"cd",X"c4",X"e0",
|
200 |
|
|
X"04",X"a6",X"c4",X"e0",X"04",X"3e",X"25",X"b6",
|
201 |
|
|
X"fe",X"37",X"c4",X"e0",X"04",X"ae",X"fe",X"05",
|
202 |
|
|
X"c4",X"e0",X"04",X"36",X"55",X"34",X"35",X"86",
|
203 |
|
|
X"fe",X"5a",X"c4",X"e0",X"04",X"01",X"ff",X"12",
|
204 |
|
|
X"11",X"ff",X"12",X"21",X"ff",X"12",X"03",X"13",
|
205 |
|
|
X"23",X"3e",X"13",X"b8",X"c4",X"e0",X"04",X"ba",
|
206 |
|
|
X"c4",X"e0",X"04",X"bc",X"c4",X"e0",X"04",X"3e",
|
207 |
|
|
X"00",X"b9",X"c4",X"e0",X"04",X"bb",X"c4",X"e0",
|
208 |
|
|
X"04",X"bd",X"c4",X"e0",X"04",X"0b",X"1b",X"2b",
|
209 |
|
|
X"3e",X"12",X"b8",X"c4",X"e0",X"04",X"ba",X"c4",
|
210 |
|
|
X"e0",X"04",X"bc",X"c4",X"e0",X"04",X"3e",X"ff",
|
211 |
|
|
X"b9",X"c4",X"e0",X"04",X"bb",X"c4",X"e0",X"04",
|
212 |
21 |
ja_rd |
X"bd",X"c4",X"e0",X"04",X"32",X"ec",X"04",X"af",
|
213 |
|
|
X"3a",X"ec",X"04",X"fe",X"ff",X"c4",X"e0",X"04",
|
214 |
|
|
X"2a",X"ea",X"04",X"22",X"ec",X"04",X"3a",X"ea",
|
215 |
|
|
X"04",X"47",X"3a",X"ec",X"04",X"b8",X"c4",X"e0",
|
216 |
|
|
X"04",X"3a",X"eb",X"04",X"47",X"3a",X"ed",X"04",
|
217 |
|
|
X"b8",X"c4",X"e0",X"04",X"3e",X"aa",X"32",X"ec",
|
218 |
2 |
ja_rd |
X"04",X"44",X"4d",X"af",X"0a",X"fe",X"aa",X"c4",
|
219 |
21 |
ja_rd |
X"e0",X"04",X"3c",X"02",X"3a",X"ec",X"04",X"fe",
|
220 |
|
|
X"ab",X"c4",X"e0",X"04",X"3e",X"77",X"32",X"ec",
|
221 |
|
|
X"04",X"2a",X"ea",X"04",X"11",X"00",X"00",X"eb",
|
222 |
2 |
ja_rd |
X"af",X"1a",X"fe",X"77",X"c4",X"e0",X"04",X"af",
|
223 |
|
|
X"84",X"85",X"c4",X"e0",X"04",X"3e",X"cc",X"12",
|
224 |
21 |
ja_rd |
X"3a",X"ec",X"04",X"fe",X"cc",X"12",X"3a",X"ec",
|
225 |
2 |
ja_rd |
X"04",X"fe",X"cc",X"c4",X"e0",X"04",X"21",X"77",
|
226 |
|
|
X"77",X"29",X"3e",X"ee",X"bc",X"c4",X"e0",X"04",
|
227 |
|
|
X"bd",X"c4",X"e0",X"04",X"21",X"55",X"55",X"01",
|
228 |
|
|
X"ff",X"ff",X"09",X"3e",X"55",X"d4",X"e0",X"04",
|
229 |
|
|
X"bc",X"c4",X"e0",X"04",X"3e",X"54",X"bd",X"c4",
|
230 |
|
|
X"e0",X"04",X"21",X"aa",X"aa",X"11",X"33",X"33",
|
231 |
|
|
X"19",X"3e",X"dd",X"bc",X"c4",X"e0",X"04",X"bd",
|
232 |
|
|
X"c4",X"e0",X"04",X"37",X"d4",X"e0",X"04",X"3f",
|
233 |
|
|
X"dc",X"e0",X"04",X"3e",X"aa",X"2f",X"fe",X"55",
|
234 |
|
|
X"c4",X"e0",X"04",X"b7",X"27",X"fe",X"55",X"c4",
|
235 |
|
|
X"e0",X"04",X"3e",X"88",X"87",X"27",X"fe",X"76",
|
236 |
|
|
X"c4",X"e0",X"04",X"af",X"3e",X"aa",X"27",X"d4",
|
237 |
|
|
X"e0",X"04",X"fe",X"10",X"c4",X"e0",X"04",X"af",
|
238 |
|
|
X"3e",X"9a",X"27",X"d4",X"e0",X"04",X"c4",X"e0",
|
239 |
|
|
X"04",X"37",X"3e",X"42",X"07",X"dc",X"e0",X"04",
|
240 |
|
|
X"07",X"d4",X"e0",X"04",X"fe",X"09",X"c4",X"e0",
|
241 |
|
|
X"04",X"0f",X"d4",X"e0",X"04",X"0f",X"fe",X"42",
|
242 |
|
|
X"c4",X"e0",X"04",X"17",X"17",X"d4",X"e0",X"04",
|
243 |
|
|
X"fe",X"08",X"c4",X"e0",X"04",X"1f",X"1f",X"dc",
|
244 |
|
|
X"e0",X"04",X"fe",X"02",X"c4",X"e0",X"04",X"01",
|
245 |
|
|
X"34",X"12",X"11",X"aa",X"aa",X"21",X"55",X"55",
|
246 |
|
|
X"af",X"c5",X"d5",X"e5",X"f5",X"01",X"00",X"00",
|
247 |
|
|
X"11",X"00",X"00",X"21",X"00",X"00",X"3e",X"c0",
|
248 |
|
|
X"c6",X"f0",X"f1",X"e1",X"d1",X"c1",X"dc",X"e0",
|
249 |
|
|
X"04",X"c4",X"e0",X"04",X"e4",X"e0",X"04",X"fc",
|
250 |
|
|
X"e0",X"04",X"3e",X"12",X"b8",X"c4",X"e0",X"04",
|
251 |
|
|
X"3e",X"34",X"b9",X"c4",X"e0",X"04",X"3e",X"aa",
|
252 |
|
|
X"ba",X"c4",X"e0",X"04",X"bb",X"c4",X"e0",X"04",
|
253 |
|
|
X"3e",X"55",X"bc",X"c4",X"e0",X"04",X"bd",X"c4",
|
254 |
21 |
ja_rd |
X"e0",X"04",X"21",X"00",X"00",X"39",X"22",X"f1",
|
255 |
|
|
X"04",X"31",X"f0",X"04",X"3b",X"3b",X"33",X"3b",
|
256 |
|
|
X"3e",X"55",X"32",X"ee",X"04",X"2f",X"32",X"ef",
|
257 |
2 |
ja_rd |
X"04",X"c1",X"b8",X"c4",X"e0",X"04",X"2f",X"b9",
|
258 |
21 |
ja_rd |
X"c4",X"e0",X"04",X"21",X"f0",X"04",X"f9",X"21",
|
259 |
|
|
X"33",X"77",X"3b",X"3b",X"e3",X"3a",X"ef",X"04",
|
260 |
|
|
X"fe",X"77",X"c4",X"e0",X"04",X"3a",X"ee",X"04",
|
261 |
2 |
ja_rd |
X"fe",X"33",X"c4",X"e0",X"04",X"3e",X"55",X"bd",
|
262 |
|
|
X"c4",X"e0",X"04",X"2f",X"bc",X"c4",X"e0",X"04",
|
263 |
21 |
ja_rd |
X"2a",X"f1",X"04",X"f9",X"21",X"e5",X"04",X"e9",
|
264 |
|
|
X"3e",X"aa",X"d3",X"20",X"76",X"3e",X"55",X"d3",
|
265 |
|
|
X"20",X"76",X"ec",X"04",X"00",X"00",X"00",X"00",
|
266 |
2 |
ja_rd |
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
267 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
268 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
269 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
270 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
271 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
272 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
273 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
274 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
275 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
276 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
277 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
278 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
279 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
280 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
281 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
282 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
283 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
284 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
285 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
286 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
287 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
288 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
289 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
290 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
291 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
292 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
293 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
294 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
295 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
296 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
297 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
298 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
299 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
300 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
301 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
302 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
303 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
304 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
305 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
306 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
307 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
308 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
309 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
310 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
311 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
312 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
313 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
314 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
315 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
316 |
12 |
ja_rd |
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
317 |
2 |
ja_rd |
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
318 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
319 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
320 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
321 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
322 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
323 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
324 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
325 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
326 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
327 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
328 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
329 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
330 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
331 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
332 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
333 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
334 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
335 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
336 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
337 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
338 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
339 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
340 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
341 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
342 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
343 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
344 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
345 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
346 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
347 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
348 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
349 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
350 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
351 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
352 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
353 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
354 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
355 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
356 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
357 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
358 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
359 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
360 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
361 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
362 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
363 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"
|
364 |
|
|
|
365 |
|
|
);
|
366 |
|
|
|
367 |
21 |
ja_rd |
signal irq_vector_byte: std_logic_vector(7 downto 0);
|
368 |
|
|
signal irq_source : integer range 0 to 7;
|
369 |
|
|
signal cycles_to_intr : integer range -10 to 255;
|
370 |
|
|
signal int_vector_index : integer range 0 to 3;
|
371 |
|
|
signal addr_vector_table: integer range 0 to 65535;
|
372 |
2 |
ja_rd |
|
373 |
21 |
ja_rd |
begin
|
374 |
2 |
ja_rd |
|
375 |
59 |
ja_rd |
-- Instantiate the Unit Under Test (UUT)
|
376 |
|
|
uut: light8080 PORT MAP(
|
377 |
|
|
clk => clk,
|
378 |
|
|
reset => reset,
|
379 |
|
|
vma => vma_o,
|
380 |
|
|
rd => rd_o,
|
381 |
|
|
wr => wr_o,
|
382 |
|
|
io => io_o,
|
383 |
|
|
fetch => fetch_o,
|
384 |
|
|
addr_out => addr_o,
|
385 |
|
|
data_in => data_i,
|
386 |
|
|
data_out => data_o,
|
387 |
|
|
|
388 |
|
|
intr => intr_i,
|
389 |
|
|
inte => inte_o,
|
390 |
|
|
inta => inta_o,
|
391 |
|
|
halt => halt_o
|
392 |
|
|
);
|
393 |
2 |
ja_rd |
|
394 |
|
|
|
395 |
21 |
ja_rd |
-- clock: run clock until test is done
|
396 |
|
|
clock:
|
397 |
|
|
process(done, clk)
|
398 |
|
|
begin
|
399 |
59 |
ja_rd |
if done = '0' then
|
400 |
|
|
clk <= not clk after T/2;
|
401 |
|
|
end if;
|
402 |
21 |
ja_rd |
end process clock;
|
403 |
2 |
ja_rd |
|
404 |
|
|
|
405 |
21 |
ja_rd |
-- Drive reset and done
|
406 |
|
|
main_test:
|
407 |
|
|
process
|
408 |
|
|
begin
|
409 |
59 |
ja_rd |
-- Assert reset for at least one full clk period
|
410 |
|
|
reset <= '1';
|
411 |
|
|
wait until clk = '1';
|
412 |
|
|
wait for T/2;
|
413 |
|
|
reset <= '0';
|
414 |
2 |
ja_rd |
|
415 |
59 |
ja_rd |
-- Remember to 'cut away' the preceding 3 clk semiperiods from
|
416 |
|
|
-- the wait statement...
|
417 |
|
|
wait for (MAX_SIM_LENGTH - T*1.5);
|
418 |
2 |
ja_rd |
|
419 |
59 |
ja_rd |
-- Maximum sim time elapsed, assume the program ran away and
|
420 |
|
|
-- stop the clk process asserting 'done' (which will stop the simulation)
|
421 |
|
|
done <= '1';
|
422 |
|
|
|
423 |
21 |
ja_rd |
assert (done = '1')
|
424 |
59 |
ja_rd |
report "Test timed out."
|
425 |
|
|
severity failure;
|
426 |
|
|
|
427 |
|
|
wait;
|
428 |
21 |
ja_rd |
end process main_test;
|
429 |
2 |
ja_rd |
|
430 |
|
|
|
431 |
21 |
ja_rd |
-- Synchronous RAM; 2KB mirrored everywhere
|
432 |
|
|
synchronous_ram:
|
433 |
|
|
process(clk)
|
434 |
|
|
begin
|
435 |
|
|
if (clk'event and clk='1') then
|
436 |
|
|
data_mem <= rom(conv_integer(addr_o(10 downto 0)));
|
437 |
|
|
if wr_o = '1' and addr_o(15 downto 11)="00000" then
|
438 |
|
|
rom(conv_integer(addr_o(10 downto 0))) <= data_o;
|
439 |
|
|
end if;
|
440 |
|
|
end if;
|
441 |
|
|
end process synchronous_ram;
|
442 |
|
|
|
443 |
|
|
|
444 |
|
|
irq_trigger_register:
|
445 |
|
|
process(clk)
|
446 |
|
|
begin
|
447 |
|
|
if (clk'event and clk='1') then
|
448 |
|
|
if reset='1' then
|
449 |
|
|
cycles_to_intr <= -10; -- meaning no interrupt pending
|
450 |
|
|
intr_i <= '0';
|
451 |
|
|
else
|
452 |
|
|
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then
|
453 |
|
|
cycles_to_intr <= conv_integer(data_o) + 1;
|
454 |
|
|
else
|
455 |
|
|
if cycles_to_intr >= 0 then
|
456 |
|
|
cycles_to_intr <= cycles_to_intr - 1;
|
457 |
|
|
end if;
|
458 |
41 |
ja_rd |
if cycles_to_intr = 0 and inta_o = '0' then
|
459 |
21 |
ja_rd |
intr_i <= '1';
|
460 |
41 |
ja_rd |
elsif inta_o = '1' then
|
461 |
21 |
ja_rd |
intr_i <= '0';
|
462 |
|
|
end if;
|
463 |
|
|
end if;
|
464 |
2 |
ja_rd |
end if;
|
465 |
21 |
ja_rd |
end if;
|
466 |
|
|
end process irq_trigger_register;
|
467 |
2 |
ja_rd |
|
468 |
|
|
|
469 |
21 |
ja_rd |
irq_source_register:
|
470 |
|
|
process(clk)
|
471 |
|
|
begin
|
472 |
|
|
if (clk'event and clk='1') then
|
473 |
|
|
if reset='1' then
|
474 |
|
|
irq_source <= 0;
|
475 |
|
|
else
|
476 |
|
|
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"10" then
|
477 |
|
|
irq_source <= conv_integer(data_o(2 downto 0));
|
478 |
|
|
end if;
|
479 |
|
|
end if;
|
480 |
|
|
end if;
|
481 |
|
|
end process irq_source_register;
|
482 |
|
|
|
483 |
|
|
|
484 |
|
|
-- 'interrupt vector' logic.
|
485 |
|
|
irq_vector_table:
|
486 |
|
|
process(clk)
|
487 |
|
|
begin
|
488 |
|
|
if (clk'event and clk='1') then
|
489 |
|
|
if vma_o = '1' and rd_o='1' then
|
490 |
|
|
if inta_o = '1' then
|
491 |
|
|
int_vector_index <= int_vector_index + 1;
|
492 |
|
|
else
|
493 |
|
|
int_vector_index <= 0;
|
494 |
|
|
end if;
|
495 |
|
|
end if;
|
496 |
|
|
-- this is the address of the byte we'll feed to the CPU
|
497 |
|
|
addr_vector_table <= 64+irq_source*4+int_vector_index;
|
498 |
|
|
end if;
|
499 |
|
|
end process irq_vector_table;
|
500 |
|
|
irq_vector_byte <= rom(addr_vector_table);
|
501 |
|
|
|
502 |
|
|
data_i <= data_mem when inta_o='0' else irq_vector_byte;
|
503 |
|
|
|
504 |
|
|
|
505 |
|
|
test_outcome_register:
|
506 |
|
|
process(clk)
|
507 |
|
|
variable outcome : std_logic_vector(7 downto 0);
|
508 |
|
|
begin
|
509 |
|
|
if (clk'event and clk='1') then
|
510 |
|
|
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"20" then
|
511 |
|
|
assert (data_o /= X"55") report "Software reports SUCCESS" severity failure;
|
512 |
|
|
assert (data_o /= X"aa") report "Software reports FAILURE" severity failure;
|
513 |
|
|
assert ((data_o = X"aa") or (data_o = X"55"))
|
514 |
|
|
report "Software reports unexpected outcome value."
|
515 |
|
|
severity failure;
|
516 |
|
|
end if;
|
517 |
|
|
end if;
|
518 |
|
|
end process test_outcome_register;
|
519 |
|
|
|
520 |
|
|
|
521 |
|
|
end;
|