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[/] [light8080/] [trunk/] [vhdl/] [test/] [light8080_tb0.vhdl] - Blame information for rev 80

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1 64 ja_rd 
--------------------------------------------------------------------------------
2 
-- Generated from template tb_template.vhdl by hexconv.pl
3 
--------------------------------------------------------------------------------
4 
-- Light8080 simulation test bench.
5 
--------------------------------------------------------------------------------
6 
-- This test bench was built from a generic template. The details on what tests
7 
-- are performed by this test bench can be found in the assembly source for the
8 
-- 8080 program, in file asm\tb0.asm.
9 
--------------------------------------------------------------------------------
10 
--
11 
-- This test bench provides a simulated CPU system to test programs. This test
12 
-- bench does not do any assertions or checks, all assertions are left to the
13 
-- software.
14 
--
15 
-- The simulated environment has 2KB of RAM, mirror-mapped to all the memory
16 
-- map of the 8080, initialized with the test program object code. See the perl
17 
-- script 'util\hexconv.pl' and BAT files in the asm directory.
18 
--
19 
-- Besides, it provides some means to trigger hardware irq from software,
20 
-- including the specification of the instructions fed to the CPU as interrupt
21 
-- vectors during inta cycles.
22 
--
23 
-- We will simulate 8 possible irq sources. The software can trigger any one of
24 
-- them by writing at ports 0x010 to 0x011. Port 0x010 holds the irq source to
25 
-- be triggered (0 to 7) and port 0x011 holds the number of clock cycles that
26 
-- will elapse from the end of the instruction that writes to the register to
27 
-- the assertion of intr. Port 0x012 holds the number of cycles intr will remain
28 
-- high. Intr will be asserted for 1 cycle at least, so writing a 0 here is the
29 
-- same as writing 1.
30 
--
31 
-- When the interrupt is acknowledged and inta is asserted, the test bench reads
32 
-- the value at register 0x010 as the irq source, and feeds an instruction to
33 
-- the CPU starting from the RAM address 0040h+source*4.
34 
-- That is, address range 0040h-005fh is reserved for the simulated 'interrupt
35 
-- vectors', a total of 4 bytes for each of the 8 sources. This allows the
36 
-- software to easily test different interrupt vectors without any hand
37 
-- assembly. All of this is strictly simulation-only stuff.
38 
--
39 
-- Upon completion, the software must write a value to register 0x020. Writing
40 
-- a 0x055 means 'success', writing a 0x0aa means 'failure'. The write operation
41 
-- will stop the simulation. Success and failure conditions are defined by the
42 
-- software.
43 
--
44 
-- If a time period defined as constant MAX_SIM_LENGTH passes before anything
45 
-- is written to io address 0x020, the test bench assumes the software ran away
46 
-- and quits with an error message.
47 
--------------------------------------------------------------------------------
48 
 
49 
library ieee;
50 
use ieee.std_logic_1164.ALL;
51 
use ieee.std_logic_unsigned.all;
52 
use ieee.numeric_std.ALL;
53 
 
54 
entity light8080_tb0 is
55 
end entity light8080_tb0;
56 
 
57 
architecture behavior of light8080_tb0 is
58 
 
59 
--------------------------------------------------------------------------------
60 
-- Simulation parameters
61 
 
62 
-- T: simulated clock period
63 
constant T : time := 100 ns;
64 
 
65 
-- MAX_SIM_LENGTH: maximum simulation time
66 
constant MAX_SIM_LENGTH : time := T*7000; -- enough for the tb0
67 
 
68 
 
69 
--------------------------------------------------------------------------------
70 
 
71 
-- Component Declaration for the Unit Under Test (UUT)
72 
component light8080
73 
  port (
74 
    addr_out :  out std_logic_vector(15 downto 0);
75 
 
76 
    inta :      out std_logic;
77 
    inte :      out std_logic;
78 
    halt :      out std_logic;
79 
    intr :      in std_logic;
80 
 
81 
    vma :       out std_logic;
82 
    io :        out std_logic;
83 
    rd :        out std_logic;
84 
    wr :        out std_logic;
85 
    fetch :     out std_logic;
86 
    data_in :   in std_logic_vector(7 downto 0);
87 
    data_out :  out std_logic_vector(7 downto 0);
88 
 
89 
    clk :       in std_logic;
90 
    reset :     in std_logic );
91 
end component;
92 
 
93 
 
94 
signal data_i :           std_logic_vector(7 downto 0) := (others=>'0');
95 
signal vma_o  :           std_logic;
96 
signal rd_o :             std_logic;
97 
signal wr_o :             std_logic;
98 
signal io_o :             std_logic;
99 
signal data_o :           std_logic_vector(7 downto 0);
100 
signal data_mem :         std_logic_vector(7 downto 0);
101 
signal addr_o :           std_logic_vector(15 downto 0);
102 
signal fetch_o :          std_logic;
103 
signal inta_o :           std_logic;
104 
signal inte_o :           std_logic;
105 
signal intr_i :           std_logic := '0';
106 
signal halt_o :           std_logic;
107 
 
108 
signal reset :            std_logic := '0';
109 
signal clk :              std_logic := '1';
110 
signal done :             std_logic := '0';
111 
 
112 
type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0);
113 
 
114 
signal rom : t_rom := (
115 
 
116 
X"31",X"1d",X"06",X"3e",X"77",X"e6",X"00",X"ca",
117 
X"0d",X"00",X"cd",X"0a",X"05",X"d2",X"13",X"00",
118 
X"cd",X"0a",X"05",X"ea",X"19",X"00",X"cd",X"0a",
119 
X"05",X"f2",X"1f",X"00",X"cd",X"0a",X"05",X"c2",
120 
X"2e",X"00",X"da",X"2e",X"00",X"e2",X"2e",X"00",
121 
X"fa",X"2e",X"00",X"c3",X"31",X"00",X"cd",X"0a",
122 
X"05",X"c6",X"06",X"c2",X"39",X"00",X"cd",X"0a",
123 
X"05",X"da",X"42",X"00",X"e2",X"42",X"00",X"f2",
124 
X"45",X"00",X"cd",X"0a",X"05",X"c6",X"70",X"e2",
125 
X"4d",X"00",X"cd",X"0a",X"05",X"fa",X"56",X"00",
126 
X"ca",X"56",X"00",X"d2",X"59",X"00",X"cd",X"0a",
127 
X"05",X"c6",X"81",X"fa",X"61",X"00",X"cd",X"0a",
128 
X"05",X"ca",X"6a",X"00",X"da",X"6a",X"00",X"e2",
129 
X"6d",X"00",X"cd",X"0a",X"05",X"c6",X"fe",X"da",
130 
X"75",X"00",X"cd",X"0a",X"05",X"ca",X"7e",X"00",
131 
X"e2",X"7e",X"00",X"fa",X"81",X"00",X"cd",X"0a",
132 
X"05",X"fe",X"00",X"da",X"99",X"00",X"ca",X"99",
133 
X"00",X"fe",X"f5",X"da",X"99",X"00",X"c2",X"99",
134 
X"00",X"fe",X"ff",X"ca",X"99",X"00",X"da",X"9c",
135 
X"00",X"cd",X"0a",X"05",X"ce",X"0a",X"ce",X"0a",
136 
X"fe",X"0b",X"ca",X"a8",X"00",X"cd",X"0a",X"05",
137 
X"d6",X"0c",X"d6",X"0f",X"fe",X"f0",X"ca",X"b4",
138 
X"00",X"cd",X"0a",X"05",X"de",X"f1",X"de",X"0e",
139 
X"fe",X"f0",X"ca",X"c0",X"00",X"cd",X"0a",X"05",
140 
X"e6",X"55",X"dc",X"0a",X"05",X"cc",X"0a",X"05",
141 
X"fe",X"50",X"ca",X"d0",X"00",X"cd",X"0a",X"05",
142 
X"f6",X"3a",X"dc",X"0a",X"05",X"cc",X"0a",X"05",
143 
X"fe",X"7a",X"ca",X"e0",X"00",X"cd",X"0a",X"05",
144 
X"ee",X"0f",X"dc",X"0a",X"05",X"cc",X"0a",X"05",
145 
X"fe",X"75",X"ca",X"f0",X"00",X"cd",X"0a",X"05",
146 
X"e6",X"00",X"dc",X"0a",X"05",X"e4",X"0a",X"05",
147 
X"fc",X"0a",X"05",X"c4",X"0a",X"05",X"fe",X"00",
148 
X"ca",X"06",X"01",X"cd",X"0a",X"05",X"d6",X"77",
149 
X"d4",X"0a",X"05",X"ec",X"0a",X"05",X"f4",X"0a",
150 
X"05",X"cc",X"0a",X"05",X"fe",X"89",X"ca",X"1c",
151 
X"01",X"cd",X"0a",X"05",X"e6",X"ff",X"e4",X"29",
152 
X"01",X"fe",X"d9",X"ca",X"86",X"01",X"cd",X"0a",
153 
X"05",X"e8",X"c6",X"10",X"ec",X"35",X"01",X"c6",
154 
X"02",X"e0",X"cd",X"0a",X"05",X"e0",X"c6",X"20",
155 
X"fc",X"41",X"01",X"c6",X"04",X"e8",X"cd",X"0a",
156 
X"05",X"f0",X"c6",X"80",X"f4",X"4d",X"01",X"c6",
157 
X"80",X"f8",X"cd",X"0a",X"05",X"f8",X"c6",X"40",
158 
X"d4",X"59",X"01",X"c6",X"40",X"f0",X"cd",X"0a",
159 
X"05",X"d8",X"c6",X"8f",X"dc",X"65",X"01",X"d6",
160 
X"02",X"d0",X"cd",X"0a",X"05",X"d0",X"c6",X"f7",
161 
X"c4",X"71",X"01",X"c6",X"fe",X"d8",X"cd",X"0a",
162 
X"05",X"c8",X"c6",X"01",X"cc",X"7d",X"01",X"c6",
163 
X"d0",X"c0",X"cd",X"0a",X"05",X"c0",X"c6",X"47",
164 
X"fe",X"47",X"c8",X"cd",X"0a",X"05",X"3e",X"77",
165 
X"3c",X"47",X"04",X"48",X"0d",X"51",X"5a",X"63",
166 
X"6c",X"7d",X"3d",X"4f",X"59",X"6b",X"45",X"50",
167 
X"62",X"7c",X"57",X"14",X"6a",X"4d",X"0c",X"61",
168 
X"44",X"05",X"58",X"7b",X"5f",X"1c",X"43",X"60",
169 
X"24",X"4c",X"69",X"55",X"15",X"7a",X"67",X"25",
170 
X"54",X"42",X"68",X"2c",X"5d",X"1d",X"4b",X"79",
171 
X"6f",X"2d",X"65",X"5c",X"53",X"4a",X"41",X"78",
172 
X"fe",X"77",X"c4",X"0a",X"05",X"af",X"06",X"01",
173 
X"0e",X"03",X"16",X"07",X"1e",X"0f",X"26",X"1f",
174 
X"2e",X"3f",X"80",X"81",X"82",X"83",X"84",X"85",
175 
X"87",X"fe",X"f0",X"c4",X"0a",X"05",X"90",X"91",
176 
X"92",X"93",X"94",X"95",X"fe",X"78",X"c4",X"0a",
177 
X"05",X"97",X"c4",X"0a",X"05",X"3e",X"80",X"87",
178 
X"06",X"01",X"0e",X"02",X"16",X"03",X"1e",X"04",
179 
X"26",X"05",X"2e",X"06",X"88",X"06",X"80",X"80",
180 
X"80",X"89",X"80",X"80",X"8a",X"80",X"80",X"8b",
181 
X"80",X"80",X"8c",X"80",X"80",X"8d",X"80",X"80",
182 
X"8f",X"fe",X"37",X"c4",X"0a",X"05",X"3e",X"80",
183 
X"87",X"06",X"01",X"98",X"06",X"ff",X"80",X"99",
184 
X"80",X"9a",X"80",X"9b",X"80",X"9c",X"80",X"9d",
185 
X"fe",X"e0",X"c4",X"0a",X"05",X"3e",X"80",X"87",
186 
X"9f",X"fe",X"ff",X"c4",X"0a",X"05",X"3e",X"ff",
187 
X"06",X"fe",X"0e",X"fc",X"16",X"ef",X"1e",X"7f",
188 
X"26",X"f4",X"2e",X"bf",X"37",X"a7",X"dc",X"0a",
189 
X"05",X"a1",X"a2",X"a3",X"a4",X"a5",X"a7",X"fe",
190 
X"24",X"c4",X"0a",X"05",X"af",X"06",X"01",X"0e",
191 
X"02",X"16",X"04",X"1e",X"08",X"26",X"10",X"2e",
192 
X"20",X"37",X"b0",X"dc",X"0a",X"05",X"b1",X"b2",
193 
X"b3",X"b4",X"b5",X"b7",X"fe",X"3f",X"c4",X"0a",
194 
X"05",X"3e",X"00",X"26",X"8f",X"2e",X"4f",X"37",
195 
X"a8",X"dc",X"0a",X"05",X"a9",X"aa",X"ab",X"ac",
196 
X"ad",X"fe",X"cf",X"c4",X"0a",X"05",X"af",X"c4",
197 
X"0a",X"05",X"06",X"44",X"0e",X"45",X"16",X"46",
198 
X"1e",X"47",X"26",X"05",X"2e",X"16",X"70",X"06",
199 
X"00",X"46",X"3e",X"44",X"b8",X"c4",X"0a",X"05",
200 
X"72",X"16",X"00",X"56",X"3e",X"46",X"ba",X"c4",
201 
X"0a",X"05",X"73",X"1e",X"00",X"5e",X"3e",X"47",
202 
X"bb",X"c4",X"0a",X"05",X"74",X"26",X"05",X"2e",
203 
X"16",X"66",X"3e",X"05",X"bc",X"c4",X"0a",X"05",
204 
X"75",X"26",X"05",X"2e",X"16",X"6e",X"3e",X"16",
205 
X"bd",X"c4",X"0a",X"05",X"26",X"05",X"2e",X"16",
206 
X"3e",X"32",X"77",X"be",X"c4",X"0a",X"05",X"86",
207 
X"fe",X"64",X"c4",X"0a",X"05",X"af",X"7e",X"fe",
208 
X"32",X"c4",X"0a",X"05",X"26",X"05",X"2e",X"16",
209 
X"7e",X"96",X"c4",X"0a",X"05",X"3e",X"80",X"87",
210 
X"8e",X"fe",X"33",X"c4",X"0a",X"05",X"3e",X"80",
211 
X"87",X"9e",X"fe",X"cd",X"c4",X"0a",X"05",X"37",
212 
X"a6",X"dc",X"0a",X"05",X"c4",X"0a",X"05",X"3e",
213 
X"25",X"37",X"b6",X"dc",X"0a",X"05",X"fe",X"37",
214 
X"c4",X"0a",X"05",X"37",X"ae",X"dc",X"0a",X"05",
215 
X"fe",X"05",X"c4",X"0a",X"05",X"36",X"55",X"34",
216 
X"35",X"86",X"fe",X"5a",X"c4",X"0a",X"05",X"01",
217 
X"ff",X"12",X"11",X"ff",X"12",X"21",X"ff",X"12",
218 
X"03",X"13",X"23",X"3e",X"13",X"b8",X"c4",X"0a",
219 
X"05",X"ba",X"c4",X"0a",X"05",X"bc",X"c4",X"0a",
220 
X"05",X"3e",X"00",X"b9",X"c4",X"0a",X"05",X"bb",
221 
X"c4",X"0a",X"05",X"bd",X"c4",X"0a",X"05",X"0b",
222 
X"1b",X"2b",X"3e",X"12",X"b8",X"c4",X"0a",X"05",
223 
X"ba",X"c4",X"0a",X"05",X"bc",X"c4",X"0a",X"05",
224 
X"3e",X"ff",X"b9",X"c4",X"0a",X"05",X"bb",X"c4",
225 
X"0a",X"05",X"bd",X"c4",X"0a",X"05",X"32",X"16",
226 
X"05",X"af",X"3a",X"16",X"05",X"fe",X"ff",X"c4",
227 
X"0a",X"05",X"2a",X"14",X"05",X"22",X"16",X"05",
228 
X"3a",X"14",X"05",X"47",X"3a",X"16",X"05",X"b8",
229 
X"c4",X"0a",X"05",X"3a",X"15",X"05",X"47",X"3a",
230 
X"17",X"05",X"b8",X"c4",X"0a",X"05",X"3e",X"aa",
231 
X"32",X"16",X"05",X"44",X"4d",X"af",X"0a",X"fe",
232 
X"aa",X"c4",X"0a",X"05",X"3c",X"02",X"3a",X"16",
233 
X"05",X"fe",X"ab",X"c4",X"0a",X"05",X"3e",X"77",
234 
X"32",X"16",X"05",X"2a",X"14",X"05",X"11",X"00",
235 
X"00",X"eb",X"af",X"1a",X"fe",X"77",X"c4",X"0a",
236 
X"05",X"af",X"84",X"85",X"c4",X"0a",X"05",X"3e",
237 
X"cc",X"12",X"3a",X"16",X"05",X"fe",X"cc",X"12",
238 
X"3a",X"16",X"05",X"fe",X"cc",X"c4",X"0a",X"05",
239 
X"21",X"77",X"77",X"29",X"3e",X"ee",X"bc",X"c4",
240 
X"0a",X"05",X"bd",X"c4",X"0a",X"05",X"21",X"55",
241 
X"55",X"01",X"ff",X"ff",X"09",X"3e",X"55",X"d4",
242 
X"0a",X"05",X"bc",X"c4",X"0a",X"05",X"3e",X"54",
243 
X"bd",X"c4",X"0a",X"05",X"21",X"aa",X"aa",X"11",
244 
X"33",X"33",X"19",X"3e",X"dd",X"bc",X"c4",X"0a",
245 
X"05",X"bd",X"c4",X"0a",X"05",X"37",X"d4",X"0a",
246 
X"05",X"3f",X"dc",X"0a",X"05",X"3e",X"aa",X"2f",
247 
X"fe",X"55",X"c4",X"0a",X"05",X"b7",X"27",X"fe",
248 
X"55",X"c4",X"0a",X"05",X"3e",X"88",X"87",X"27",
249 
X"fe",X"76",X"c4",X"0a",X"05",X"af",X"3e",X"aa",
250 
X"27",X"d4",X"0a",X"05",X"fe",X"10",X"c4",X"0a",
251 
X"05",X"af",X"3e",X"9a",X"27",X"d4",X"0a",X"05",
252 
X"c4",X"0a",X"05",X"37",X"3e",X"42",X"07",X"dc",
253 
X"0a",X"05",X"07",X"d4",X"0a",X"05",X"fe",X"09",
254 
X"c4",X"0a",X"05",X"0f",X"d4",X"0a",X"05",X"0f",
255 
X"fe",X"42",X"c4",X"0a",X"05",X"17",X"17",X"d4",
256 
X"0a",X"05",X"fe",X"08",X"c4",X"0a",X"05",X"1f",
257 
X"1f",X"dc",X"0a",X"05",X"fe",X"02",X"c4",X"0a",
258 
X"05",X"01",X"34",X"12",X"11",X"aa",X"aa",X"21",
259 
X"55",X"55",X"af",X"c5",X"d5",X"e5",X"f5",X"01",
260 
X"00",X"00",X"11",X"00",X"00",X"21",X"00",X"00",
261 
X"3e",X"c0",X"c6",X"f0",X"f1",X"e1",X"d1",X"c1",
262 
X"dc",X"0a",X"05",X"c4",X"0a",X"05",X"e4",X"0a",
263 
X"05",X"fc",X"0a",X"05",X"3e",X"12",X"b8",X"c4",
264 
X"0a",X"05",X"3e",X"34",X"b9",X"c4",X"0a",X"05",
265 
X"3e",X"aa",X"ba",X"c4",X"0a",X"05",X"bb",X"c4",
266 
X"0a",X"05",X"3e",X"55",X"bc",X"c4",X"0a",X"05",
267 
X"bd",X"c4",X"0a",X"05",X"21",X"00",X"00",X"39",
268 
X"22",X"1b",X"05",X"31",X"1a",X"05",X"3b",X"3b",
269 
X"33",X"3b",X"3e",X"55",X"32",X"18",X"05",X"2f",
270 
X"32",X"19",X"05",X"c1",X"b8",X"c4",X"0a",X"05",
271 
X"2f",X"b9",X"c4",X"0a",X"05",X"21",X"1a",X"05",
272 
X"f9",X"21",X"33",X"77",X"3b",X"3b",X"e3",X"3a",
273 
X"19",X"05",X"fe",X"77",X"c4",X"0a",X"05",X"3a",
274 
X"18",X"05",X"fe",X"33",X"c4",X"0a",X"05",X"3e",
275 
X"55",X"bd",X"c4",X"0a",X"05",X"2f",X"bc",X"c4",
276 
X"0a",X"05",X"2a",X"1b",X"05",X"f9",X"21",X"0f",
277 
X"05",X"e9",X"3e",X"aa",X"d3",X"20",X"76",X"3e",
278 
X"55",X"d3",X"20",X"76",X"16",X"05",X"00",X"00",
279 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
280 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
281 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
282 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
283 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
284 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
285 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
286 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
287 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
288 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
289 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
290 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
291 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
292 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
293 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
294 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
295 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
296 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
297 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
298 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
299 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
300 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
301 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
302 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
303 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
304 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
305 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
306 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
307 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
308 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
309 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
310 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
311 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
312 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
313 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
314 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
315 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
316 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
317 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
318 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
319 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
320 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
321 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
322 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
323 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
324 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
325 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
326 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
327 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
328 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
329 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
330 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
331 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
332 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
333 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
334 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
335 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
336 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
337 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
338 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
339 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
340 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
341 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
342 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
343 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
344 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
345 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
346 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
347 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
348 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
349 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
350 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
351 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
352 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
353 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
354 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
355 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
356 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
357 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
358 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
359 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
360 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
361 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
362 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
363 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
364 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
365 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
366 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
367 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
368 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
369 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
370 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
371 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"
372 
 
373 
);
374 
 
375 
signal irq_vector_byte:   std_logic_vector(7 downto 0);
376 
signal irq_source :       integer range 0 to 7;
377 
signal cycles_to_intr :   integer range -10 to 255;
378 
signal intr_width :       integer range 0 to 255;
379 
signal int_vector_index : integer range 0 to 3;
380 
signal addr_vector_table: integer range 0 to 65535;
381 
 
382 
begin
383 
 
384 
  -- Instantiate the Unit Under Test (UUT)
385 
  uut: light8080 PORT MAP(
386 
    clk => clk,
387 
    reset => reset,
388 
    vma => vma_o,
389 
    rd => rd_o,
390 
    wr => wr_o,
391 
    io => io_o,
392 
    fetch => fetch_o,
393 
    addr_out => addr_o,
394 
    data_in => data_i,
395 
    data_out => data_o,
396 
 
397 
    intr => intr_i,
398 
    inte => inte_o,
399 
    inta => inta_o,
400 
    halt => halt_o
401 
  );
402 
 
403 
 
404 
-- clock: run clock until test is done
405 
clock:
406 
process(done, clk)
407 
begin
408 
  if done = '0' then
409 
    clk <= not clk after T/2;
410 
  end if;
411 
end process clock;
412 
 
413 
 
414 
-- Drive reset and done
415 
main_test:
416 
process
417 
begin
418 
  -- Assert reset for at least one full clk period
419 
  reset <= '1';
420 
  wait until clk = '1';
421 
  wait for T/2;
422 
  reset <= '0';
423 
 
424 
  -- Remember to 'cut away' the preceding 3 clk semiperiods from
425 
  -- the wait statement...
426 
  wait for (MAX_SIM_LENGTH - T*1.5);
427 
 
428 
  -- Maximum sim time elapsed, assume the program ran away and
429 
  -- stop the clk process asserting 'done' (which will stop the simulation)
430 
  done <= '1';
431 
 
432 
  assert (done = '1')
433 
  report "Test timed out."
434 
  severity failure;
435 
 
436 
  wait;
437 
end process main_test;
438 
 
439 
 
440 
-- Synchronous RAM; 2KB mirrored everywhere
441 
synchronous_ram:
442 
process(clk)
443 
begin
444 
  if (clk'event and clk='1') then
445 
    data_mem <= rom(conv_integer(addr_o(10 downto 0)));
446 
    if wr_o = '1' and addr_o(15 downto 11)="00000" then
447 
      rom(conv_integer(addr_o(10 downto 0))) <= data_o;
448 
    end if;
449 
  end if;
450 
end process synchronous_ram;
451 
 
452 
 
453 
irq_trigger_register:
454 
process(clk)
455 
begin
456 
  if (clk'event and clk='1') then
457 
    if reset='1' then
458 
      cycles_to_intr <= -10; -- meaning no interrupt pending
459 
    else
460 
      if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then
461 
        cycles_to_intr <= conv_integer(data_o) + 1;
462 
      else
463 
        if cycles_to_intr >= 0 then
464 
          cycles_to_intr <= cycles_to_intr - 1;
465 
        end if;
466 
      end if;
467 
    end if;
468 
  end if;
469 
end process irq_trigger_register;
470 
 
471 
irq_pulse_width_register:
472 
process(clk)
473 
variable intr_pulse_countdown : integer;
474 
begin
475 
  if (clk'event and clk='1') then
476 
    if reset='1' then
477 
      intr_width <= 1;
478 
      intr_pulse_countdown := 0;
479 
      intr_i <= '0';
480 
    else
481 
      if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"12" then
482 
        intr_width <= conv_integer(data_o) + 1;
483 
      end if;
484 
 
485 
      if cycles_to_intr = 0 then
486 
        intr_i <= '1';
487 
        intr_pulse_countdown := intr_width;
488 
      elsif intr_pulse_countdown <= 1 then
489 
        intr_i <= '0';
490 
      else
491 
        intr_pulse_countdown := intr_pulse_countdown - 1;
492 
      end if;
493 
    end if;
494 
  end if;
495 
end process irq_pulse_width_register;
496 
 
497 
irq_source_register:
498 
process(clk)
499 
begin
500 
  if (clk'event and clk='1') then
501 
    if reset='1' then
502 
      irq_source <= 0;
503 
    else
504 
      if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"10" then
505 
        irq_source <= conv_integer(data_o(2 downto 0));
506 
      end if;
507 
    end if;
508 
  end if;
509 
end process irq_source_register;
510 
 
511 
 
512 
-- 'interrupt vector' logic.
513 
irq_vector_table:
514 
process(clk)
515 
begin
516 
  if (clk'event and clk='1') then
517 
    if vma_o = '1' and rd_o='1' then
518 
      if inta_o = '1' then
519 
        int_vector_index <= int_vector_index + 1;
520 
      else
521 
        int_vector_index <= 0;
522 
      end if;
523 
    end if;
524 
    -- this is the address of the byte we'll feed to the CPU
525 
    addr_vector_table <= 64+irq_source*4+int_vector_index;
526 
  end if;
527 
end process irq_vector_table;
528 
irq_vector_byte <= rom(addr_vector_table);
529 
 
530 
data_i <= data_mem when inta_o='0' else irq_vector_byte;
531 
 
532 
 
533 
test_outcome_register:
534 
process(clk)
535 
variable outcome : std_logic_vector(7 downto 0);
536 
begin
537 
  if (clk'event and clk='1') then
538 
    if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"20" then
539 
    assert (data_o /= X"55") report "Software reports SUCCESS" severity failure;
540 
    assert (data_o /= X"aa") report "Software reports FAILURE" severity failure;
541 
    assert ((data_o = X"aa") or (data_o = X"55"))
542 
    report "Software reports unexpected outcome value."
543 
    severity failure;
544 
    end if;
545 
  end if;
546 
end process test_outcome_register;
547 
 
548 
 
549 
end;

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