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URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] [light8080/] [trunk/] [vhdl/] [test/] [light8080_tb1.vhdl] - Blame information for rev 2

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Line No. Rev Author Line
1 2 ja_rd 
--------------------------------------------------------------------------------
2 
-- Light8080 simulation test bench 1 : Interrupt response test
3 
--------------------------------------------------------------------------------
4 
-- Source for the 8080 program is in asm\tb1.asm
5 
-- Upon completion, a value of 055h in ACC means success and a 0aah means
6 
-- failure, but the proper behavior of intr/inta/halt has to be verified
7 
-- visually.
8 
--------------------------------------------------------------------------------
9 
 
10 
LIBRARY ieee;
11 
USE ieee.std_logic_1164.ALL;
12 
USE ieee.std_logic_unsigned.all;
13 
USE ieee.numeric_std.ALL;
14 
 
15 
ENTITY light8080_tb1 IS
16 
END light8080_tb1;
17 
 
18 
ARCHITECTURE behavior OF light8080_tb1 IS
19 
 
20 
--------------------------------------------------------------------------------
21 
-- Simulation parameters
22 
 
23 
-- T: simulation clock period
24 
constant T : time := 100 ns;
25 
 
26 
-- sim_length: total simulation time
27 
constant sim_length : time := 45000 ns;
28 
 
29 
 
30 
--------------------------------------------------------------------------------
31 
 
32 
        -- Component Declaration for the Unit Under Test (UUT)
33 
        COMPONENT light8080
34 
    PORT (
35 
            addr_out :  out std_logic_vector(15 downto 0);
36 
 
37 
            inta :      out std_logic;
38 
            inte :      out std_logic;
39 
            halt :      out std_logic;
40 
            intr :      in std_logic;
41 
 
42 
            vma :       out std_logic;
43 
            io :        out std_logic;
44 
            rd :        out std_logic;
45 
            wr :        out std_logic;
46 
            data_in :   in std_logic_vector(7 downto 0);
47 
            data_out :  out std_logic_vector(7 downto 0);
48 
 
49 
            clk :       in std_logic;
50 
            reset :     in std_logic );
51 
        END COMPONENT;
52 
 
53 
 
54 
SIGNAL data_i :  std_logic_vector(7 downto 0) := (others=>'0');
55 
 
56 
SIGNAL vma_o  :  std_logic;
57 
SIGNAL rd_o  :  std_logic;
58 
SIGNAL wr_o  :  std_logic;
59 
SIGNAL io_o  :  std_logic;
60 
SIGNAL data_o :  std_logic_vector(7 downto 0);
61 
SIGNAL data_mem :  std_logic_vector(7 downto 0);
62 
SIGNAL addr_o :  std_logic_vector(15 downto 0);
63 
 
64 
signal inta_o : std_logic;
65 
signal inte_o : std_logic;
66 
signal intr_i : std_logic := '0';
67 
signal halt_o : std_logic;
68 
 
69 
signal reset    : std_logic := '0';
70 
signal clk      : std_logic := '1';
71 
signal done     : std_logic := '0';
72 
 
73 
type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0);
74 
 
75 
signal rom : t_rom := (
76 
 
77 
X"c3",X"40",X"00",X"00",X"00",X"00",X"00",X"00",
78 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
79 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
80 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
81 
X"c6",X"07",X"fb",X"c9",X"00",X"00",X"00",X"00",
82 
X"47",X"c9",X"00",X"00",X"00",X"00",X"00",X"00",
83 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
84 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
85 
X"31",X"06",X"02",X"fb",X"3e",X"00",X"ef",X"c6",
86 
X"01",X"c6",X"01",X"c6",X"01",X"c6",X"01",X"c6",
87 
X"01",X"c6",X"01",X"c6",X"01",X"fb",X"c6",X"01",
88 
X"c6",X"01",X"c6",X"01",X"fb",X"76",X"fe",X"11",
89 
X"c2",X"7b",X"00",X"78",X"fe",X"00",X"c2",X"7b",
90 
X"00",X"79",X"fe",X"0c",X"c2",X"7b",X"00",X"7a",
91 
X"fe",X"12",X"7b",X"fe",X"34",X"c2",X"7b",X"00",
92 
X"3e",X"55",X"76",X"3e",X"aa",X"76",X"00",X"00",
93 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
94 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
95 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
96 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
97 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
98 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
99 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
100 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
101 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
102 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
103 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
104 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
105 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
106 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
107 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
108 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
109 
X"c6",X"09",X"06",X"77",X"fb",X"c9",X"00",X"00",
110 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
111 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
112 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
113 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
114 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
115 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
116 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
117 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
118 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
119 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
120 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
121 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
122 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
123 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
124 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
125 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
126 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
127 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
128 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
129 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
130 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
131 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
132 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
133 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
134 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
135 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
136 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
137 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
138 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
139 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
140 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
141 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
142 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
143 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
144 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
145 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
146 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
147 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
148 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
149 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
150 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
151 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
152 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
153 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
154 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
155 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
156 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
157 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
158 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
159 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
160 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
161 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
162 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
163 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
164 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
165 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
166 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
167 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
168 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
169 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
170 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
171 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
172 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
173 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
174 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
175 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
176 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
177 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
178 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
179 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
180 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
181 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
182 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
183 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
184 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
185 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
186 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
187 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
188 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
189 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
190 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
191 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
192 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
193 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
194 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
195 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
196 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
197 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
198 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
199 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
200 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
201 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
202 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
203 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
204 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
205 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
206 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
207 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
208 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
209 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
210 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
211 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
212 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
213 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
214 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
215 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
216 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
217 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
218 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
219 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
220 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
221 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
222 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
223 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
224 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
225 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
226 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
227 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
228 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
229 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
230 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
231 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
232 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
233 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
234 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
235 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
236 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
237 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
238 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
239 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
240 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
241 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
242 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
243 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
244 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
245 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
246 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
247 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
248 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
249 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
250 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
251 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
252 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
253 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
254 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
255 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
256 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
257 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
258 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
259 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
260 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
261 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
262 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
263 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
264 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
265 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
266 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
267 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
268 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
269 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
270 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
271 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
272 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
273 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
274 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
275 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
276 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
277 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
278 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
279 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
280 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
281 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
282 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
283 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
284 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
285 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
286 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
287 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
288 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
289 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
290 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
291 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
292 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
293 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
294 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
295 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
296 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
297 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
298 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
299 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
300 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
301 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
302 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
303 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
304 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
305 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
306 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
307 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
308 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
309 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
310 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
311 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
312 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
313 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
314 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
315 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
316 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
317 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
318 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
319 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
320 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
321 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
322 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
323 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
324 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
325 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
326 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
327 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
328 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
329 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
330 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
331 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
332 
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"
333 
 
334 
);
335 
 
336 
 
337 
 
338 
type t_int_vectors is array(0 to 15) of std_logic_vector(7 downto 0);
339 
 
340 
signal int_vectors : t_int_vectors := (
341 
  X"00",                -- not used
342 
  X"e7",                -- rst 4 (rst 20h)
343 
  X"4f",                -- mov c,a
344 
  X"11", X"34", X"12",  -- lxi d, 1234h
345 
  X"00",                -- nop
346 
  X"00",                -- not used
347 
  X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
348 
);
349 
 
350 
signal vector_counter : integer := 0;
351 
signal int_vector : std_logic_vector(7 downto 0);
352 
 
353 
BEGIN
354 
 
355 
        -- Instantiate the Unit Under Test (UUT)
356 
        uut: light8080 PORT MAP(
357 
                clk => clk,
358 
                reset => reset,
359 
                vma => vma_o,
360 
                rd => rd_o,
361 
                wr => wr_o,
362 
                io => io_o,
363 
                addr_out => addr_o,
364 
                data_in => data_i,
365 
                data_out => data_o,
366 
 
367 
                intr => intr_i,
368 
                inte => inte_o,
369 
                inta => inta_o,
370 
                halt => halt_o
371 
        );
372 
 
373 
 
374 
  ---------------------------------------------------------------------------
375 
        -- clock: Clocking process.
376 
        clock:
377 
        process(done, clk)
378 
        begin
379 
                if done = '0' then
380 
                        clk <= not clk after T/2;
381 
                end if;
382 
        end process clock;
383 
 
384 
 
385 
  main_test:
386 
        process
387 
        begin
388 
                -- Assert reset for at least one full clk period
389 
                reset <= '1';
390 
                wait until clk = '1';
391 
                wait for T/2;
392 
                reset <= '0';
393 
 
394 
                -- Remember to 'cut away' the preceding 3 clk semiperiods from
395 
                -- the wait statement...
396 
                wait for (sim_length - T*1.5);
397 
 
398 
                -- Stop the clk process asserting 'done'
399 
                done <= '1';
400 
 
401 
 
402 
          assert (done = '1')
403 
                report "Test finished."
404 
        severity failure;
405 
 
406 
 
407 
                wait;
408 
        end process main_test;
409 
 
410 
  -- RAM access
411 
  process(clk)
412 
  begin
413 
    if (clk'event and clk='1') then
414 
      data_mem <= rom(conv_integer(addr_o(10 downto 0)));
415 
      if wr_o = '1' then
416 
        rom(conv_integer(addr_o(10 downto 0))) <= data_o;
417 
      end if;
418 
    end if;
419 
  end process;
420 
 
421 
  process(clk)
422 
  begin
423 
    if (clk'event and clk='1') then
424 
      if inta_o = '1' and vma_o = '1' and rd_o='1' then
425 
        vector_counter <= vector_counter + 1;
426 
      end if;
427 
    end if;
428 
  end process;
429 
 
430 
  int_vector <= int_vectors(vector_counter);
431 
 
432 
  data_i <= data_mem when inta_o='0' else int_vector;
433 
 
434 
        int0:
435 
        process
436 
        begin
437 
                intr_i <= '0';
438 
 
439 
                --
440 
          wait for T*89;
441 
                intr_i <= '1';
442 
                wait for T;
443 
                intr_i <= '0';
444 
 
445 
                --
446 
          wait for T*87;
447 
                intr_i <= '1';
448 
                wait for T;
449 
                intr_i <= '0';
450 
 
451 
                --
452 
          wait for T*49;
453 
                intr_i <= '1';
454 
                wait for T;
455 
                intr_i <= '0';
456 
 
457 
                -- intr after cpu is halted
458 
          wait for T*41;
459 
                intr_i <= '1';
460 
                wait for T;
461 
                intr_i <= '0';
462 
 
463 
    wait;
464 
        end process int0;
465 
 
466 
END;

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