| 1 |
42 |
ja_rd |
--------------------------------------------------------------------------------
|
| 2 |
|
|
-- Generated from template tb_template.vhdl by hexconv.pl
|
| 3 |
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--------------------------------------------------------------------------------
|
| 4 |
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-- Light8080 simulation test bench.
|
| 5 |
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|
--------------------------------------------------------------------------------
|
| 6 |
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-- This test bench was built from a generic template. The details on what tests
|
| 7 |
|
|
-- are performed by this test bench can be found in the assembly source for the
|
| 8 |
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-- 8080 program, in file asm\tb1.asm.
|
| 9 |
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--------------------------------------------------------------------------------
|
| 10 |
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--
|
| 11 |
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-- This test bench provides a simulated CPU system to test programs. This test
|
| 12 |
|
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-- bench does not do any assertions or checks, all assertions are left to the
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| 13 |
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-- software.
|
| 14 |
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--
|
| 15 |
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-- The simulated environment has 2KB of RAM, mirror-mapped to all the memory
|
| 16 |
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-- map of the 8080, initialized with the test program object code. See the perl
|
| 17 |
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-- script 'util\hexconv.pl' and BAT files in the asm directory.
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| 18 |
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--
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| 19 |
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-- Besides, it provides some means to trigger hardware irq from software,
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| 20 |
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-- including the specification of the instructions fed to the CPU as interrupt
|
| 21 |
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-- vectors during inta cycles.
|
| 22 |
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--
|
| 23 |
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-- We will simulate 8 possible irq sources. The software can trigger any one of
|
| 24 |
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-- them by writing at ports 0x010 to 0x011. Port 0x010 holds the irq source to
|
| 25 |
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|
-- be triggered (0 to 7) and port 0x011 holds the number of clock cycles that
|
| 26 |
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-- will elapse from the end of the instruction that writes to the register to
|
| 27 |
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-- the assertion of intr. Port 0x012 holds the number of cycles intr will remain
|
| 28 |
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-- high. Intr will be asserted for 1 cycle at least, so writing a 0 here is the
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| 29 |
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-- same as writing 1.
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| 30 |
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--
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| 31 |
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-- When the interrupt is acknowledged and inta is asserted, the test bench reads
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| 32 |
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-- the value at register 0x010 as the irq source, and feeds an instruction to
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| 33 |
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-- the CPU starting from the RAM address 0040h+source*4.
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| 34 |
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-- That is, address range 0040h-005fh is reserved for the simulated 'interrupt
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| 35 |
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-- vectors', a total of 4 bytes for each of the 8 sources. This allows the
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| 36 |
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-- software to easily test different interrupt vectors without any hand
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| 37 |
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-- assembly. All of this is strictly simulation-only stuff.
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| 38 |
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--
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| 39 |
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-- Upon completion, the software must write a value to register 0x020. Writing
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| 40 |
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-- a 0x055 means 'success', writing a 0x0aa means 'failure'. The write operation
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| 41 |
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-- will stop the simulation. Success and failure conditions are defined by the
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| 42 |
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-- software.
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| 43 |
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--
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| 44 |
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-- If a time period defined as constant MAX_SIM_LENGTH passes before anything
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| 45 |
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-- is written to io address 0x020, the test bench assumes the software ran away
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| 46 |
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-- and quits with an error message.
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| 47 |
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--------------------------------------------------------------------------------
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| 48 |
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| 49 |
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library ieee;
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| 50 |
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use ieee.std_logic_1164.ALL;
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| 51 |
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.ALL;
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| 53 |
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| 54 |
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entity light8080_tb1 is
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| 55 |
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end entity light8080_tb1;
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| 56 |
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| 57 |
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architecture behavior of light8080_tb1 is
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| 58 |
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| 59 |
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--------------------------------------------------------------------------------
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| 60 |
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-- Simulation parameters
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| 61 |
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| 62 |
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-- T: simulated clock period
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| 63 |
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constant T : time := 100 ns;
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| 64 |
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| 65 |
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-- MAX_SIM_LENGTH: maximum simulation time
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| 66 |
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constant MAX_SIM_LENGTH : time := T*7000; -- enough for the tb0
|
| 67 |
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|
|
| 68 |
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| 69 |
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--------------------------------------------------------------------------------
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| 71 |
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-- Component Declaration for the Unit Under Test (UUT)
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| 72 |
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component light8080
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| 73 |
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port (
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| 74 |
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addr_out : out std_logic_vector(15 downto 0);
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| 75 |
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|
| 76 |
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inta : out std_logic;
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| 77 |
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inte : out std_logic;
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| 78 |
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halt : out std_logic;
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| 79 |
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intr : in std_logic;
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| 80 |
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|
| 81 |
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vma : out std_logic;
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| 82 |
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io : out std_logic;
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| 83 |
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rd : out std_logic;
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| 84 |
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wr : out std_logic;
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| 85 |
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fetch : out std_logic;
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| 86 |
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data_in : in std_logic_vector(7 downto 0);
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| 87 |
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data_out : out std_logic_vector(7 downto 0);
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| 88 |
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| 89 |
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clk : in std_logic;
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| 90 |
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reset : in std_logic );
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| 91 |
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end component;
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| 92 |
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| 93 |
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| 94 |
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signal data_i : std_logic_vector(7 downto 0) := (others=>'0');
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| 95 |
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signal vma_o : std_logic;
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| 96 |
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signal rd_o : std_logic;
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| 97 |
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signal wr_o : std_logic;
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| 98 |
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signal io_o : std_logic;
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| 99 |
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signal data_o : std_logic_vector(7 downto 0);
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| 100 |
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signal data_mem : std_logic_vector(7 downto 0);
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| 101 |
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signal addr_o : std_logic_vector(15 downto 0);
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| 102 |
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signal fetch_o : std_logic;
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| 103 |
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signal inta_o : std_logic;
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| 104 |
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signal inte_o : std_logic;
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| 105 |
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signal intr_i : std_logic := '0';
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| 106 |
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signal halt_o : std_logic;
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| 107 |
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| 108 |
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signal reset : std_logic := '0';
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| 109 |
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signal clk : std_logic := '1';
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| 110 |
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signal done : std_logic := '0';
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| 111 |
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| 112 |
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type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0);
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| 113 |
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| 114 |
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signal rom : t_rom := (
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| 115 |
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| 116 |
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X"c3",X"60",X"00",X"00",X"00",X"00",X"00",X"00",
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| 117 |
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|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 118 |
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|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 119 |
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|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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| 120 |
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|
X"c6",X"01",X"fb",X"c9",X"00",X"00",X"00",X"00",
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| 121 |
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|
X"3c",X"fb",X"c9",X"00",X"00",X"00",X"00",X"00",
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| 122 |
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|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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| 123 |
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|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 124 |
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|
X"3c",X"00",X"00",X"00",X"ef",X"00",X"00",X"00",
|
| 125 |
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|
X"23",X"00",X"00",X"00",X"3e",X"42",X"00",X"00",
|
| 126 |
|
|
X"21",X"34",X"12",X"00",X"c3",X"2f",X"01",X"00",
|
| 127 |
|
|
X"cd",X"34",X"01",X"00",X"cd",X"37",X"01",X"00",
|
| 128 |
|
|
X"31",X"7a",X"01",X"3e",X"13",X"e7",X"fe",X"14",
|
| 129 |
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|
X"c2",X"2a",X"01",X"3e",X"00",X"d3",X"10",X"fb",
|
| 130 |
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|
X"3e",X"14",X"d3",X"11",X"3e",X"27",X"00",X"00",
|
| 131 |
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|
X"00",X"00",X"fe",X"28",X"c2",X"2a",X"01",X"3e",
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| 132 |
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X"01",X"d3",X"10",X"fb",X"3e",X"14",X"d3",X"11",
|
| 133 |
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|
X"3e",X"20",X"00",X"00",X"00",X"00",X"fe",X"21",
|
| 134 |
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X"c2",X"2a",X"01",X"21",X"ff",X"13",X"3e",X"02",
|
| 135 |
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X"d3",X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",
|
| 136 |
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X"00",X"7d",X"fe",X"00",X"c2",X"2a",X"01",X"7c",
|
| 137 |
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X"fe",X"14",X"c2",X"2a",X"01",X"3e",X"03",X"d3",
|
| 138 |
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|
X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",
|
| 139 |
|
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X"fe",X"42",X"c2",X"2a",X"01",X"3e",X"04",X"d3",
|
| 140 |
|
|
X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",
|
| 141 |
|
|
X"7c",X"fe",X"12",X"c2",X"2a",X"01",X"7d",X"fe",
|
| 142 |
|
|
X"34",X"c2",X"2a",X"01",X"3e",X"05",X"d3",X"10",
|
| 143 |
|
|
X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",X"fe",
|
| 144 |
|
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X"79",X"c2",X"2a",X"01",X"3e",X"06",X"d3",X"10",
|
| 145 |
|
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X"fb",X"3e",X"04",X"d3",X"11",X"3c",X"00",X"fe",
|
| 146 |
|
|
X"05",X"c2",X"2a",X"01",X"78",X"fe",X"19",X"c2",
|
| 147 |
|
|
X"2a",X"01",X"f3",X"3e",X"07",X"d3",X"10",X"3e",
|
| 148 |
|
|
X"04",X"d3",X"11",X"00",X"00",X"00",X"3e",X"50",
|
| 149 |
|
|
X"d3",X"12",X"3e",X"01",X"d3",X"10",X"fb",X"3e",
|
| 150 |
|
|
X"14",X"d3",X"11",X"3e",X"27",X"00",X"00",X"3c",
|
| 151 |
|
|
X"00",X"00",X"3c",X"00",X"00",X"00",X"00",X"00",
|
| 152 |
50 |
ja_rd |
X"fe",X"2b",X"c2",X"2a",X"01",X"3e",X"55",X"d3",
|
| 153 |
42 |
ja_rd |
X"20",X"76",X"3e",X"aa",X"d3",X"20",X"76",X"3e",
|
| 154 |
|
|
X"79",X"c3",X"df",X"00",X"06",X"19",X"c9",X"c3",
|
| 155 |
|
|
X"2a",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 156 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 157 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 158 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 159 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 160 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 161 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 162 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 163 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 164 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 165 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 166 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 167 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 168 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 169 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 170 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 171 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 172 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 173 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 174 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 175 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 176 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 177 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 178 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 179 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 180 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 181 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 182 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 183 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 184 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 185 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 186 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 187 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 188 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 189 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 190 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 191 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 192 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 193 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 194 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 195 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 196 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 197 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 198 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 199 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 200 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 201 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 202 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 203 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 204 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 205 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 206 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 207 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 208 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 209 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 210 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 211 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 212 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 213 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 214 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 215 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 216 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 217 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 218 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 219 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 220 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 221 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 222 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 223 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 224 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 225 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 226 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 227 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 228 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 229 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 230 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 231 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 232 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 233 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 234 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 235 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 236 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 237 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 238 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 239 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 240 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 241 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 242 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 243 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 244 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 245 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 246 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 247 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 248 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 249 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 250 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 251 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 252 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 253 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 254 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 255 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 256 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 257 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 258 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 259 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 260 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 261 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 262 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 263 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 264 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 265 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 266 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 267 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 268 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 269 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 270 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 271 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 272 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 273 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 274 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 275 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 276 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 277 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 278 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 279 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 280 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 281 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 282 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 283 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 284 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 285 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 286 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 287 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 288 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 289 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 290 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 291 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 292 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 293 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 294 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 295 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 296 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 297 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 298 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 299 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 300 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 301 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 302 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 303 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 304 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 305 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 306 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 307 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 308 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 309 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 310 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 311 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 312 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 313 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 314 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 315 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 316 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 317 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 318 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 319 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 320 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 321 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 322 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 323 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 324 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 325 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 326 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 327 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 328 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 329 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 330 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 331 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 332 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 333 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 334 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 335 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 336 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 337 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 338 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 339 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 340 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 341 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 342 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 343 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 344 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 345 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 346 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 347 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 348 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 349 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 350 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 351 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 352 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 353 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 354 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 355 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 356 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 357 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 358 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 359 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 360 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 361 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 362 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 363 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 364 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 365 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 366 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 367 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 368 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 369 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 370 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| 371 |
|
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"
|
| 372 |
|
|
|
| 373 |
|
|
);
|
| 374 |
|
|
|
| 375 |
|
|
signal irq_vector_byte: std_logic_vector(7 downto 0);
|
| 376 |
|
|
signal irq_source : integer range 0 to 7;
|
| 377 |
|
|
signal cycles_to_intr : integer range -10 to 255;
|
| 378 |
|
|
signal intr_width : integer range 0 to 255;
|
| 379 |
|
|
signal int_vector_index : integer range 0 to 3;
|
| 380 |
|
|
signal addr_vector_table: integer range 0 to 65535;
|
| 381 |
|
|
|
| 382 |
|
|
begin
|
| 383 |
|
|
|
| 384 |
59 |
ja_rd |
-- Instantiate the Unit Under Test (UUT)
|
| 385 |
|
|
uut: light8080 PORT MAP(
|
| 386 |
|
|
clk => clk,
|
| 387 |
|
|
reset => reset,
|
| 388 |
|
|
vma => vma_o,
|
| 389 |
|
|
rd => rd_o,
|
| 390 |
|
|
wr => wr_o,
|
| 391 |
|
|
io => io_o,
|
| 392 |
|
|
fetch => fetch_o,
|
| 393 |
|
|
addr_out => addr_o,
|
| 394 |
|
|
data_in => data_i,
|
| 395 |
|
|
data_out => data_o,
|
| 396 |
|
|
|
| 397 |
|
|
intr => intr_i,
|
| 398 |
|
|
inte => inte_o,
|
| 399 |
|
|
inta => inta_o,
|
| 400 |
|
|
halt => halt_o
|
| 401 |
|
|
);
|
| 402 |
42 |
ja_rd |
|
| 403 |
|
|
|
| 404 |
|
|
-- clock: run clock until test is done
|
| 405 |
|
|
clock:
|
| 406 |
|
|
process(done, clk)
|
| 407 |
|
|
begin
|
| 408 |
59 |
ja_rd |
if done = '0' then
|
| 409 |
|
|
clk <= not clk after T/2;
|
| 410 |
|
|
end if;
|
| 411 |
42 |
ja_rd |
end process clock;
|
| 412 |
|
|
|
| 413 |
|
|
|
| 414 |
|
|
-- Drive reset and done
|
| 415 |
|
|
main_test:
|
| 416 |
|
|
process
|
| 417 |
|
|
begin
|
| 418 |
59 |
ja_rd |
-- Assert reset for at least one full clk period
|
| 419 |
|
|
reset <= '1';
|
| 420 |
|
|
wait until clk = '1';
|
| 421 |
|
|
wait for T/2;
|
| 422 |
|
|
reset <= '0';
|
| 423 |
42 |
ja_rd |
|
| 424 |
59 |
ja_rd |
-- Remember to 'cut away' the preceding 3 clk semiperiods from
|
| 425 |
|
|
-- the wait statement...
|
| 426 |
|
|
wait for (MAX_SIM_LENGTH - T*1.5);
|
| 427 |
42 |
ja_rd |
|
| 428 |
59 |
ja_rd |
-- Maximum sim time elapsed, assume the program ran away and
|
| 429 |
|
|
-- stop the clk process asserting 'done' (which will stop the simulation)
|
| 430 |
|
|
done <= '1';
|
| 431 |
|
|
|
| 432 |
42 |
ja_rd |
assert (done = '1')
|
| 433 |
59 |
ja_rd |
report "Test timed out."
|
| 434 |
|
|
severity failure;
|
| 435 |
|
|
|
| 436 |
|
|
wait;
|
| 437 |
42 |
ja_rd |
end process main_test;
|
| 438 |
|
|
|
| 439 |
|
|
|
| 440 |
|
|
-- Synchronous RAM; 2KB mirrored everywhere
|
| 441 |
|
|
synchronous_ram:
|
| 442 |
|
|
process(clk)
|
| 443 |
|
|
begin
|
| 444 |
|
|
if (clk'event and clk='1') then
|
| 445 |
|
|
data_mem <= rom(conv_integer(addr_o(10 downto 0)));
|
| 446 |
|
|
if wr_o = '1' and addr_o(15 downto 11)="00000" then
|
| 447 |
|
|
rom(conv_integer(addr_o(10 downto 0))) <= data_o;
|
| 448 |
|
|
end if;
|
| 449 |
|
|
end if;
|
| 450 |
|
|
end process synchronous_ram;
|
| 451 |
|
|
|
| 452 |
|
|
|
| 453 |
|
|
irq_trigger_register:
|
| 454 |
|
|
process(clk)
|
| 455 |
|
|
begin
|
| 456 |
|
|
if (clk'event and clk='1') then
|
| 457 |
|
|
if reset='1' then
|
| 458 |
|
|
cycles_to_intr <= -10; -- meaning no interrupt pending
|
| 459 |
|
|
else
|
| 460 |
|
|
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then
|
| 461 |
|
|
cycles_to_intr <= conv_integer(data_o) + 1;
|
| 462 |
|
|
else
|
| 463 |
|
|
if cycles_to_intr >= 0 then
|
| 464 |
|
|
cycles_to_intr <= cycles_to_intr - 1;
|
| 465 |
|
|
end if;
|
| 466 |
|
|
end if;
|
| 467 |
|
|
end if;
|
| 468 |
|
|
end if;
|
| 469 |
|
|
end process irq_trigger_register;
|
| 470 |
|
|
|
| 471 |
|
|
irq_pulse_width_register:
|
| 472 |
|
|
process(clk)
|
| 473 |
|
|
variable intr_pulse_countdown : integer;
|
| 474 |
|
|
begin
|
| 475 |
|
|
if (clk'event and clk='1') then
|
| 476 |
|
|
if reset='1' then
|
| 477 |
|
|
intr_width <= 1;
|
| 478 |
|
|
intr_pulse_countdown := 0;
|
| 479 |
|
|
intr_i <= '0';
|
| 480 |
|
|
else
|
| 481 |
|
|
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"12" then
|
| 482 |
|
|
intr_width <= conv_integer(data_o) + 1;
|
| 483 |
|
|
end if;
|
| 484 |
|
|
|
| 485 |
|
|
if cycles_to_intr = 0 then
|
| 486 |
|
|
intr_i <= '1';
|
| 487 |
|
|
intr_pulse_countdown := intr_width;
|
| 488 |
|
|
elsif intr_pulse_countdown <= 1 then
|
| 489 |
|
|
intr_i <= '0';
|
| 490 |
|
|
else
|
| 491 |
|
|
intr_pulse_countdown := intr_pulse_countdown - 1;
|
| 492 |
|
|
end if;
|
| 493 |
|
|
end if;
|
| 494 |
|
|
end if;
|
| 495 |
|
|
end process irq_pulse_width_register;
|
| 496 |
|
|
|
| 497 |
|
|
irq_source_register:
|
| 498 |
|
|
process(clk)
|
| 499 |
|
|
begin
|
| 500 |
|
|
if (clk'event and clk='1') then
|
| 501 |
|
|
if reset='1' then
|
| 502 |
|
|
irq_source <= 0;
|
| 503 |
|
|
else
|
| 504 |
|
|
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"10" then
|
| 505 |
|
|
irq_source <= conv_integer(data_o(2 downto 0));
|
| 506 |
|
|
end if;
|
| 507 |
|
|
end if;
|
| 508 |
|
|
end if;
|
| 509 |
|
|
end process irq_source_register;
|
| 510 |
|
|
|
| 511 |
|
|
|
| 512 |
|
|
-- 'interrupt vector' logic.
|
| 513 |
|
|
irq_vector_table:
|
| 514 |
|
|
process(clk)
|
| 515 |
|
|
begin
|
| 516 |
|
|
if (clk'event and clk='1') then
|
| 517 |
|
|
if vma_o = '1' and rd_o='1' then
|
| 518 |
|
|
if inta_o = '1' then
|
| 519 |
|
|
int_vector_index <= int_vector_index + 1;
|
| 520 |
|
|
else
|
| 521 |
|
|
int_vector_index <= 0;
|
| 522 |
|
|
end if;
|
| 523 |
|
|
end if;
|
| 524 |
|
|
-- this is the address of the byte we'll feed to the CPU
|
| 525 |
|
|
addr_vector_table <= 64+irq_source*4+int_vector_index;
|
| 526 |
|
|
end if;
|
| 527 |
|
|
end process irq_vector_table;
|
| 528 |
|
|
irq_vector_byte <= rom(addr_vector_table);
|
| 529 |
|
|
|
| 530 |
|
|
data_i <= data_mem when inta_o='0' else irq_vector_byte;
|
| 531 |
|
|
|
| 532 |
|
|
|
| 533 |
|
|
test_outcome_register:
|
| 534 |
|
|
process(clk)
|
| 535 |
|
|
variable outcome : std_logic_vector(7 downto 0);
|
| 536 |
|
|
begin
|
| 537 |
|
|
if (clk'event and clk='1') then
|
| 538 |
|
|
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"20" then
|
| 539 |
|
|
assert (data_o /= X"55") report "Software reports SUCCESS" severity failure;
|
| 540 |
|
|
assert (data_o /= X"aa") report "Software reports FAILURE" severity failure;
|
| 541 |
|
|
assert ((data_o = X"aa") or (data_o = X"55"))
|
| 542 |
|
|
report "Software reports unexpected outcome value."
|
| 543 |
|
|
severity failure;
|
| 544 |
|
|
end if;
|
| 545 |
|
|
end if;
|
| 546 |
|
|
end process test_outcome_register;
|
| 547 |
|
|
|
| 548 |
|
|
|
| 549 |
|
|
end;
|
