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1 20 ja_rd
--------------------------------------------------------------------------------
2
-- Light8080 simulation test bench.
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--------------------------------------------------------------------------------
4 40 ja_rd
-- This test bench was built from a generic template. The details on what tests
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-- are performed by this test bench can be found in the assembly source for the 
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-- 8080 program, in file asm\@PROGNAME@.asm.
7 20 ja_rd
-------------------------------------------------------------------------------- 
8
-- 
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-- This test bench provides a simulated CPU system to test programs. This test 
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-- bench does not do any assertions or checks, all assertions are left to the 
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-- software.
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--
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-- The simulated environment has 2KB of RAM, mirror-mapped to all the memory 
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-- map of the 8080, initialized with the test program object code. See the perl
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-- script 'util\hexconv.pl' and BAT files in the asm directory.
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--
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-- Besides, it provides some means to trigger hardware irq from software, 
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-- including the specification of the instructions fed to the CPU as interrupt
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-- vectors during inta cycles.
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--
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-- We will simulate 8 possible irq sources. The software can trigger any one of 
22 40 ja_rd
-- them by writing at ports 0x010 to 0x011. Port 0x010 holds the irq source to 
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-- be triggered (0 to 7) and port 0x011 holds the number of clock cycles that 
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-- will elapse from the end of the instruction that writes to the register to 
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-- the assertion of intr. Port 0x012 holds the number of cycles intr will remain 
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-- high. Intr will be asserted for 1 cycle at least, so writing a 0 here is the 
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-- same as writing 1.
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--
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-- When the interrupt is acknowledged and inta is asserted, the test bench reads
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-- the value at register 0x010 as the irq source, and feeds an instruction to 
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-- the CPU starting from the RAM address 0040h+source*4.
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-- That is, address range 0040h-005fh is reserved for the simulated 'interrupt
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-- vectors', a total of 4 bytes for each of the 8 sources. This allows the 
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-- software to easily test different interrupt vectors without any hand 
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-- assembly. All of this is strictly simulation-only stuff.
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--
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-- Upon completion, the software must write a value to register 0x020. Writing 
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-- a 0x055 means 'success', writing a 0x0aa means 'failure'. The write operation
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-- will stop the simulation. Success and failure conditions are defined by the 
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-- software.
41 20 ja_rd
--
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-- If a time period defined as constant MAX_SIM_LENGTH passes before anything
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-- is written to io address 0x020, the test bench assumes the software ran away
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-- and quits with an error message.
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--------------------------------------------------------------------------------
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47
library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.ALL;
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entity light8080_@PROGNAME@ is
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end entity light8080_@PROGNAME@;
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architecture behavior of light8080_@PROGNAME@ is
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57
--------------------------------------------------------------------------------
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-- Simulation parameters
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-- T: simulated clock period
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constant T : time := 100 ns;
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-- MAX_SIM_LENGTH: maximum simulation time
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constant MAX_SIM_LENGTH : time := T*7000; -- enough for the tb0
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66
 
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--------------------------------------------------------------------------------
68
 
69 40 ja_rd
-- Component Declaration for the Unit Under Test (UUT)
70 20 ja_rd
component light8080
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  port (
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    addr_out :  out std_logic_vector(15 downto 0);
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    inta :      out std_logic;
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    inte :      out std_logic;
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    halt :      out std_logic;
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    intr :      in std_logic;
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    vma :       out std_logic;
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    io :        out std_logic;
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    rd :        out std_logic;
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    wr :        out std_logic;
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    fetch :     out std_logic;
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    data_in :   in std_logic_vector(7 downto 0);
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    data_out :  out std_logic_vector(7 downto 0);
86
 
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    clk :       in std_logic;
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    reset :     in std_logic );
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end component;
90
 
91
 
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signal data_i :           std_logic_vector(7 downto 0) := (others=>'0');
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signal vma_o  :           std_logic;
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signal rd_o :             std_logic;
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signal wr_o :             std_logic;
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signal io_o :             std_logic;
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signal data_o :           std_logic_vector(7 downto 0);
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signal data_mem :         std_logic_vector(7 downto 0);
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signal addr_o :           std_logic_vector(15 downto 0);
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signal fetch_o :          std_logic;
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signal inta_o :           std_logic;
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signal inte_o :           std_logic;
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signal intr_i :           std_logic := '0';
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signal halt_o :           std_logic;
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signal reset :            std_logic := '0';
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signal clk :              std_logic := '1';
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signal done :             std_logic := '0';
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type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0);
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signal rom : t_rom := (
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114
--@rom_data
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116
);
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signal irq_vector_byte:   std_logic_vector(7 downto 0);
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signal irq_source :       integer range 0 to 7;
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signal cycles_to_intr :   integer range -10 to 255;
121 40 ja_rd
signal intr_width :       integer range 0 to 255;
122 20 ja_rd
signal int_vector_index : integer range 0 to 3;
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signal addr_vector_table: integer range 0 to 65535;
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125
begin
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        -- Instantiate the Unit Under Test (UUT)
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        uut: light8080 PORT MAP(
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                clk => clk,
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                reset => reset,
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                vma => vma_o,
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                rd => rd_o,
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                wr => wr_o,
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                io => io_o,
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                fetch => fetch_o,
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                addr_out => addr_o,
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                data_in => data_i,
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                data_out => data_o,
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                intr => intr_i,
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                inte => inte_o,
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                inta => inta_o,
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                halt => halt_o
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        );
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-- clock: run clock until test is done
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clock:
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process(done, clk)
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begin
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        if done = '0' then
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                clk <= not clk after T/2;
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        end if;
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end process clock;
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-- Drive reset and done 
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main_test:
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process
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begin
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        -- Assert reset for at least one full clk period
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        reset <= '1';
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        wait until clk = '1';
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        wait for T/2;
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        reset <= '0';
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        -- Remember to 'cut away' the preceding 3 clk semiperiods from 
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        -- the wait statement...
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        wait for (MAX_SIM_LENGTH - T*1.5);
170
 
171
        -- Maximum sim time elapsed, assume the program ran away and
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        -- stop the clk process asserting 'done' (which will stop the simulation)
173
        done <= '1';
174
 
175
  assert (done = '1')
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        report "Test timed out."
177
        severity failure;
178
 
179
        wait;
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end process main_test;
181
 
182
 
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-- Synchronous RAM; 2KB mirrored everywhere
184
synchronous_ram:
185
process(clk)
186
begin
187
  if (clk'event and clk='1') then
188
    data_mem <= rom(conv_integer(addr_o(10 downto 0)));
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    if wr_o = '1' and addr_o(15 downto 11)="00000" then
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      rom(conv_integer(addr_o(10 downto 0))) <= data_o;
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    end if;
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  end if;
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end process synchronous_ram;
194
 
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irq_trigger_register:
197
process(clk)
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begin
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  if (clk'event and clk='1') then
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    if reset='1' then
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      cycles_to_intr <= -10; -- meaning no interrupt pending
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    else
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      if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then
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        cycles_to_intr <= conv_integer(data_o) + 1;
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      else
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        if cycles_to_intr >= 0 then
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          cycles_to_intr <= cycles_to_intr - 1;
208
        end if;
209
      end if;
210
    end if;
211
  end if;
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end process irq_trigger_register;
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214 40 ja_rd
irq_pulse_width_register:
215
process(clk)
216
variable intr_pulse_countdown : integer;
217
begin
218
  if (clk'event and clk='1') then
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    if reset='1' then
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      intr_width <= 1;
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      intr_pulse_countdown := 0;
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      intr_i <= '0';
223
    else
224
      if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"12" then
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        intr_width <= conv_integer(data_o) + 1;
226
      end if;
227 20 ja_rd
 
228 40 ja_rd
      if cycles_to_intr = 0 then
229
        intr_i <= '1';
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        intr_pulse_countdown := intr_width;
231
      elsif intr_pulse_countdown <= 1 then
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        intr_i <= '0';
233
      else
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        intr_pulse_countdown := intr_pulse_countdown - 1;
235
      end if;
236
    end if;
237
  end if;
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end process irq_pulse_width_register;
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240 20 ja_rd
irq_source_register:
241
process(clk)
242
begin
243
  if (clk'event and clk='1') then
244
    if reset='1' then
245
      irq_source <= 0;
246
    else
247
      if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"10" then
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        irq_source <= conv_integer(data_o(2 downto 0));
249
      end if;
250
    end if;
251
  end if;
252
end process irq_source_register;
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255
-- 'interrupt vector' logic.
256
irq_vector_table:
257
process(clk)
258
begin
259
  if (clk'event and clk='1') then
260
    if vma_o = '1' and rd_o='1' then
261
      if inta_o = '1' then
262
        int_vector_index <= int_vector_index + 1;
263
      else
264
        int_vector_index <= 0;
265
      end if;
266
    end if;
267
    -- this is the address of the byte we'll feed to the CPU
268
    addr_vector_table <= 64+irq_source*4+int_vector_index;
269
  end if;
270
end process irq_vector_table;
271
irq_vector_byte <= rom(addr_vector_table);
272
 
273
data_i <= data_mem when inta_o='0' else irq_vector_byte;
274
 
275
 
276
test_outcome_register:
277
process(clk)
278
variable outcome : std_logic_vector(7 downto 0);
279
begin
280
  if (clk'event and clk='1') then
281
    if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"20" then
282
    assert (data_o /= X"55") report "Software reports SUCCESS" severity failure;
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    assert (data_o /= X"aa") report "Software reports FAILURE" severity failure;
284
    assert ((data_o = X"aa") or (data_o = X"55"))
285
    report "Software reports unexpected outcome value."
286
    severity failure;
287
    end if;
288
  end if;
289
end process test_outcome_register;
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end;

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